^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is dual-licensed; you may select either version 2 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License ("GPL") or BSD license ("BSD").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This Synopsys DWC XLGMAC software driver and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (hereinafter the "Software") is an unsupported proprietary work of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Synopsys, Inc. unless otherwise expressly agreed to in writing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Synopsys and you. The Software IS NOT an item of Licensed Software or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Licensed Product under any End User Software License Agreement or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Agreement for Licensed Products with Synopsys or any supplement thereto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Synopsys is a registered trademark of Synopsys, Inc. Other names included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * in the SOFTWARE may be the trademarks of their respective owners.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __DWC_XLGMAC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __DWC_XLGMAC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XLGMAC_DRV_NAME "dwc-xlgmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XLGMAC_DRV_VERSION "1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XLGMAC_DRV_DESC "Synopsys DWC XLGMAC Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Descriptor related parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XLGMAC_TX_DESC_CNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XLGMAC_TX_DESC_MIN_FREE (XLGMAC_TX_DESC_CNT >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XLGMAC_TX_DESC_MAX_PROC (XLGMAC_TX_DESC_CNT >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XLGMAC_RX_DESC_CNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XLGMAC_RX_DESC_MAX_DIRTY (XLGMAC_RX_DESC_CNT >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Descriptors required for maximum contiguous TSO/GSO packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XLGMAC_TX_MAX_SPLIT ((GSO_MAX_SIZE / XLGMAC_TX_MAX_BUF_SIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Maximum possible descriptors needed for a SKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XLGMAC_TX_MAX_DESC_NR (MAX_SKB_FRAGS + XLGMAC_TX_MAX_SPLIT + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XLGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XLGMAC_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XLGMAC_RX_BUF_ALIGN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Maximum Size for Splitting the Header Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Keep in sync with SKB_ALLOC_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 3'b000: 64 bytes, 3'b001: 128 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 3'b010: 256 bytes, 3'b011: 512 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 3'b100: 1023 bytes , 3'b101'3'b111: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define XLGMAC_SPH_HDSMS_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XLGMAC_SKB_ALLOC_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XLGMAC_MAX_FIFO 81920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XLGMAC_MAX_DMA_CHANNELS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XLGMAC_DMA_STOP_TIMEOUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define XLGMAC_DMA_INTERRUPT_MASK 0x31c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Default coalescing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XLGMAC_INIT_DMA_TX_USECS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XLGMAC_INIT_DMA_TX_FRAMES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XLGMAC_INIT_DMA_RX_USECS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XLGMAC_INIT_DMA_RX_FRAMES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XLGMAC_MAX_DMA_RIWT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XLGMAC_MIN_DMA_RIWT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Flow control queue count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XLGMAC_MAX_FLOW_CONTROL_QUEUES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* System clock is 125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XLGMAC_SYSCLOCK 125000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Maximum MAC address hash table size (256 bits = 8 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XLGMAC_MAC_HASH_TABLE_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Receive Side Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XLGMAC_RSS_HASH_KEY_SIZE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XLGMAC_RSS_MAX_TABLE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XLGMAC_RSS_LOOKUP_TABLE_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XLGMAC_RSS_HASH_KEY_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XLGMAC_STD_PACKET_MTU 1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XLGMAC_JUMBO_PACKET_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Helper macro for descriptor handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Always use XLGMAC_GET_DESC_DATA to access the descriptor data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XLGMAC_GET_DESC_DATA(ring, idx) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typeof(ring) _ring = (ring); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ((_ring)->desc_data_head + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ((idx) & ((_ring)->dma_desc_count - 1))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XLGMAC_GET_REG_BITS(var, pos, len) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) typeof(pos) _pos = (pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) typeof(len) _len = (len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XLGMAC_GET_REG_BITS_LE(var, pos, len) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typeof(pos) _pos = (pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) typeof(len) _len = (len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) typeof(var) _var = le32_to_cpu((var)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) typeof(var) _var = (var); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) typeof(pos) _pos = (pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) typeof(len) _len = (len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) typeof(val) _val = (val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) typeof(var) _var = (var); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) typeof(pos) _pos = (pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) typeof(len) _len = (len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) typeof(val) _val = (val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cpu_to_le32(_var); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct xlgmac_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum xlgmac_int {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) XLGMAC_INT_DMA_CH_SR_TI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) XLGMAC_INT_DMA_CH_SR_TPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) XLGMAC_INT_DMA_CH_SR_TBU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) XLGMAC_INT_DMA_CH_SR_RI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) XLGMAC_INT_DMA_CH_SR_RBU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) XLGMAC_INT_DMA_CH_SR_RPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) XLGMAC_INT_DMA_CH_SR_TI_RI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) XLGMAC_INT_DMA_CH_SR_FBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) XLGMAC_INT_DMA_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct xlgmac_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* MMC TX counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u64 txoctetcount_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 txframecount_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u64 txbroadcastframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u64 txmulticastframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u64 tx64octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 tx65to127octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 tx128to255octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u64 tx256to511octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 tx512to1023octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u64 tx1024tomaxoctets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u64 txunicastframes_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u64 txmulticastframes_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u64 txbroadcastframes_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u64 txunderflowerror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u64 txoctetcount_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u64 txframecount_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u64 txpauseframes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u64 txvlanframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* MMC RX counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u64 rxframecount_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u64 rxoctetcount_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u64 rxoctetcount_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 rxbroadcastframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 rxmulticastframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u64 rxcrcerror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 rxrunterror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u64 rxjabbererror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u64 rxundersize_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u64 rxoversize_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u64 rx64octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u64 rx65to127octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u64 rx128to255octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u64 rx256to511octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u64 rx512to1023octets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u64 rx1024tomaxoctets_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u64 rxunicastframes_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u64 rxlengtherror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u64 rxoutofrangetype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u64 rxpauseframes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u64 rxfifooverflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u64 rxvlanframes_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u64 rxwatchdogerror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Extra counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u64 tx_tso_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u64 rx_split_header_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 tx_process_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u64 rx_process_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u64 tx_buffer_unavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u64 rx_buffer_unavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u64 fatal_bus_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u64 tx_vlan_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u64 rx_vlan_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u64 napi_poll_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 napi_poll_txtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct xlgmac_ring_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dma_addr_t skb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int skb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Common Tx and Rx DMA hardware descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct xlgmac_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le32 desc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __le32 desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le32 desc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le32 desc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Page allocation related values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct xlgmac_page_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct page *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int pages_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int pages_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dma_addr_t pages_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Ring entry buffer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct xlgmac_buffer_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct xlgmac_page_alloc pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct xlgmac_page_alloc pa_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_addr_t dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Tx-related desc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct xlgmac_tx_desc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int packets; /* BQL packet count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int bytes; /* BQL byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Rx-related desc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct xlgmac_rx_desc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct xlgmac_buffer_data hdr; /* Header locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct xlgmac_buffer_data buf; /* Payload locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned short hdr_len; /* Length of received header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned short len; /* Length of received packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct xlgmac_pkt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int attributes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* descriptors needed for this packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int header_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int tcp_header_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int tcp_payload_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned short mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned short vlan_ctag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u64 rx_tstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 rss_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enum pkt_hash_types rss_hash_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct xlgmac_desc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* dma_desc: Virtual address of descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * dma_desc_addr: DMA address of descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct xlgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dma_addr_t dma_desc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* skb: Virtual address of SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * skb_dma: DMA address of SKB data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * skb_dma_len: Length of SKB DMA area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma_addr_t skb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int skb_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Tx/Rx -related data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct xlgmac_tx_desc_data tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct xlgmac_rx_desc_data rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int mapped_as_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Incomplete receive save location. If the budget is exhausted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * or the last descriptor (last normal descriptor or a following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * context descriptor) has not been DMA'd yet the current state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * of the receive processing needs to be saved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int state_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct xlgmac_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Per packet related information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct xlgmac_pkt_info pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Virtual/DMA addresses of DMA descriptor list and the total count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct xlgmac_dma_desc *dma_desc_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dma_addr_t dma_desc_head_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int dma_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Array of descriptor data corresponding the DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * (always use the XLGMAC_GET_DESC_DATA macro to access this data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct xlgmac_desc_data *desc_data_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Page allocation for RX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct xlgmac_page_alloc rx_hdr_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct xlgmac_page_alloc rx_buf_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Ring index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * cur - Tx: index of descriptor to be used for current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Rx: index of descriptor to check for packet availability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * dirty - Tx: index of descriptor to check for transfer complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Rx: index of descriptor to check for buffer reallocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Coalesce frame count used for interrupt bit setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int coalesce_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int xmit_more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int queue_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned short cur_mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned short cur_vlan_ctag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct xlgmac_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Address of private data area for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct xlgmac_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Queue index and base address of queue's DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int queue_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void __iomem *dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Per channel interrupt irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) char dma_irq_name[IFNAMSIZ + 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Netdev related settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int saved_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int tx_timer_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct timer_list tx_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct xlgmac_ring *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct xlgmac_ring *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct xlgmac_desc_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int (*alloc_channles_and_rings)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void (*free_channels_and_rings)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int (*map_tx_skb)(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int (*map_rx_buffer)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct xlgmac_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct xlgmac_desc_data *desc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void (*unmap_desc_data)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct xlgmac_desc_data *desc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void (*tx_desc_init)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void (*rx_desc_init)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct xlgmac_hw_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int (*init)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int (*exit)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int (*tx_complete)(struct xlgmac_dma_desc *dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void (*enable_tx)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) void (*disable_tx)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void (*enable_rx)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void (*disable_rx)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int (*enable_int)(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum xlgmac_int int_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int (*disable_int)(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) enum xlgmac_int int_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void (*dev_xmit)(struct xlgmac_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int (*dev_read)(struct xlgmac_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int (*set_mac_address)(struct xlgmac_pdata *pdata, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int (*config_rx_mode)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int (*enable_rx_csum)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int (*disable_rx_csum)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* For MII speed configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int (*set_xlgmii_25000_speed)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int (*set_xlgmii_40000_speed)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int (*set_xlgmii_50000_speed)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int (*set_xlgmii_100000_speed)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* For descriptor related operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void (*tx_desc_init)(struct xlgmac_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void (*rx_desc_init)(struct xlgmac_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void (*tx_desc_reset)(struct xlgmac_desc_data *desc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void (*rx_desc_reset)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct xlgmac_desc_data *desc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int (*is_last_desc)(struct xlgmac_dma_desc *dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int (*is_context_desc)(struct xlgmac_dma_desc *dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void (*tx_start_xmit)(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct xlgmac_ring *ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* For Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int (*config_tx_flow_control)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int (*config_rx_flow_control)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* For Vlan related config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int (*enable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int (*disable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int (*enable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int (*disable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int (*update_vlan_hash_table)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* For RX coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int (*config_rx_coalesce)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int (*config_tx_coalesce)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int (*usec_to_riwt)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int (*riwt_to_usec)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int riwt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* For RX and TX threshold config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int (*config_rx_threshold)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int (*config_tx_threshold)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* For RX and TX Store and Forward Mode config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int (*config_rsf_mode)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int (*config_tsf_mode)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* For TX DMA Operate on Second Frame config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int (*config_osp_mode)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* For RX and TX PBL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int (*config_rx_pbl_val)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int (*get_rx_pbl_val)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int (*config_tx_pbl_val)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int (*get_tx_pbl_val)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int (*config_pblx8)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* For MMC statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void (*rx_mmc_int)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void (*tx_mmc_int)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void (*read_mmc_stats)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* For Receive Side Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int (*enable_rss)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int (*disable_rss)(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int (*set_rss_hash_key)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const u8 *key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int (*set_rss_lookup_table)(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) const u32 *table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* This structure contains flags that indicate what hardware features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * or configurations are present in the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct xlgmac_hw_features {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* HW Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* HW Feature Register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int phyifsel; /* PHY interface support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int vlhash; /* VLAN Hash Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int sma; /* SMA(MDIO) Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int rwk; /* PMT remote wake-up packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int mgk; /* PMT magic packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int mmc; /* RMON module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int aoe; /* ARP Offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int eee; /* Energy Efficient Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int tx_coe; /* Tx Checksum Offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int rx_coe; /* Rx Checksum Offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int addn_mac; /* Additional MAC Addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int ts_src; /* Timestamp Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* HW Feature Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int adv_ts_hi; /* Advance Timestamping High Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int dma_width; /* DMA width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int dcb; /* DCB Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int sph; /* Split Header Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int tso; /* TCP Segmentation Offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int dma_debug; /* DMA Debug Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int rss; /* Receive Side Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int tc_cnt; /* Number of Traffic Classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned int hash_table_size; /* Hash Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* HW Feature Register2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int pps_out_num; /* Number of PPS outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct xlgmac_resources {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct xlgmac_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct xlgmac_hw_ops hw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct xlgmac_desc_ops desc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Device statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct xlgmac_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* MAC registers base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void __iomem *mac_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Hardware features of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct xlgmac_hw_features hw_feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct work_struct restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Rings for Tx/Rx on a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct xlgmac_channel *channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int channel_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int tx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int rx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int tx_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int rx_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int tx_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int rx_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Tx/Rx common settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int pblx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Tx settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int tx_sf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int tx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int tx_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int tx_osp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Rx settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int rx_sf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int rx_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Tx coalescing settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int tx_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int tx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Rx coalescing settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int rx_riwt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int rx_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int rx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Current Rx buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int rx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Flow control settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned int tx_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int rx_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Device interrupt number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int dev_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int per_channel_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int channel_irq[XLGMAC_MAX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Netdev related settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned char mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) netdev_features_t netdev_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Filtering support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Device clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned long sysclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* RSS addressing mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct mutex rss_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Receive Side Scaling settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 rss_key[XLGMAC_RSS_HASH_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 rss_table[XLGMAC_RSS_MAX_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 rss_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int phy_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) char drv_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) char drv_ver[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) void xlgmac_init_desc_ops(struct xlgmac_desc_ops *desc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) const struct net_device_ops *xlgmac_get_netdev_ops(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) const struct ethtool_ops *xlgmac_get_ethtool_ops(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct xlgmac_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct xlgmac_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void xlgmac_print_pkt(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct sk_buff *skb, bool tx_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int xlgmac_drv_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct xlgmac_resources *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int xlgmac_drv_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* For debug prints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef XLGMAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define XLGMAC_PR(fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define XLGMAC_PR(x...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #endif /* __DWC_XLGMAC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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