^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is dual-licensed; you may select either version 2 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License ("GPL") or BSD license ("BSD").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This Synopsys DWC XLGMAC software driver and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (hereinafter the "Software") is an unsupported proprietary work of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Synopsys, Inc. unless otherwise expressly agreed to in writing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Synopsys and you. The Software IS NOT an item of Licensed Software or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Licensed Product under any End User Software License Agreement or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Agreement for Licensed Products with Synopsys or any supplement thereto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Synopsys is a registered trademark of Synopsys, Inc. Other names included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * in the SOFTWARE may be the trademarks of their respective owners.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __DWC_XLGMAC_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __DWC_XLGMAC_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* MAC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAC_TCR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAC_RCR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAC_PFR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAC_HTR0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAC_VLANTR 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAC_VLANHTR 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAC_VLANIR 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAC_Q0TFCR 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAC_RFCR 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAC_RQC0R 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAC_RQC1R 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAC_RQC2R 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAC_RQC3R 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAC_ISR 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAC_IER 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAC_VR 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAC_HWF0R 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAC_HWF1R 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAC_HWF2R 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAC_MACA0HR 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAC_MACA0LR 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAC_MACA1HR 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAC_MACA1LR 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAC_RSSCR 0x0c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAC_RSSAR 0x0c88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAC_RSSDR 0x0c8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAC_QTFCR_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAC_MACA_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAC_HTR_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAC_RQC2_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAC_RQC2_Q_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* MAC register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAC_HWF0R_ADDMACADRSEL_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAC_HWF0R_ADDMACADRSEL_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAC_HWF0R_ARPOFFSEL_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAC_HWF0R_ARPOFFSEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAC_HWF0R_EEESEL_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAC_HWF0R_EEESEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAC_HWF0R_PHYIFSEL_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAC_HWF0R_PHYIFSEL_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MAC_HWF0R_MGKSEL_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAC_HWF0R_MGKSEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAC_HWF0R_MMCSEL_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAC_HWF0R_MMCSEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAC_HWF0R_RWKSEL_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAC_HWF0R_RWKSEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAC_HWF0R_RXCOESEL_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAC_HWF0R_RXCOESEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAC_HWF0R_SAVLANINS_POS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAC_HWF0R_SAVLANINS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAC_HWF0R_SMASEL_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAC_HWF0R_SMASEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAC_HWF0R_TSSEL_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAC_HWF0R_TSSEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAC_HWF0R_TSSTSSEL_POS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAC_HWF0R_TSSTSSEL_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAC_HWF0R_TXCOESEL_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAC_HWF0R_TXCOESEL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MAC_HWF0R_VLHASH_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAC_HWF0R_VLHASH_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAC_HWF1R_ADDR64_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAC_HWF1R_ADDR64_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAC_HWF1R_ADVTHWORD_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAC_HWF1R_ADVTHWORD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAC_HWF1R_DBGMEMA_POS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAC_HWF1R_DBGMEMA_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAC_HWF1R_DCBEN_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAC_HWF1R_DCBEN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAC_HWF1R_HASHTBLSZ_POS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAC_HWF1R_HASHTBLSZ_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAC_HWF1R_L3L4FNUM_POS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MAC_HWF1R_L3L4FNUM_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MAC_HWF1R_NUMTC_POS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAC_HWF1R_NUMTC_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MAC_HWF1R_RSSEN_POS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAC_HWF1R_RSSEN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAC_HWF1R_RXFIFOSIZE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAC_HWF1R_RXFIFOSIZE_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAC_HWF1R_SPHEN_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAC_HWF1R_SPHEN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAC_HWF1R_TSOEN_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAC_HWF1R_TSOEN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAC_HWF1R_TXFIFOSIZE_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MAC_HWF1R_TXFIFOSIZE_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAC_HWF2R_AUXSNAPNUM_POS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAC_HWF2R_AUXSNAPNUM_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAC_HWF2R_PPSOUTNUM_POS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAC_HWF2R_PPSOUTNUM_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MAC_HWF2R_RXCHCNT_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MAC_HWF2R_RXCHCNT_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAC_HWF2R_RXQCNT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MAC_HWF2R_RXQCNT_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MAC_HWF2R_TXCHCNT_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MAC_HWF2R_TXCHCNT_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAC_HWF2R_TXQCNT_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MAC_HWF2R_TXQCNT_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MAC_IER_TSIE_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MAC_IER_TSIE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAC_ISR_MMCRXIS_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAC_ISR_MMCRXIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAC_ISR_MMCTXIS_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAC_ISR_MMCTXIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAC_ISR_PMTIS_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAC_ISR_PMTIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MAC_ISR_TSIS_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MAC_ISR_TSIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MAC_MACA1HR_AE_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MAC_MACA1HR_AE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAC_PFR_HMC_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAC_PFR_HMC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MAC_PFR_HPF_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MAC_PFR_HPF_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MAC_PFR_HUC_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MAC_PFR_HUC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MAC_PFR_PM_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MAC_PFR_PM_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MAC_PFR_PR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MAC_PFR_PR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MAC_PFR_VTFE_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MAC_PFR_VTFE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAC_Q0TFCR_PT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MAC_Q0TFCR_PT_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MAC_Q0TFCR_TFE_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MAC_Q0TFCR_TFE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MAC_RCR_ACS_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MAC_RCR_ACS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MAC_RCR_CST_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAC_RCR_CST_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MAC_RCR_DCRCC_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MAC_RCR_DCRCC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAC_RCR_HDSMS_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MAC_RCR_HDSMS_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MAC_RCR_IPC_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MAC_RCR_IPC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MAC_RCR_JE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MAC_RCR_JE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MAC_RCR_LM_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MAC_RCR_LM_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MAC_RCR_RE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAC_RCR_RE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAC_RFCR_PFCE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MAC_RFCR_PFCE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAC_RFCR_RFE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAC_RFCR_RFE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MAC_RFCR_UP_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MAC_RFCR_UP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAC_RQC0R_RXQ0EN_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MAC_RQC0R_RXQ0EN_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MAC_RSSAR_ADDRT_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAC_RSSAR_ADDRT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAC_RSSAR_CT_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MAC_RSSAR_CT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MAC_RSSAR_OB_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MAC_RSSAR_OB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAC_RSSAR_RSSIA_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MAC_RSSAR_RSSIA_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MAC_RSSCR_IP2TE_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAC_RSSCR_IP2TE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MAC_RSSCR_RSSE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MAC_RSSCR_RSSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MAC_RSSCR_TCP4TE_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MAC_RSSCR_TCP4TE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MAC_RSSCR_UDP4TE_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAC_RSSCR_UDP4TE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MAC_RSSDR_DMCH_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MAC_RSSDR_DMCH_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MAC_TCR_SS_POS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MAC_TCR_SS_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MAC_TCR_TE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MAC_TCR_TE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MAC_VLANHTR_VLHT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MAC_VLANHTR_VLHT_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MAC_VLANIR_VLTI_POS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MAC_VLANIR_VLTI_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MAC_VLANIR_CSVL_POS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MAC_VLANIR_CSVL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MAC_VLANTR_DOVLTC_POS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MAC_VLANTR_DOVLTC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MAC_VLANTR_ERSVLM_POS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MAC_VLANTR_ERSVLM_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MAC_VLANTR_ESVL_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MAC_VLANTR_ESVL_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MAC_VLANTR_ETV_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MAC_VLANTR_ETV_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MAC_VLANTR_EVLS_POS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MAC_VLANTR_EVLS_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MAC_VLANTR_EVLRXS_POS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MAC_VLANTR_EVLRXS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MAC_VLANTR_VL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MAC_VLANTR_VL_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MAC_VLANTR_VTHM_POS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MAC_VLANTR_VTHM_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MAC_VLANTR_VTIM_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MAC_VLANTR_VTIM_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MAC_VR_DEVID_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MAC_VR_DEVID_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MAC_VR_SNPSVER_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MAC_VR_SNPSVER_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MAC_VR_USERVER_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MAC_VR_USERVER_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* MMC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MMC_CR 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MMC_RISR 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MMC_TISR 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MMC_RIER 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MMC_TIER 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MMC_TXOCTETCOUNT_GB_LO 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MMC_TXFRAMECOUNT_GB_LO 0x081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MMC_TX64OCTETS_GB_LO 0x0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MMC_TX65TO127OCTETS_GB_LO 0x083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MMC_TX128TO255OCTETS_GB_LO 0x0844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MMC_TX256TO511OCTETS_GB_LO 0x084c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MMC_TXUNDERFLOWERROR_LO 0x087c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MMC_TXOCTETCOUNT_G_LO 0x0884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MMC_TXFRAMECOUNT_G_LO 0x088c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MMC_TXPAUSEFRAMES_LO 0x0894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MMC_TXVLANFRAMES_G_LO 0x089c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MMC_RXFRAMECOUNT_GB_LO 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MMC_RXOCTETCOUNT_GB_LO 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MMC_RXOCTETCOUNT_G_LO 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MMC_RXCRCERROR_LO 0x0928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MMC_RXRUNTERROR 0x0930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MMC_RXJABBERERROR 0x0934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MMC_RXUNDERSIZE_G 0x0938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MMC_RXOVERSIZE_G 0x093c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MMC_RX64OCTETS_GB_LO 0x0940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MMC_RX65TO127OCTETS_GB_LO 0x0948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MMC_RX128TO255OCTETS_GB_LO 0x0950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MMC_RX256TO511OCTETS_GB_LO 0x0958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MMC_RXUNICASTFRAMES_G_LO 0x0970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MMC_RXLENGTHERROR_LO 0x0978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MMC_RXOUTOFRANGETYPE_LO 0x0980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MMC_RXPAUSEFRAMES_LO 0x0988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MMC_RXFIFOOVERFLOW_LO 0x0990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MMC_RXVLANFRAMES_GB_LO 0x0998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MMC_RXWATCHDOGERROR 0x09a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* MMC register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MMC_CR_CR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MMC_CR_CR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MMC_CR_CSR_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MMC_CR_CSR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MMC_CR_ROR_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MMC_CR_ROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MMC_CR_MCF_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MMC_CR_MCF_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MMC_CR_MCT_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MMC_CR_MCT_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MMC_RIER_ALL_INTERRUPTS_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MMC_RIER_ALL_INTERRUPTS_LEN 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MMC_RISR_RXFRAMECOUNT_GB_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MMC_RISR_RXFRAMECOUNT_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MMC_RISR_RXOCTETCOUNT_GB_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MMC_RISR_RXOCTETCOUNT_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MMC_RISR_RXOCTETCOUNT_G_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MMC_RISR_RXOCTETCOUNT_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MMC_RISR_RXBROADCASTFRAMES_G_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MMC_RISR_RXBROADCASTFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MMC_RISR_RXMULTICASTFRAMES_G_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MMC_RISR_RXMULTICASTFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MMC_RISR_RXCRCERROR_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MMC_RISR_RXCRCERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MMC_RISR_RXRUNTERROR_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MMC_RISR_RXRUNTERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MMC_RISR_RXJABBERERROR_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MMC_RISR_RXJABBERERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MMC_RISR_RXUNDERSIZE_G_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MMC_RISR_RXUNDERSIZE_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MMC_RISR_RXOVERSIZE_G_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MMC_RISR_RXOVERSIZE_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MMC_RISR_RX64OCTETS_GB_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MMC_RISR_RX64OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MMC_RISR_RX65TO127OCTETS_GB_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MMC_RISR_RX65TO127OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MMC_RISR_RX128TO255OCTETS_GB_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MMC_RISR_RX128TO255OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MMC_RISR_RX256TO511OCTETS_GB_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MMC_RISR_RX256TO511OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MMC_RISR_RX512TO1023OCTETS_GB_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MMC_RISR_RX512TO1023OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MMC_RISR_RX1024TOMAXOCTETS_GB_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MMC_RISR_RX1024TOMAXOCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MMC_RISR_RXUNICASTFRAMES_G_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MMC_RISR_RXUNICASTFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MMC_RISR_RXLENGTHERROR_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MMC_RISR_RXLENGTHERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MMC_RISR_RXOUTOFRANGETYPE_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MMC_RISR_RXOUTOFRANGETYPE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MMC_RISR_RXPAUSEFRAMES_POS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MMC_RISR_RXPAUSEFRAMES_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MMC_RISR_RXFIFOOVERFLOW_POS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MMC_RISR_RXFIFOOVERFLOW_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MMC_RISR_RXVLANFRAMES_GB_POS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MMC_RISR_RXVLANFRAMES_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MMC_RISR_RXWATCHDOGERROR_POS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MMC_RISR_RXWATCHDOGERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MMC_TIER_ALL_INTERRUPTS_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MMC_TIER_ALL_INTERRUPTS_LEN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MMC_TISR_TXOCTETCOUNT_GB_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MMC_TISR_TXOCTETCOUNT_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MMC_TISR_TXFRAMECOUNT_GB_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MMC_TISR_TXFRAMECOUNT_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MMC_TISR_TXBROADCASTFRAMES_G_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MMC_TISR_TXBROADCASTFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MMC_TISR_TXMULTICASTFRAMES_G_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MMC_TISR_TXMULTICASTFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MMC_TISR_TX64OCTETS_GB_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MMC_TISR_TX64OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MMC_TISR_TX65TO127OCTETS_GB_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MMC_TISR_TX65TO127OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MMC_TISR_TX128TO255OCTETS_GB_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MMC_TISR_TX128TO255OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MMC_TISR_TX256TO511OCTETS_GB_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MMC_TISR_TX256TO511OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MMC_TISR_TX512TO1023OCTETS_GB_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MMC_TISR_TX512TO1023OCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MMC_TISR_TX1024TOMAXOCTETS_GB_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MMC_TISR_TX1024TOMAXOCTETS_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MMC_TISR_TXUNICASTFRAMES_GB_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MMC_TISR_TXUNICASTFRAMES_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MMC_TISR_TXMULTICASTFRAMES_GB_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MMC_TISR_TXMULTICASTFRAMES_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MMC_TISR_TXBROADCASTFRAMES_GB_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MMC_TISR_TXBROADCASTFRAMES_GB_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MMC_TISR_TXUNDERFLOWERROR_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MMC_TISR_TXUNDERFLOWERROR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MMC_TISR_TXOCTETCOUNT_G_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MMC_TISR_TXOCTETCOUNT_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MMC_TISR_TXFRAMECOUNT_G_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MMC_TISR_TXFRAMECOUNT_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MMC_TISR_TXPAUSEFRAMES_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MMC_TISR_TXPAUSEFRAMES_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MMC_TISR_TXVLANFRAMES_G_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MMC_TISR_TXVLANFRAMES_G_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* MTL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MTL_OMR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define MTL_FDDR 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MTL_RQDCM0R 0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MTL_RQDCM_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MTL_RQDCM_Q_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* MTL register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MTL_OMR_ETSALG_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MTL_OMR_ETSALG_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MTL_OMR_RAA_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MTL_OMR_RAA_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* MTL queue register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Multiple queues can be active. The first queue has registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * that begin at 0x1100. Each subsequent queue has registers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * are accessed using an offset of 0x80 from the previous queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MTL_Q_BASE 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MTL_Q_INC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MTL_Q_TQOMR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MTL_Q_RQOMR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MTL_Q_RQDR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MTL_Q_RQFCR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MTL_Q_IER 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MTL_Q_ISR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* MTL queue register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MTL_Q_RQDR_PRXQ_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MTL_Q_RQDR_PRXQ_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MTL_Q_RQDR_RXQSTS_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MTL_Q_RQDR_RXQSTS_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MTL_Q_RQFCR_RFA_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MTL_Q_RQFCR_RFA_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MTL_Q_RQFCR_RFD_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MTL_Q_RQFCR_RFD_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MTL_Q_RQOMR_EHFC_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MTL_Q_RQOMR_EHFC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MTL_Q_RQOMR_RQS_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MTL_Q_RQOMR_RQS_LEN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MTL_Q_RQOMR_RSF_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MTL_Q_RQOMR_RSF_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MTL_Q_RQOMR_FEP_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MTL_Q_RQOMR_FEP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MTL_Q_RQOMR_FUP_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MTL_Q_RQOMR_FUP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MTL_Q_RQOMR_RTC_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MTL_Q_RQOMR_RTC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MTL_Q_TQOMR_FTQ_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MTL_Q_TQOMR_FTQ_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MTL_Q_TQOMR_Q2TCMAP_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MTL_Q_TQOMR_Q2TCMAP_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MTL_Q_TQOMR_TQS_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MTL_Q_TQOMR_TQS_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MTL_Q_TQOMR_TSF_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MTL_Q_TQOMR_TSF_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MTL_Q_TQOMR_TTC_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MTL_Q_TQOMR_TTC_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MTL_Q_TQOMR_TXQEN_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MTL_Q_TQOMR_TXQEN_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* MTL queue register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MTL_RSF_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MTL_RSF_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MTL_TSF_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MTL_TSF_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MTL_RX_THRESHOLD_64 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MTL_RX_THRESHOLD_96 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MTL_RX_THRESHOLD_128 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MTL_TX_THRESHOLD_64 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MTL_TX_THRESHOLD_96 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MTL_TX_THRESHOLD_128 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MTL_TX_THRESHOLD_192 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MTL_TX_THRESHOLD_256 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MTL_TX_THRESHOLD_384 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MTL_TX_THRESHOLD_512 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MTL_ETSALG_WRR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MTL_ETSALG_WFQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MTL_ETSALG_DWRR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MTL_RAA_SP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MTL_RAA_WSP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MTL_Q_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MTL_Q_ENABLED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MTL_RQDCM0R_Q0MDMACH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MTL_RQDCM0R_Q1MDMACH 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MTL_RQDCM0R_Q2MDMACH 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MTL_RQDCM0R_Q3MDMACH 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MTL_RQDCM1R_Q4MDMACH 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define MTL_RQDCM1R_Q5MDMACH 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MTL_RQDCM1R_Q6MDMACH 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MTL_RQDCM1R_Q7MDMACH 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MTL_RQDCM2R_Q8MDMACH 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MTL_RQDCM2R_Q9MDMACH 0x00000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MTL_RQDCM2R_Q10MDMACH 0x000A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MTL_RQDCM2R_Q11MDMACH 0x0B000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* MTL traffic class register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Multiple traffic classes can be active. The first class has registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * that begin at 0x1100. Each subsequent queue has registers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * are accessed using an offset of 0x80 from the previous queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MTL_TC_BASE MTL_Q_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define MTL_TC_INC MTL_Q_INC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MTL_TC_ETSCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MTL_TC_ETSSR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MTL_TC_QWR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* MTL traffic class register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MTL_TC_ETSCR_TSA_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MTL_TC_ETSCR_TSA_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MTL_TC_QWR_QW_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MTL_TC_QWR_QW_LEN 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* MTL traffic class register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MTL_TSA_SP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MTL_TSA_ETS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* DMA register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DMA_MR 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DMA_SBMR 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DMA_ISR 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DMA_DSR0 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DMA_DSR1 0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* DMA register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DMA_ISR_MACIS_POS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DMA_ISR_MACIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DMA_ISR_MTLIS_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DMA_ISR_MTLIS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DMA_MR_SWR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DMA_MR_SWR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DMA_SBMR_EAME_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DMA_SBMR_EAME_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DMA_SBMR_BLEN_64_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DMA_SBMR_BLEN_64_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DMA_SBMR_BLEN_128_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DMA_SBMR_BLEN_128_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DMA_SBMR_BLEN_256_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DMA_SBMR_BLEN_256_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DMA_SBMR_UNDEF_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DMA_SBMR_UNDEF_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* DMA register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DMA_DSR_RPS_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DMA_DSR_TPS_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define DMA_DSR_Q_LEN (DMA_DSR_RPS_LEN + DMA_DSR_TPS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DMA_DSR0_TPS_START 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DMA_DSRX_FIRST_QUEUE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DMA_DSRX_INC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DMA_DSRX_QPR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DMA_DSRX_TPS_START 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DMA_TPS_STOPPED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DMA_TPS_SUSPENDED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* DMA channel register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Multiple channels can be active. The first channel has registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * that begin at 0x3100. Each subsequent channel has registers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * are accessed using an offset of 0x80 from the previous channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DMA_CH_BASE 0x3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DMA_CH_INC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DMA_CH_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DMA_CH_TCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DMA_CH_RCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DMA_CH_TDLR_HI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DMA_CH_TDLR_LO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DMA_CH_RDLR_HI 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DMA_CH_RDLR_LO 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define DMA_CH_TDTR_LO 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define DMA_CH_RDTR_LO 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define DMA_CH_TDRLR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define DMA_CH_RDRLR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define DMA_CH_IER 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define DMA_CH_RIWT 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DMA_CH_SR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* DMA channel register entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DMA_CH_CR_PBLX8_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DMA_CH_CR_PBLX8_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DMA_CH_CR_SPH_POS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define DMA_CH_CR_SPH_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DMA_CH_IER_AIE_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DMA_CH_IER_AIE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define DMA_CH_IER_FBEE_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define DMA_CH_IER_FBEE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define DMA_CH_IER_NIE_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define DMA_CH_IER_NIE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DMA_CH_IER_RBUE_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define DMA_CH_IER_RBUE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define DMA_CH_IER_RIE_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DMA_CH_IER_RIE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define DMA_CH_IER_RSE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define DMA_CH_IER_RSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define DMA_CH_IER_TBUE_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define DMA_CH_IER_TBUE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define DMA_CH_IER_TIE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define DMA_CH_IER_TIE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define DMA_CH_IER_TXSE_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define DMA_CH_IER_TXSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DMA_CH_RCR_PBL_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DMA_CH_RCR_PBL_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define DMA_CH_RCR_RBSZ_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DMA_CH_RCR_RBSZ_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define DMA_CH_RCR_SR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DMA_CH_RCR_SR_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define DMA_CH_RIWT_RWT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define DMA_CH_RIWT_RWT_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DMA_CH_SR_FBE_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define DMA_CH_SR_FBE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DMA_CH_SR_RBU_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define DMA_CH_SR_RBU_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DMA_CH_SR_RI_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define DMA_CH_SR_RI_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define DMA_CH_SR_RPS_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define DMA_CH_SR_RPS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define DMA_CH_SR_TBU_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define DMA_CH_SR_TBU_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define DMA_CH_SR_TI_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define DMA_CH_SR_TI_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define DMA_CH_SR_TPS_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define DMA_CH_SR_TPS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define DMA_CH_TCR_OSP_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define DMA_CH_TCR_OSP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define DMA_CH_TCR_PBL_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define DMA_CH_TCR_PBL_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define DMA_CH_TCR_ST_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define DMA_CH_TCR_ST_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DMA_CH_TCR_TSE_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define DMA_CH_TCR_TSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* DMA channel register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DMA_OSP_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DMA_OSP_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define DMA_PBL_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DMA_PBL_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define DMA_PBL_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define DMA_PBL_8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define DMA_PBL_16 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DMA_PBL_32 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define DMA_PBL_64 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define DMA_PBL_128 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define DMA_PBL_256 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DMA_PBL_X8_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DMA_PBL_X8_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Descriptor/Packet entry bit positions and sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define RX_PACKET_ERRORS_CRC_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define RX_PACKET_ERRORS_CRC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define RX_PACKET_ERRORS_FRAME_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define RX_PACKET_ERRORS_FRAME_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define RX_PACKET_ERRORS_LENGTH_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define RX_PACKET_ERRORS_LENGTH_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define RX_PACKET_ERRORS_OVERRUN_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define RX_PACKET_ERRORS_OVERRUN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define RX_PACKET_ATTRIBUTES_INCOMPLETE_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define RX_PACKET_ATTRIBUTES_CONTEXT_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define RX_PACKET_ATTRIBUTES_CONTEXT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define RX_PACKET_ATTRIBUTES_RSS_HASH_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define RX_PACKET_ATTRIBUTES_RSS_HASH_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define RX_NORMAL_DESC0_OVT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define RX_NORMAL_DESC0_OVT_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define RX_NORMAL_DESC2_HL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define RX_NORMAL_DESC2_HL_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define RX_NORMAL_DESC3_CDA_POS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define RX_NORMAL_DESC3_CDA_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define RX_NORMAL_DESC3_CTXT_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define RX_NORMAL_DESC3_CTXT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define RX_NORMAL_DESC3_ES_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define RX_NORMAL_DESC3_ES_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define RX_NORMAL_DESC3_ETLT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define RX_NORMAL_DESC3_ETLT_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define RX_NORMAL_DESC3_FD_POS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define RX_NORMAL_DESC3_FD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define RX_NORMAL_DESC3_INTE_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define RX_NORMAL_DESC3_INTE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define RX_NORMAL_DESC3_L34T_POS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define RX_NORMAL_DESC3_L34T_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define RX_NORMAL_DESC3_LD_POS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define RX_NORMAL_DESC3_LD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define RX_NORMAL_DESC3_OWN_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define RX_NORMAL_DESC3_OWN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define RX_NORMAL_DESC3_PL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define RX_NORMAL_DESC3_PL_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define RX_NORMAL_DESC3_RSV_POS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define RX_NORMAL_DESC3_RSV_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define RX_DESC3_L34T_IPV4_TCP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define RX_DESC3_L34T_IPV4_UDP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define RX_DESC3_L34T_IPV4_ICMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define RX_DESC3_L34T_IPV6_TCP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define RX_DESC3_L34T_IPV6_UDP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define RX_DESC3_L34T_IPV6_ICMP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define RX_CONTEXT_DESC3_TSA_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define RX_CONTEXT_DESC3_TSA_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define RX_CONTEXT_DESC3_TSD_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define RX_CONTEXT_DESC3_TSD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define TX_PACKET_ATTRIBUTES_PTP_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define TX_PACKET_ATTRIBUTES_PTP_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define TX_CONTEXT_DESC2_MSS_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TX_CONTEXT_DESC2_MSS_LEN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define TX_CONTEXT_DESC3_CTXT_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TX_CONTEXT_DESC3_CTXT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TX_CONTEXT_DESC3_TCMSSV_POS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define TX_CONTEXT_DESC3_TCMSSV_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TX_CONTEXT_DESC3_VLTV_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define TX_CONTEXT_DESC3_VLTV_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define TX_CONTEXT_DESC3_VT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define TX_CONTEXT_DESC3_VT_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define TX_NORMAL_DESC2_HL_B1L_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define TX_NORMAL_DESC2_HL_B1L_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TX_NORMAL_DESC2_IC_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define TX_NORMAL_DESC2_IC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define TX_NORMAL_DESC2_TTSE_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define TX_NORMAL_DESC2_TTSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define TX_NORMAL_DESC2_VTIR_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define TX_NORMAL_DESC2_VTIR_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define TX_NORMAL_DESC3_CIC_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define TX_NORMAL_DESC3_CIC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define TX_NORMAL_DESC3_CPC_POS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define TX_NORMAL_DESC3_CPC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TX_NORMAL_DESC3_CTXT_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define TX_NORMAL_DESC3_CTXT_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define TX_NORMAL_DESC3_FD_POS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define TX_NORMAL_DESC3_FD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TX_NORMAL_DESC3_FL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define TX_NORMAL_DESC3_FL_LEN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define TX_NORMAL_DESC3_LD_POS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define TX_NORMAL_DESC3_LD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define TX_NORMAL_DESC3_OWN_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define TX_NORMAL_DESC3_OWN_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define TX_NORMAL_DESC3_TCPHDRLEN_POS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define TX_NORMAL_DESC3_TCPHDRLEN_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TX_NORMAL_DESC3_TCPPL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define TX_NORMAL_DESC3_TCPPL_LEN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define TX_NORMAL_DESC3_TSE_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define TX_NORMAL_DESC3_TSE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define XLGMAC_MTL_REG(pdata, n, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ((pdata)->mac_regs + MTL_Q_BASE + ((n) * MTL_Q_INC) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif /* __DWC_XLGMAC_REG_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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