^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is dual-licensed; you may select either version 2 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License ("GPL") or BSD license ("BSD").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This Synopsys DWC XLGMAC software driver and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (hereinafter the "Software") is an unsupported proprietary work of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Synopsys, Inc. unless otherwise expressly agreed to in writing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Synopsys and you. The Software IS NOT an item of Licensed Software or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Licensed Product under any End User Software License Agreement or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Agreement for Licensed Products with Synopsys or any supplement thereto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Synopsys is a registered trademark of Synopsys, Inc. Other names included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * in the SOFTWARE may be the trademarks of their respective owners.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/bitrev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/crc32poly.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dcbnl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "dwc-xlgmac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "dwc-xlgmac-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int xlgmac_tx_complete(struct xlgmac_dma_desc *dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return !XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) TX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) TX_NORMAL_DESC3_OWN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int xlgmac_disable_rx_csum(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MAC_RCR_IPC_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int xlgmac_enable_rx_csum(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MAC_RCR_IPC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int xlgmac_set_mac_address(struct xlgmac_pdata *pdata, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int mac_addr_hi, mac_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (addr[1] << 8) | (addr[0] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(mac_addr_hi, pdata->mac_regs + MAC_MACA0HR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(mac_addr_lo, pdata->mac_regs + MAC_MACA0LR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void xlgmac_set_mac_reg(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct netdev_hw_addr *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int *mac_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int mac_addr_hi, mac_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 *mac_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mac_addr_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mac_addr_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ha) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mac_addr = (u8 *)&mac_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mac_addr[0] = ha->addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mac_addr[1] = ha->addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mac_addr[2] = ha->addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mac_addr[3] = ha->addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mac_addr = (u8 *)&mac_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mac_addr[0] = ha->addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mac_addr[1] = ha->addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) netif_dbg(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "adding mac address %pM at %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ha->addr, *mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mac_addr_hi = XLGMAC_SET_REG_BITS(mac_addr_hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MAC_MACA1HR_AE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MAC_MACA1HR_AE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(mac_addr_hi, pdata->mac_regs + *mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *mac_reg += MAC_MACA_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(mac_addr_lo, pdata->mac_regs + *mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *mac_reg += MAC_MACA_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int xlgmac_enable_rx_vlan_stripping(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regval = readl(pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Put the VLAN tag in the Rx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MAC_VLANTR_EVLRXS_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Don't check the VLAN type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MAC_VLANTR_DOVLTC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Check only C-TAG (0x8100) packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MAC_VLANTR_ERSVLM_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MAC_VLANTR_ESVL_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Enable VLAN tag stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MAC_VLANTR_EVLS_LEN, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(regval, pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int xlgmac_disable_rx_vlan_stripping(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regval = readl(pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MAC_VLANTR_EVLS_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(regval, pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int xlgmac_enable_rx_vlan_filtering(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) regval = readl(pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Enable VLAN filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MAC_PFR_VTFE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(regval, pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regval = readl(pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Enable VLAN Hash Table filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MAC_VLANTR_VTHM_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Disable VLAN tag inverse matching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MAC_VLANTR_VTIM_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Only filter on the lower 12-bits of the VLAN tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MAC_VLANTR_ETV_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* In order for the VLAN Hash Table filtering to be effective,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * the VLAN tag identifier in the VLAN Tag Register must not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * be zero. Set the VLAN tag identifier to "1" to enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * VLAN Hash Table filtering. This implies that a VLAN tag of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * 1 will always pass filtering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MAC_VLANTR_VL_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(regval, pdata->mac_regs + MAC_VLANTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int xlgmac_disable_rx_vlan_filtering(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regval = readl(pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Disable VLAN filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MAC_PFR_VTFE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(regval, pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static u32 xlgmac_vid_crc32_le(__le16 vid_le)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned char *data = (unsigned char *)&vid_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned char data_byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 crc = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int i, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bits = get_bitmask_order(VLAN_VID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 0; i < bits; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if ((i % 8) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data_byte = data[i / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) temp = ((crc & 1) ^ data_byte) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) crc >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) data_byte >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) crc ^= CRC32_POLY_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int xlgmac_update_vlan_hash_table(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 vlan_hash_table = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __le16 vid_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Generate the VLAN Hash Table value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Get the CRC32 value of the VLAN ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vid_le = cpu_to_le16(vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) crc = bitrev32(~xlgmac_vid_crc32_le(vid_le)) >> 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vlan_hash_table |= (1 << crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regval = readl(pdata->mac_regs + MAC_VLANHTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set the VLAN Hash Table filtering register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MAC_VLANHTR_VLHT_LEN, vlan_hash_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(regval, pdata->mac_regs + MAC_VLANHTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int xlgmac_set_promiscuous_mode(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int val = enable ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MAC_PFR_PR_POS, MAC_PFR_PR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (regval == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enable ? "entering" : "leaving");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) regval = readl(pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MAC_PFR_PR_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(regval, pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Hardware will still perform VLAN filtering in promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) xlgmac_disable_rx_vlan_filtering(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) xlgmac_enable_rx_vlan_filtering(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int xlgmac_set_all_multicast_mode(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int val = enable ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MAC_PFR_PM_POS, MAC_PFR_PM_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (regval == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enable ? "entering" : "leaving");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regval = readl(pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MAC_PFR_PM_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(regval, pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void xlgmac_set_mac_addn_addrs(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int addn_macs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int mac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mac_reg = MAC_MACA1HR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) addn_macs = pdata->hw_feat.addn_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (netdev_uc_count(netdev) > addn_macs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) xlgmac_set_promiscuous_mode(pdata, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) netdev_for_each_uc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) xlgmac_set_mac_reg(pdata, ha, &mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) addn_macs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (netdev_mc_count(netdev) > addn_macs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) xlgmac_set_all_multicast_mode(pdata, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) netdev_for_each_mc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) xlgmac_set_mac_reg(pdata, ha, &mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) addn_macs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Clear remaining additional MAC address entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (addn_macs--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) xlgmac_set_mac_reg(pdata, NULL, &mac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void xlgmac_set_mac_hash_table(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int hash_table_shift, hash_table_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 hash_table[XLGMAC_MAC_HASH_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int hash_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hash_table_count = pdata->hw_feat.hash_table_size / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) memset(hash_table, 0, sizeof(hash_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Build the MAC Hash Table register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) netdev_for_each_uc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) crc >>= hash_table_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hash_table[crc >> 5] |= (1 << (crc & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) netdev_for_each_mc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) crc >>= hash_table_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) hash_table[crc >> 5] |= (1 << (crc & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Set the MAC Hash Table registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hash_reg = MAC_HTR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; i < hash_table_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(hash_table[i], pdata->mac_regs + hash_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hash_reg += MAC_HTR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int xlgmac_add_mac_addresses(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (pdata->hw_feat.hash_table_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xlgmac_set_mac_hash_table(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) xlgmac_set_mac_addn_addrs(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void xlgmac_config_mac_address(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) xlgmac_set_mac_address(pdata, pdata->netdev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Filtering is done using perfect filtering and hash filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (pdata->hw_feat.hash_table_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) regval = readl(pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MAC_PFR_HPF_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MAC_PFR_HUC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MAC_PFR_HMC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(regval, pdata->mac_regs + MAC_PFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void xlgmac_config_jumbo_enable(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val = (pdata->netdev->mtu > XLGMAC_STD_PACKET_MTU) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MAC_RCR_JE_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void xlgmac_config_checksum_offload(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (pdata->netdev->features & NETIF_F_RXCSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) xlgmac_enable_rx_csum(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) xlgmac_disable_rx_csum(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void xlgmac_config_vlan_support(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regval = readl(pdata->mac_regs + MAC_VLANIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Indicate that VLAN Tx CTAGs come from context descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MAC_VLANIR_CSVL_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MAC_VLANIR_VLTI_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(regval, pdata->mac_regs + MAC_VLANIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Set the current VLAN Hash Table register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) xlgmac_update_vlan_hash_table(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) xlgmac_enable_rx_vlan_filtering(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) xlgmac_disable_rx_vlan_filtering(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) xlgmac_enable_rx_vlan_stripping(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) xlgmac_disable_rx_vlan_stripping(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int xlgmac_config_rx_mode(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int pr_mode, am_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) xlgmac_set_promiscuous_mode(pdata, pr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) xlgmac_set_all_multicast_mode(pdata, am_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) xlgmac_add_mac_addresses(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void xlgmac_prepare_tx_stop(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct xlgmac_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int tx_dsr, tx_pos, tx_qidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned long tx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Calculate the status register to read and the position within */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tx_dsr = DMA_DSR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tx_pos = (channel->queue_index * DMA_DSR_Q_LEN) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DMA_DSR0_TPS_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_LEN) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DMA_DSRX_TPS_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* The Tx engine cannot be stopped if it is actively processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * descriptors. Wait for the Tx engine to enter the stopped or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * suspended state. Don't wait forever though...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tx_timeout = jiffies + (XLGMAC_DMA_STOP_TIMEOUT * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) while (time_before(jiffies, tx_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tx_status = readl(pdata->mac_regs + tx_dsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tx_status = XLGMAC_GET_REG_BITS(tx_status, tx_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DMA_DSR_TPS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if ((tx_status == DMA_TPS_STOPPED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (tx_status == DMA_TPS_SUSPENDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!time_before(jiffies, tx_timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) netdev_info(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "timed out waiting for Tx DMA channel %u to stop\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) channel->queue_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void xlgmac_enable_tx(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Enable each Tx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DMA_CH_TCR_ST_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Enable each Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MTL_Q_TQOMR_TXQEN_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MTL_Q_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Enable MAC Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MAC_TCR_TE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void xlgmac_disable_tx(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Prepare for Tx DMA channel stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) xlgmac_prepare_tx_stop(pdata, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Disable MAC Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MAC_TCR_TE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Disable each Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MTL_Q_TQOMR_TXQEN_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Disable each Tx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DMA_CH_TCR_ST_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void xlgmac_prepare_rx_stop(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int rx_status, prxq, rxqsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned long rx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* The Rx engine cannot be stopped if it is actively processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * packets. Wait for the Rx queue to empty the Rx fifo. Don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * wait forever though...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rx_timeout = jiffies + (XLGMAC_DMA_STOP_TIMEOUT * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) while (time_before(jiffies, rx_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rx_status = readl(XLGMAC_MTL_REG(pdata, queue, MTL_Q_RQDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) prxq = XLGMAC_GET_REG_BITS(rx_status, MTL_Q_RQDR_PRXQ_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MTL_Q_RQDR_PRXQ_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rxqsts = XLGMAC_GET_REG_BITS(rx_status, MTL_Q_RQDR_RXQSTS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MTL_Q_RQDR_RXQSTS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if ((prxq == 0) && (rxqsts == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!time_before(jiffies, rx_timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) netdev_info(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "timed out waiting for Rx queue %u to empty\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void xlgmac_enable_rx(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int regval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Enable each Rx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DMA_CH_RCR_SR_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Enable each Rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (i = 0; i < pdata->rx_q_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) regval |= (0x02 << (i << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) writel(regval, pdata->mac_regs + MAC_RQC0R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Enable MAC Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MAC_RCR_DCRCC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MAC_RCR_CST_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MAC_RCR_ACS_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MAC_RCR_RE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void xlgmac_disable_rx(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Disable MAC Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MAC_RCR_DCRCC_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MAC_RCR_CST_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MAC_RCR_ACS_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MAC_RCR_RE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Prepare for Rx DMA channel stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (i = 0; i < pdata->rx_q_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) xlgmac_prepare_rx_stop(pdata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Disable each Rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel(0, pdata->mac_regs + MAC_RQC0R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Disable each Rx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DMA_CH_RCR_SR_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void xlgmac_tx_start_xmit(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct xlgmac_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct xlgmac_pdata *pdata = channel->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Make sure everything is written before the register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Issue a poll command to Tx DMA by writing address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * of next immediate free descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) desc_data = XLGMAC_GET_DESC_DATA(ring, ring->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(lower_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) XLGMAC_DMA_REG(channel, DMA_CH_TDTR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Start the Tx timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (pdata->tx_usecs && !channel->tx_timer_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) channel->tx_timer_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mod_timer(&channel->tx_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) jiffies + usecs_to_jiffies(pdata->tx_usecs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ring->tx.xmit_more = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void xlgmac_dev_xmit(struct xlgmac_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct xlgmac_pdata *pdata = channel->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct xlgmac_ring *ring = channel->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int tso_context, vlan_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct xlgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct xlgmac_pkt_info *pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned int csum, tso, vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int start_index = ring->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int cur_index = ring->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int tx_set_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pkt_info = &ring->pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) csum = XLGMAC_GET_REG_BITS(pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tso = XLGMAC_GET_REG_BITS(pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) vlan = XLGMAC_GET_REG_BITS(pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (tso && (pkt_info->mss != ring->tx.cur_mss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) tso_context = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tso_context = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (vlan && (pkt_info->vlan_ctag != ring->tx.cur_vlan_ctag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) vlan_context = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) vlan_context = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Determine if an interrupt should be generated for this Tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * Interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * - Tx frame count exceeds the frame count setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * - Addition of Tx frame count to the frame count since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * last interrupt was set exceeds the frame count setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * No interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * - No frame count setting specified (ethtool -C ethX tx-frames 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * - Addition of Tx frame count to the frame count since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * last interrupt was set does not exceed the frame count setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ring->coalesce_count += pkt_info->tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!pdata->tx_frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) tx_set_ic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else if (pkt_info->tx_packets > pdata->tx_frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tx_set_ic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else if ((ring->coalesce_count % pdata->tx_frames) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pkt_info->tx_packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tx_set_ic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tx_set_ic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) desc_data = XLGMAC_GET_DESC_DATA(ring, cur_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Create a context descriptor if this is a TSO pkt_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (tso_context || vlan_context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (tso_context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) netif_dbg(pdata, tx_queued, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "TSO context descriptor, mss=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pkt_info->mss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Set the MSS size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) TX_CONTEXT_DESC2_MSS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TX_CONTEXT_DESC2_MSS_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pkt_info->mss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Mark it as a CONTEXT descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TX_CONTEXT_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TX_CONTEXT_DESC3_CTXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Indicate this descriptor contains the MSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TX_CONTEXT_DESC3_TCMSSV_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) TX_CONTEXT_DESC3_TCMSSV_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ring->tx.cur_mss = pkt_info->mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (vlan_context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) netif_dbg(pdata, tx_queued, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "VLAN context descriptor, ctag=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pkt_info->vlan_ctag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Mark it as a CONTEXT descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TX_CONTEXT_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TX_CONTEXT_DESC3_CTXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Set the VLAN tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TX_CONTEXT_DESC3_VT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TX_CONTEXT_DESC3_VT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pkt_info->vlan_ctag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Indicate this descriptor contains the VLAN tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TX_CONTEXT_DESC3_VLTV_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TX_CONTEXT_DESC3_VLTV_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ring->tx.cur_vlan_ctag = pkt_info->vlan_ctag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) cur_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) desc_data = XLGMAC_GET_DESC_DATA(ring, cur_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Update buffer address (for TSO this is the header) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dma_desc->desc0 = cpu_to_le32(lower_32_bits(desc_data->skb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dma_desc->desc1 = cpu_to_le32(upper_32_bits(desc_data->skb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Update the buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TX_NORMAL_DESC2_HL_B1L_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) TX_NORMAL_DESC2_HL_B1L_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) desc_data->skb_dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* VLAN tag insertion check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (vlan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TX_NORMAL_DESC2_VTIR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) TX_NORMAL_DESC2_VTIR_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TX_NORMAL_DESC2_VLAN_INSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pdata->stats.tx_vlan_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Timestamp enablement check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (XLGMAC_GET_REG_BITS(pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TX_PACKET_ATTRIBUTES_PTP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TX_PACKET_ATTRIBUTES_PTP_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) TX_NORMAL_DESC2_TTSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) TX_NORMAL_DESC2_TTSE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Mark it as First Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) TX_NORMAL_DESC3_FD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) TX_NORMAL_DESC3_FD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Mark it as a NORMAL descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) TX_NORMAL_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) TX_NORMAL_DESC3_CTXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Set OWN bit if not the first descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (cur_index != start_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) TX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) TX_NORMAL_DESC3_OWN_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (tso) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Enable TSO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TX_NORMAL_DESC3_TSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) TX_NORMAL_DESC3_TSE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TX_NORMAL_DESC3_TCPPL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) TX_NORMAL_DESC3_TCPPL_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pkt_info->tcp_payload_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) TX_NORMAL_DESC3_TCPHDRLEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) TX_NORMAL_DESC3_TCPHDRLEN_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pkt_info->tcp_header_len / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pdata->stats.tx_tso_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Enable CRC and Pad Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) TX_NORMAL_DESC3_CPC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) TX_NORMAL_DESC3_CPC_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Enable HW CSUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (csum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) TX_NORMAL_DESC3_CIC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TX_NORMAL_DESC3_CIC_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Set the total length to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) TX_NORMAL_DESC3_FL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) TX_NORMAL_DESC3_FL_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pkt_info->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) for (i = cur_index - start_index + 1; i < pkt_info->desc_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) cur_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) desc_data = XLGMAC_GET_DESC_DATA(ring, cur_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Update buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dma_desc->desc0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) cpu_to_le32(lower_32_bits(desc_data->skb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dma_desc->desc1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cpu_to_le32(upper_32_bits(desc_data->skb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Update the buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) TX_NORMAL_DESC2_HL_B1L_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TX_NORMAL_DESC2_HL_B1L_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) desc_data->skb_dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Set OWN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) TX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) TX_NORMAL_DESC3_OWN_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Mark it as NORMAL descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TX_NORMAL_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) TX_NORMAL_DESC3_CTXT_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Enable HW CSUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (csum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) TX_NORMAL_DESC3_CIC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) TX_NORMAL_DESC3_CIC_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Set LAST bit for the last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) TX_NORMAL_DESC3_LD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) TX_NORMAL_DESC3_LD_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Set IC bit based on Tx coalescing settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (tx_set_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dma_desc->desc2 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) TX_NORMAL_DESC2_IC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) TX_NORMAL_DESC2_IC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Save the Tx info to report back during cleanup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) desc_data->tx.packets = pkt_info->tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) desc_data->tx.bytes = pkt_info->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* In case the Tx DMA engine is running, make sure everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * is written to the descriptor(s) before setting the OWN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * for the first descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* Set OWN bit for the first descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) desc_data = XLGMAC_GET_DESC_DATA(ring, start_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) TX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) TX_NORMAL_DESC3_OWN_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (netif_msg_tx_queued(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) xlgmac_dump_tx_desc(pdata, ring, start_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pkt_info->desc_count, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Make sure ownership is written to the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ring->cur = cur_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!netdev_xmit_more() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) channel->queue_index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) xlgmac_tx_start_xmit(channel, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ring->tx.xmit_more = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) XLGMAC_PR("%s: descriptors %u to %u written\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) channel->name, start_index & (ring->dma_desc_count - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (ring->cur - 1) & (ring->dma_desc_count - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static void xlgmac_get_rx_tstamp(struct xlgmac_pkt_info *pkt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct xlgmac_dma_desc *dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u32 tsa, tsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) tsa = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) RX_CONTEXT_DESC3_TSA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) RX_CONTEXT_DESC3_TSA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) tsd = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RX_CONTEXT_DESC3_TSD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RX_CONTEXT_DESC3_TSD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (tsa && !tsd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) nsec = le32_to_cpu(dma_desc->desc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) nsec <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) nsec |= le32_to_cpu(dma_desc->desc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (nsec != 0xffffffffffffffffULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pkt_info->rx_tstamp = nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static void xlgmac_tx_desc_reset(struct xlgmac_desc_data *desc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct xlgmac_dma_desc *dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Reset the Tx descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * Set buffer 1 (lo) address to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Set buffer 1 (hi) address to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * Reset all other control bits (IC, TTSE, B2L & B1L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dma_desc->desc0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dma_desc->desc1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dma_desc->desc2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dma_desc->desc3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Make sure ownership is written to the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static void xlgmac_tx_desc_init(struct xlgmac_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct xlgmac_ring *ring = channel->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int start_index = ring->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Initialze all descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for (i = 0; i < ring->dma_desc_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) desc_data = XLGMAC_GET_DESC_DATA(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Initialize Tx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) xlgmac_tx_desc_reset(desc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* Update the total number of Tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_TDRLR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Update the starting address of descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) desc_data = XLGMAC_GET_DESC_DATA(ring, start_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) writel(upper_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) XLGMAC_DMA_REG(channel, DMA_CH_TDLR_HI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) writel(lower_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) XLGMAC_DMA_REG(channel, DMA_CH_TDLR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static void xlgmac_rx_desc_reset(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct xlgmac_desc_data *desc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct xlgmac_dma_desc *dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) unsigned int rx_frames = pdata->rx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) unsigned int rx_usecs = pdata->rx_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dma_addr_t hdr_dma, buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) unsigned int inte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (!rx_usecs && !rx_frames) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* No coalescing, interrupt for every descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) inte = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Set interrupt based on Rx frame coalescing setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (rx_frames && !((index + 1) % rx_frames))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) inte = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) inte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Reset the Rx descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * Set buffer 1 (lo) address to header dma address (lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Set buffer 1 (hi) address to header dma address (hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * Set buffer 2 (lo) address to buffer dma address (lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * Set buffer 2 (hi) address to buffer dma address (hi) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * set control bits OWN and INTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) hdr_dma = desc_data->rx.hdr.dma_base + desc_data->rx.hdr.dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) buf_dma = desc_data->rx.buf.dma_base + desc_data->rx.buf.dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dma_desc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dma_desc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dma_desc->desc2 = cpu_to_le32(lower_32_bits(buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dma_desc->desc3 = cpu_to_le32(upper_32_bits(buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RX_NORMAL_DESC3_INTE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) RX_NORMAL_DESC3_INTE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) inte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Since the Rx DMA engine is likely running, make sure everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * is written to the descriptor(s) before setting the OWN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * for the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) RX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) RX_NORMAL_DESC3_OWN_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Make sure ownership is written to the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void xlgmac_rx_desc_init(struct xlgmac_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct xlgmac_pdata *pdata = channel->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct xlgmac_ring *ring = channel->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned int start_index = ring->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Initialize all descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) for (i = 0; i < ring->dma_desc_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) desc_data = XLGMAC_GET_DESC_DATA(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Initialize Rx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) xlgmac_rx_desc_reset(pdata, desc_data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Update the total number of Rx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_RDRLR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Update the starting address of descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) desc_data = XLGMAC_GET_DESC_DATA(ring, start_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) writel(upper_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) XLGMAC_DMA_REG(channel, DMA_CH_RDLR_HI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) writel(lower_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) XLGMAC_DMA_REG(channel, DMA_CH_RDLR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Update the Rx Descriptor Tail Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) desc_data = XLGMAC_GET_DESC_DATA(ring, start_index +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ring->dma_desc_count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) writel(lower_32_bits(desc_data->dma_desc_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) XLGMAC_DMA_REG(channel, DMA_CH_RDTR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static int xlgmac_is_context_desc(struct xlgmac_dma_desc *dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) TX_NORMAL_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) TX_NORMAL_DESC3_CTXT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static int xlgmac_is_last_desc(struct xlgmac_dma_desc *dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Rx and Tx share LD bit, so check TDES3.LD bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) TX_NORMAL_DESC3_LD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) TX_NORMAL_DESC3_LD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int xlgmac_disable_tx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) unsigned int max_q_count, q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned int reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* Clear MTL flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MTL_Q_RQOMR_EHFC_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Clear MAC flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) max_q_count = XLGMAC_MAX_FLOW_CONTROL_QUEUES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) reg = MAC_Q0TFCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) for (i = 0; i < q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) regval = readl(pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) regval = XLGMAC_SET_REG_BITS(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) MAC_Q0TFCR_TFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) MAC_Q0TFCR_TFE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) reg += MAC_QTFCR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int xlgmac_enable_tx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned int max_q_count, q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) unsigned int reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Set MTL flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MTL_Q_RQOMR_EHFC_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Set MAC flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) max_q_count = XLGMAC_MAX_FLOW_CONTROL_QUEUES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) reg = MAC_Q0TFCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) for (i = 0; i < q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) regval = readl(pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Enable transmit flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) MAC_Q0TFCR_TFE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* Set pause time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MAC_Q0TFCR_PT_LEN, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) reg += MAC_QTFCR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int xlgmac_disable_rx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) regval = readl(pdata->mac_regs + MAC_RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) MAC_RFCR_RFE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) writel(regval, pdata->mac_regs + MAC_RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int xlgmac_enable_rx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) regval = readl(pdata->mac_regs + MAC_RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) MAC_RFCR_RFE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) writel(regval, pdata->mac_regs + MAC_RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int xlgmac_config_tx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (pdata->tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) xlgmac_enable_tx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) xlgmac_disable_tx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int xlgmac_config_rx_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (pdata->rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) xlgmac_enable_rx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) xlgmac_disable_rx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int xlgmac_config_rx_coalesce(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) DMA_CH_RIWT_RWT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) pdata->rx_riwt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static void xlgmac_config_flow_control(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) xlgmac_config_tx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) xlgmac_config_rx_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void xlgmac_config_rx_fep_enable(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) MTL_Q_RQOMR_FEP_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static void xlgmac_config_rx_fup_enable(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) MTL_Q_RQOMR_FUP_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int xlgmac_config_tx_coalesce(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static void xlgmac_config_rx_buffer_size(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) DMA_CH_RCR_RBSZ_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) pdata->rx_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static void xlgmac_config_tso_mode(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (pdata->hw_feat.tso) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) DMA_CH_TCR_TSE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static void xlgmac_config_sph_mode(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) DMA_CH_CR_SPH_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) regval = readl(pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) MAC_RCR_HDSMS_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) XLGMAC_SPH_HDSMS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) writel(regval, pdata->mac_regs + MAC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static unsigned int xlgmac_usec_to_riwt(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) unsigned int usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) rate = pdata->sysclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Convert the input usec value to the watchdog timer value. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * watchdog timer value is equivalent to 256 clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * Calculate the required value as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * ( usec * ( system_clock_mhz / 10^6 ) / 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = (usec * (rate / 1000000)) / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static unsigned int xlgmac_riwt_to_usec(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) unsigned int riwt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) rate = pdata->sysclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Convert the input watchdog timer value to the usec value. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * watchdog timer value is equivalent to 256 clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Calculate the required value as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = (riwt * 256) / (rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static int xlgmac_config_rx_threshold(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) MTL_Q_RQOMR_RTC_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static void xlgmac_config_mtl_mode(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* Set Tx to weighted round robin scheduling algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) regval = readl(pdata->mac_regs + MTL_OMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) MTL_OMR_ETSALG_LEN, MTL_ETSALG_WRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) writel(regval, pdata->mac_regs + MTL_OMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Set Tx traffic classes to use WRR algorithm with equal weights */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) MTL_TC_ETSCR_TSA_LEN, MTL_TSA_ETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) MTL_TC_QWR_QW_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* Set Rx to strict priority algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) regval = readl(pdata->mac_regs + MTL_OMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) MTL_OMR_RAA_LEN, MTL_RAA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) writel(regval, pdata->mac_regs + MTL_OMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static void xlgmac_config_queue_mapping(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) unsigned int ppq, ppq_extra, prio, prio_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) unsigned int qptc, qptc_extra, queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) unsigned int reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* Map the MTL Tx Queues to Traffic Classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * Note: Tx Queues >= Traffic Classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) for (j = 0; j < qptc; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) netif_dbg(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) "TXq%u mapped to TC%u\n", queue, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) regval = readl(XLGMAC_MTL_REG(pdata, queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) regval = XLGMAC_SET_REG_BITS(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) MTL_Q_TQOMR_Q2TCMAP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) MTL_Q_TQOMR_Q2TCMAP_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) writel(regval, XLGMAC_MTL_REG(pdata, queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) queue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (i < qptc_extra) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) netif_dbg(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "TXq%u mapped to TC%u\n", queue, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) regval = readl(XLGMAC_MTL_REG(pdata, queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) regval = XLGMAC_SET_REG_BITS(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) MTL_Q_TQOMR_Q2TCMAP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MTL_Q_TQOMR_Q2TCMAP_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) writel(regval, XLGMAC_MTL_REG(pdata, queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) queue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Map the 8 VLAN priority values to available MTL Rx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pdata->rx_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) reg = MAC_RQC2R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) for (i = 0, prio = 0; i < prio_queues;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) for (j = 0; j < ppq; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) netif_dbg(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) "PRIO%u mapped to RXq%u\n", prio, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) mask |= (1 << prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) prio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (i < ppq_extra) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) netif_dbg(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) "PRIO%u mapped to RXq%u\n", prio, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) mask |= (1 << prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) prio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) reg += MAC_RQC2_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /* Configure one to one, MTL Rx queue to DMA Rx channel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * ie Q0 <--> CH0, Q1 <--> CH1 ... Q11 <--> CH11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) reg = MTL_RQDCM0R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) regval = readl(pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) regval |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) MTL_RQDCM0R_Q2MDMACH | MTL_RQDCM0R_Q3MDMACH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) reg += MTL_RQDCM_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) regval = readl(pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) regval |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) MTL_RQDCM1R_Q6MDMACH | MTL_RQDCM1R_Q7MDMACH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) reg += MTL_RQDCM_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) regval = readl(pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) regval |= (MTL_RQDCM2R_Q8MDMACH | MTL_RQDCM2R_Q9MDMACH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) MTL_RQDCM2R_Q10MDMACH | MTL_RQDCM2R_Q11MDMACH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) writel(regval, pdata->mac_regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static unsigned int xlgmac_calculate_per_queue_fifo(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) unsigned int fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) unsigned int queue_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) unsigned int q_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unsigned int p_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* Calculate the configured fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) q_fifo_size = 1 << (fifo_size + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* The configured value may not be the actual amount of fifo RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) q_fifo_size = min_t(unsigned int, XLGMAC_MAX_FIFO, q_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) q_fifo_size = q_fifo_size / queue_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* Each increment in the queue fifo size represents 256 bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * fifo, with 0 representing 256 bytes. Distribute the fifo equally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * between the queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) p_fifo = q_fifo_size / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (p_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) p_fifo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return p_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static void xlgmac_config_tx_fifo_size(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) fifo_size = xlgmac_calculate_per_queue_fifo(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) pdata->hw_feat.tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) pdata->tx_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MTL_Q_TQOMR_TQS_LEN, fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) netif_info(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) "%d Tx hardware queues, %d byte fifo per queue\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pdata->tx_q_count, ((fifo_size + 1) * 256));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static void xlgmac_config_rx_fifo_size(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) fifo_size = xlgmac_calculate_per_queue_fifo(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) pdata->hw_feat.rx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) pdata->rx_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) MTL_Q_RQOMR_RQS_LEN, fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) netif_info(pdata, drv, pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) "%d Rx hardware queues, %d byte fifo per queue\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pdata->rx_q_count, ((fifo_size + 1) * 256));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static void xlgmac_config_flow_control_threshold(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* Activate flow control when less than 4k left in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) MTL_Q_RQFCR_RFA_LEN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /* De-activate flow control when more than 6k left in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) MTL_Q_RQFCR_RFD_LEN, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static int xlgmac_config_tx_threshold(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) MTL_Q_TQOMR_TTC_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static int xlgmac_config_rsf_mode(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) for (i = 0; i < pdata->rx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) MTL_Q_RQOMR_RSF_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static int xlgmac_config_tsf_mode(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) MTL_Q_TQOMR_TSF_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static int xlgmac_config_osp_mode(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) DMA_CH_TCR_OSP_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) pdata->tx_osp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static int xlgmac_config_pblx8(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) DMA_CH_CR_PBLX8_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) pdata->pblx8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int xlgmac_get_tx_pbl_val(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) DMA_CH_TCR_PBL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static int xlgmac_config_tx_pbl_val(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (!channel->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) DMA_CH_TCR_PBL_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) pdata->tx_pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static int xlgmac_get_rx_pbl_val(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) DMA_CH_RCR_PBL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static int xlgmac_config_rx_pbl_val(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (!channel->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) DMA_CH_RCR_PBL_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) pdata->rx_pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static u64 xlgmac_mmc_read(struct xlgmac_pdata *pdata, unsigned int reg_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) bool read_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) switch (reg_lo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /* These registers are always 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case MMC_TXOCTETCOUNT_GB_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case MMC_TXOCTETCOUNT_G_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) case MMC_RXOCTETCOUNT_GB_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) case MMC_RXOCTETCOUNT_G_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) read_hi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) read_hi = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) val = (u64)readl(pdata->mac_regs + reg_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (read_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) val |= ((u64)readl(pdata->mac_regs + reg_lo + 4) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static void xlgmac_tx_mmc_int(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) unsigned int mmc_isr = readl(pdata->mac_regs + MMC_TISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct xlgmac_stats *stats = &pdata->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) MMC_TISR_TXOCTETCOUNT_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) MMC_TISR_TXOCTETCOUNT_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) stats->txoctetcount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) MMC_TISR_TXFRAMECOUNT_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) MMC_TISR_TXFRAMECOUNT_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) stats->txframecount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) MMC_TISR_TXBROADCASTFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) MMC_TISR_TXBROADCASTFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) stats->txbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) MMC_TISR_TXMULTICASTFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) MMC_TISR_TXMULTICASTFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) stats->txmulticastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) MMC_TISR_TX64OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) MMC_TISR_TX64OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) stats->tx64octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) xlgmac_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) MMC_TISR_TX65TO127OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) MMC_TISR_TX65TO127OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) stats->tx65to127octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) xlgmac_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) MMC_TISR_TX128TO255OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) MMC_TISR_TX128TO255OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) stats->tx128to255octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) xlgmac_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) MMC_TISR_TX256TO511OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) MMC_TISR_TX256TO511OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) stats->tx256to511octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) xlgmac_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) MMC_TISR_TX512TO1023OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) MMC_TISR_TX512TO1023OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) stats->tx512to1023octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) xlgmac_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) MMC_TISR_TX1024TOMAXOCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) MMC_TISR_TX1024TOMAXOCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) stats->tx1024tomaxoctets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) xlgmac_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MMC_TISR_TXUNICASTFRAMES_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) MMC_TISR_TXUNICASTFRAMES_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) stats->txunicastframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) xlgmac_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) MMC_TISR_TXMULTICASTFRAMES_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) MMC_TISR_TXMULTICASTFRAMES_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) stats->txmulticastframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) MMC_TISR_TXBROADCASTFRAMES_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) MMC_TISR_TXBROADCASTFRAMES_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) stats->txbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) MMC_TISR_TXUNDERFLOWERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) MMC_TISR_TXUNDERFLOWERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) stats->txunderflowerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) xlgmac_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) MMC_TISR_TXOCTETCOUNT_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) MMC_TISR_TXOCTETCOUNT_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) stats->txoctetcount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) MMC_TISR_TXFRAMECOUNT_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) MMC_TISR_TXFRAMECOUNT_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) stats->txframecount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) MMC_TISR_TXPAUSEFRAMES_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) MMC_TISR_TXPAUSEFRAMES_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) stats->txpauseframes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) xlgmac_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) MMC_TISR_TXVLANFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) MMC_TISR_TXVLANFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) stats->txvlanframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) xlgmac_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static void xlgmac_rx_mmc_int(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) unsigned int mmc_isr = readl(pdata->mac_regs + MMC_RISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct xlgmac_stats *stats = &pdata->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) MMC_RISR_RXFRAMECOUNT_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) MMC_RISR_RXFRAMECOUNT_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) stats->rxframecount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) xlgmac_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) MMC_RISR_RXOCTETCOUNT_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) MMC_RISR_RXOCTETCOUNT_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) stats->rxoctetcount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) MMC_RISR_RXOCTETCOUNT_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) MMC_RISR_RXOCTETCOUNT_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) stats->rxoctetcount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) MMC_RISR_RXBROADCASTFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) MMC_RISR_RXBROADCASTFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) stats->rxbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) xlgmac_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) MMC_RISR_RXMULTICASTFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) MMC_RISR_RXMULTICASTFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) stats->rxmulticastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) xlgmac_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) MMC_RISR_RXCRCERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) MMC_RISR_RXCRCERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) stats->rxcrcerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) xlgmac_mmc_read(pdata, MMC_RXCRCERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) MMC_RISR_RXRUNTERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) MMC_RISR_RXRUNTERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) stats->rxrunterror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) xlgmac_mmc_read(pdata, MMC_RXRUNTERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) MMC_RISR_RXJABBERERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) MMC_RISR_RXJABBERERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) stats->rxjabbererror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) xlgmac_mmc_read(pdata, MMC_RXJABBERERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) MMC_RISR_RXUNDERSIZE_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) MMC_RISR_RXUNDERSIZE_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) stats->rxundersize_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) xlgmac_mmc_read(pdata, MMC_RXUNDERSIZE_G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) MMC_RISR_RXOVERSIZE_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) MMC_RISR_RXOVERSIZE_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) stats->rxoversize_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) xlgmac_mmc_read(pdata, MMC_RXOVERSIZE_G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) MMC_RISR_RX64OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) MMC_RISR_RX64OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) stats->rx64octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) xlgmac_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) MMC_RISR_RX65TO127OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) MMC_RISR_RX65TO127OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) stats->rx65to127octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) xlgmac_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) MMC_RISR_RX128TO255OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) MMC_RISR_RX128TO255OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) stats->rx128to255octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) xlgmac_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) MMC_RISR_RX256TO511OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) MMC_RISR_RX256TO511OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) stats->rx256to511octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) xlgmac_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) MMC_RISR_RX512TO1023OCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) MMC_RISR_RX512TO1023OCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) stats->rx512to1023octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) xlgmac_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) MMC_RISR_RX1024TOMAXOCTETS_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) MMC_RISR_RX1024TOMAXOCTETS_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) stats->rx1024tomaxoctets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) xlgmac_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) MMC_RISR_RXUNICASTFRAMES_G_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) MMC_RISR_RXUNICASTFRAMES_G_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) stats->rxunicastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) xlgmac_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) MMC_RISR_RXLENGTHERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) MMC_RISR_RXLENGTHERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) stats->rxlengtherror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) xlgmac_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) MMC_RISR_RXOUTOFRANGETYPE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) MMC_RISR_RXOUTOFRANGETYPE_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) stats->rxoutofrangetype +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) xlgmac_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) MMC_RISR_RXPAUSEFRAMES_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) MMC_RISR_RXPAUSEFRAMES_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) stats->rxpauseframes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) xlgmac_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) MMC_RISR_RXFIFOOVERFLOW_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) MMC_RISR_RXFIFOOVERFLOW_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) stats->rxfifooverflow +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) xlgmac_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) MMC_RISR_RXVLANFRAMES_GB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) MMC_RISR_RXVLANFRAMES_GB_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) stats->rxvlanframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) xlgmac_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (XLGMAC_GET_REG_BITS(mmc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) MMC_RISR_RXWATCHDOGERROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) MMC_RISR_RXWATCHDOGERROR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) stats->rxwatchdogerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) xlgmac_mmc_read(pdata, MMC_RXWATCHDOGERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static void xlgmac_read_mmc_stats(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct xlgmac_stats *stats = &pdata->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /* Freeze counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) regval = readl(pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) MMC_CR_MCF_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) writel(regval, pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) stats->txoctetcount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) stats->txframecount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) stats->txbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) stats->txmulticastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) stats->tx64octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) xlgmac_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) stats->tx65to127octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) xlgmac_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) stats->tx128to255octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) xlgmac_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) stats->tx256to511octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) xlgmac_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) stats->tx512to1023octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) xlgmac_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) stats->tx1024tomaxoctets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) xlgmac_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) stats->txunicastframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) xlgmac_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) stats->txmulticastframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) stats->txbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) stats->txunderflowerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) xlgmac_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) stats->txoctetcount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) stats->txframecount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) stats->txpauseframes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) xlgmac_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) stats->txvlanframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) xlgmac_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) stats->rxframecount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) xlgmac_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) stats->rxoctetcount_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) stats->rxoctetcount_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) stats->rxbroadcastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) xlgmac_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) stats->rxmulticastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) xlgmac_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) stats->rxcrcerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) xlgmac_mmc_read(pdata, MMC_RXCRCERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) stats->rxrunterror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) xlgmac_mmc_read(pdata, MMC_RXRUNTERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) stats->rxjabbererror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) xlgmac_mmc_read(pdata, MMC_RXJABBERERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) stats->rxundersize_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) xlgmac_mmc_read(pdata, MMC_RXUNDERSIZE_G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) stats->rxoversize_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) xlgmac_mmc_read(pdata, MMC_RXOVERSIZE_G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) stats->rx64octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) xlgmac_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) stats->rx65to127octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) xlgmac_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) stats->rx128to255octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) xlgmac_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) stats->rx256to511octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) xlgmac_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) stats->rx512to1023octets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) xlgmac_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) stats->rx1024tomaxoctets_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) xlgmac_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) stats->rxunicastframes_g +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) xlgmac_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) stats->rxlengtherror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) xlgmac_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) stats->rxoutofrangetype +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) xlgmac_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) stats->rxpauseframes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) xlgmac_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) stats->rxfifooverflow +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) xlgmac_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) stats->rxvlanframes_gb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) xlgmac_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) stats->rxwatchdogerror +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) xlgmac_mmc_read(pdata, MMC_RXWATCHDOGERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* Un-freeze counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) regval = readl(pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) MMC_CR_MCF_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) writel(regval, pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static void xlgmac_config_mmc(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) regval = readl(pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* Set counters to reset on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) MMC_CR_ROR_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* Reset the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) MMC_CR_CR_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) writel(regval, pdata->mac_regs + MMC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static int xlgmac_write_rss_reg(struct xlgmac_pdata *pdata, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) unsigned int index, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) unsigned int wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) mutex_lock(&pdata->rss_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) MAC_RSSAR_OB_POS, MAC_RSSAR_OB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (regval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) writel(val, pdata->mac_regs + MAC_RSSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) regval = readl(pdata->mac_regs + MAC_RSSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) MAC_RSSAR_RSSIA_LEN, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) MAC_RSSAR_ADDRT_LEN, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) MAC_RSSAR_CT_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) MAC_RSSAR_OB_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) writel(regval, pdata->mac_regs + MAC_RSSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) wait = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) while (wait--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) MAC_RSSAR_OB_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) MAC_RSSAR_OB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (!regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) mutex_unlock(&pdata->rss_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static int xlgmac_write_rss_hash_key(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) unsigned int *key = (unsigned int *)&pdata->rss_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) while (key_regs--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ret = xlgmac_write_rss_reg(pdata, XLGMAC_RSS_HASH_KEY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) key_regs, *key++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static int xlgmac_write_rss_lookup_table(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ret = xlgmac_write_rss_reg(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) XLGMAC_RSS_LOOKUP_TABLE_TYPE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pdata->rss_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static int xlgmac_set_rss_hash_key(struct xlgmac_pdata *pdata, const u8 *key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) return xlgmac_write_rss_hash_key(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static int xlgmac_set_rss_lookup_table(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) const u32 *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) u32 tval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) tval = table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) pdata->rss_table[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) MAC_RSSDR_DMCH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) MAC_RSSDR_DMCH_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) tval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return xlgmac_write_rss_lookup_table(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static int xlgmac_enable_rss(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (!pdata->hw_feat.rss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) /* Program the hash key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ret = xlgmac_write_rss_hash_key(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) /* Program the lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) ret = xlgmac_write_rss_lookup_table(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /* Set the RSS options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) writel(pdata->rss_options, pdata->mac_regs + MAC_RSSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* Enable RSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) regval = readl(pdata->mac_regs + MAC_RSSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) MAC_RSSCR_RSSE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) writel(regval, pdata->mac_regs + MAC_RSSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) static int xlgmac_disable_rss(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (!pdata->hw_feat.rss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) regval = readl(pdata->mac_regs + MAC_RSSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) MAC_RSSCR_RSSE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) writel(regval, pdata->mac_regs + MAC_RSSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static void xlgmac_config_rss(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (!pdata->hw_feat.rss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (pdata->netdev->features & NETIF_F_RXHASH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ret = xlgmac_enable_rss(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ret = xlgmac_disable_rss(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) netdev_err(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) "error configuring RSS, RSS disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static void xlgmac_enable_dma_interrupts(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) unsigned int dma_ch_isr, dma_ch_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct xlgmac_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) channel = pdata->channel_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) for (i = 0; i < pdata->channel_count; i++, channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /* Clear all the interrupts which are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* Clear all interrupt enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) dma_ch_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) /* Enable following interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * NIE - Normal Interrupt Summary Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * AIE - Abnormal Interrupt Summary Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * FBEE - Fatal Bus Error Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) DMA_CH_IER_NIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) DMA_CH_IER_NIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) DMA_CH_IER_AIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) DMA_CH_IER_AIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) DMA_CH_IER_FBEE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) DMA_CH_IER_FBEE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if (channel->tx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /* Enable the following Tx interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) * TIE - Transmit Interrupt Enable (unless using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * per channel interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) if (!pdata->per_channel_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) DMA_CH_IER_TIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) DMA_CH_IER_TIE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (channel->rx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* Enable following Rx interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) * RBUE - Receive Buffer Unavailable Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) * RIE - Receive Interrupt Enable (unless using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * per channel interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) DMA_CH_IER_RBUE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) DMA_CH_IER_RBUE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (!pdata->per_channel_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) dma_ch_ier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) DMA_CH_IER_RIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) DMA_CH_IER_RIE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static void xlgmac_enable_mtl_interrupts(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) unsigned int q_count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) unsigned int mtl_q_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) for (i = 0; i < q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) /* Clear all the interrupts which are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) mtl_q_isr = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) writel(mtl_q_isr, XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /* No MTL interrupts to be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) writel(0, XLGMAC_MTL_REG(pdata, i, MTL_Q_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) static void xlgmac_enable_mac_interrupts(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) unsigned int mac_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* Enable Timestamp interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) mac_ier = XLGMAC_SET_REG_BITS(mac_ier, MAC_IER_TSIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) MAC_IER_TSIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) writel(mac_ier, pdata->mac_regs + MAC_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) /* Enable all counter interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) regval = readl(pdata->mac_regs + MMC_RIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) MMC_RIER_ALL_INTERRUPTS_LEN, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) writel(regval, pdata->mac_regs + MMC_RIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) regval = readl(pdata->mac_regs + MMC_TIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) MMC_TIER_ALL_INTERRUPTS_LEN, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) writel(regval, pdata->mac_regs + MMC_TIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) static int xlgmac_set_xlgmii_25000_speed(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) MAC_TCR_SS_POS, MAC_TCR_SS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (regval == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) MAC_TCR_SS_LEN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static int xlgmac_set_xlgmii_40000_speed(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) MAC_TCR_SS_POS, MAC_TCR_SS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (regval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) MAC_TCR_SS_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static int xlgmac_set_xlgmii_50000_speed(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) MAC_TCR_SS_POS, MAC_TCR_SS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (regval == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) MAC_TCR_SS_LEN, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) static int xlgmac_set_xlgmii_100000_speed(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) MAC_TCR_SS_POS, MAC_TCR_SS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (regval == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) regval = readl(pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) MAC_TCR_SS_LEN, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) writel(regval, pdata->mac_regs + MAC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static void xlgmac_config_mac_speed(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) switch (pdata->phy_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) case SPEED_100000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) xlgmac_set_xlgmii_100000_speed(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) case SPEED_50000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) xlgmac_set_xlgmii_50000_speed(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) case SPEED_40000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) xlgmac_set_xlgmii_40000_speed(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case SPEED_25000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) xlgmac_set_xlgmii_25000_speed(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static int xlgmac_dev_read(struct xlgmac_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct xlgmac_pdata *pdata = channel->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct xlgmac_ring *ring = channel->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct xlgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) struct xlgmac_pkt_info *pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) unsigned int err, etlt, l34t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) desc_data = XLGMAC_GET_DESC_DATA(ring, ring->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) pkt_info = &ring->pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) /* Check for data availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) RX_NORMAL_DESC3_OWN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) RX_NORMAL_DESC3_OWN_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) /* Make sure descriptor fields are read after reading the OWN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (netif_msg_rx_status(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) xlgmac_dump_rx_desc(pdata, ring, ring->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) RX_NORMAL_DESC3_CTXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) RX_NORMAL_DESC3_CTXT_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* Timestamp Context Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) xlgmac_get_rx_tstamp(pkt_info, dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) RX_PACKET_ATTRIBUTES_CONTEXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) RX_PACKET_ATTRIBUTES_CONTEXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) /* Normal Descriptor, be sure Context Descriptor bit is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) RX_PACKET_ATTRIBUTES_CONTEXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) RX_PACKET_ATTRIBUTES_CONTEXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* Indicate if a Context Descriptor is next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) RX_NORMAL_DESC3_CDA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) RX_NORMAL_DESC3_CDA_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* Get the header length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) RX_NORMAL_DESC3_FD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) RX_NORMAL_DESC3_FD_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) desc_data->rx.hdr_len = XLGMAC_GET_REG_BITS_LE(dma_desc->desc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) RX_NORMAL_DESC2_HL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) RX_NORMAL_DESC2_HL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (desc_data->rx.hdr_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) pdata->stats.rx_split_header_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* Get the RSS hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) RX_NORMAL_DESC3_RSV_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) RX_NORMAL_DESC3_RSV_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) RX_PACKET_ATTRIBUTES_RSS_HASH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) RX_PACKET_ATTRIBUTES_RSS_HASH_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) pkt_info->rss_hash = le32_to_cpu(dma_desc->desc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) l34t = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) RX_NORMAL_DESC3_L34T_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) RX_NORMAL_DESC3_L34T_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) switch (l34t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) case RX_DESC3_L34T_IPV4_TCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) case RX_DESC3_L34T_IPV4_UDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) case RX_DESC3_L34T_IPV6_TCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) case RX_DESC3_L34T_IPV6_UDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) pkt_info->rss_hash_type = PKT_HASH_TYPE_L4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) pkt_info->rss_hash_type = PKT_HASH_TYPE_L3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* Get the pkt_info length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) desc_data->rx.len = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) RX_NORMAL_DESC3_PL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) RX_NORMAL_DESC3_PL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (!XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) RX_NORMAL_DESC3_LD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) RX_NORMAL_DESC3_LD_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* Not all the data has been transferred for this pkt_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) RX_PACKET_ATTRIBUTES_INCOMPLETE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* This is the last of the data for this pkt_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) RX_PACKET_ATTRIBUTES_INCOMPLETE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* Set checksum done indicator as appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (netdev->features & NETIF_F_RXCSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) RX_PACKET_ATTRIBUTES_CSUM_DONE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) /* Check for errors (only valid in last descriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) err = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) RX_NORMAL_DESC3_ES_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) RX_NORMAL_DESC3_ES_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) etlt = XLGMAC_GET_REG_BITS_LE(dma_desc->desc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) RX_NORMAL_DESC3_ETLT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) RX_NORMAL_DESC3_ETLT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (!err || !etlt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) /* No error if err is 0 or etlt is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if ((etlt == 0x09) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) pkt_info->vlan_ctag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) XLGMAC_GET_REG_BITS_LE(dma_desc->desc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) RX_NORMAL_DESC0_OVT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) RX_NORMAL_DESC0_OVT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) pkt_info->vlan_ctag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) if ((etlt == 0x05) || (etlt == 0x06))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) pkt_info->attributes = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) pkt_info->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) RX_PACKET_ATTRIBUTES_CSUM_DONE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pkt_info->errors = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) pkt_info->errors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) RX_PACKET_ERRORS_FRAME_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) RX_PACKET_ERRORS_FRAME_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) XLGMAC_PR("%s - descriptor=%u (cur=%d)\n", channel->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ring->cur & (ring->dma_desc_count - 1), ring->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static int xlgmac_enable_int(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) enum xlgmac_int int_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) unsigned int dma_ch_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) switch (int_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) case XLGMAC_INT_DMA_CH_SR_TI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) dma_ch_ier, DMA_CH_IER_TIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) DMA_CH_IER_TIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) case XLGMAC_INT_DMA_CH_SR_TPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) dma_ch_ier, DMA_CH_IER_TXSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) DMA_CH_IER_TXSE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) case XLGMAC_INT_DMA_CH_SR_TBU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) dma_ch_ier, DMA_CH_IER_TBUE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) DMA_CH_IER_TBUE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) case XLGMAC_INT_DMA_CH_SR_RI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) dma_ch_ier, DMA_CH_IER_RIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) DMA_CH_IER_RIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) case XLGMAC_INT_DMA_CH_SR_RBU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) dma_ch_ier, DMA_CH_IER_RBUE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) DMA_CH_IER_RBUE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) case XLGMAC_INT_DMA_CH_SR_RPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dma_ch_ier, DMA_CH_IER_RSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) DMA_CH_IER_RSE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) case XLGMAC_INT_DMA_CH_SR_TI_RI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) dma_ch_ier, DMA_CH_IER_TIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) DMA_CH_IER_TIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) dma_ch_ier, DMA_CH_IER_RIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) DMA_CH_IER_RIE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) case XLGMAC_INT_DMA_CH_SR_FBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) dma_ch_ier, DMA_CH_IER_FBEE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) DMA_CH_IER_FBEE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) case XLGMAC_INT_DMA_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) dma_ch_ier |= channel->saved_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static int xlgmac_disable_int(struct xlgmac_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) enum xlgmac_int int_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) unsigned int dma_ch_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) switch (int_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) case XLGMAC_INT_DMA_CH_SR_TI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) dma_ch_ier, DMA_CH_IER_TIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) DMA_CH_IER_TIE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) case XLGMAC_INT_DMA_CH_SR_TPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) dma_ch_ier, DMA_CH_IER_TXSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) DMA_CH_IER_TXSE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) case XLGMAC_INT_DMA_CH_SR_TBU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) dma_ch_ier, DMA_CH_IER_TBUE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) DMA_CH_IER_TBUE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) case XLGMAC_INT_DMA_CH_SR_RI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) dma_ch_ier, DMA_CH_IER_RIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) DMA_CH_IER_RIE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) case XLGMAC_INT_DMA_CH_SR_RBU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) dma_ch_ier, DMA_CH_IER_RBUE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) DMA_CH_IER_RBUE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) case XLGMAC_INT_DMA_CH_SR_RPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) dma_ch_ier, DMA_CH_IER_RSE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) DMA_CH_IER_RSE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) case XLGMAC_INT_DMA_CH_SR_TI_RI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) dma_ch_ier, DMA_CH_IER_TIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) DMA_CH_IER_TIE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) dma_ch_ier, DMA_CH_IER_RIE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) DMA_CH_IER_RIE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) case XLGMAC_INT_DMA_CH_SR_FBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) dma_ch_ier = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) dma_ch_ier, DMA_CH_IER_FBEE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) DMA_CH_IER_FBEE_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) case XLGMAC_INT_DMA_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) channel->saved_ier = dma_ch_ier & XLGMAC_DMA_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) dma_ch_ier &= ~XLGMAC_DMA_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) static int xlgmac_flush_tx_queues(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) unsigned int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) MTL_Q_TQOMR_FTQ_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) /* Poll Until Poll Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) for (i = 0; i < pdata->tx_q_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) count = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) regval = XLGMAC_GET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) MTL_Q_TQOMR_FTQ_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) while (--count && regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) static void xlgmac_config_dma_bus(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) regval = readl(pdata->mac_regs + DMA_SBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /* Set enhanced addressing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) DMA_SBMR_EAME_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* Set the System Bus mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) DMA_SBMR_UNDEF_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) DMA_SBMR_BLEN_256_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) writel(regval, pdata->mac_regs + DMA_SBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) static int xlgmac_hw_init(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) struct xlgmac_desc_ops *desc_ops = &pdata->desc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) /* Flush Tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) ret = xlgmac_flush_tx_queues(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* Initialize DMA related features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) xlgmac_config_dma_bus(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) xlgmac_config_osp_mode(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) xlgmac_config_pblx8(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) xlgmac_config_tx_pbl_val(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) xlgmac_config_rx_pbl_val(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) xlgmac_config_rx_coalesce(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) xlgmac_config_tx_coalesce(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) xlgmac_config_rx_buffer_size(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) xlgmac_config_tso_mode(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) xlgmac_config_sph_mode(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) xlgmac_config_rss(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) desc_ops->tx_desc_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) desc_ops->rx_desc_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) xlgmac_enable_dma_interrupts(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* Initialize MTL related features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) xlgmac_config_mtl_mode(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) xlgmac_config_queue_mapping(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) xlgmac_config_tsf_mode(pdata, pdata->tx_sf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) xlgmac_config_rsf_mode(pdata, pdata->rx_sf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) xlgmac_config_tx_threshold(pdata, pdata->tx_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) xlgmac_config_rx_threshold(pdata, pdata->rx_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) xlgmac_config_tx_fifo_size(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) xlgmac_config_rx_fifo_size(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) xlgmac_config_flow_control_threshold(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) xlgmac_config_rx_fep_enable(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) xlgmac_config_rx_fup_enable(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) xlgmac_enable_mtl_interrupts(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) /* Initialize MAC related features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) xlgmac_config_mac_address(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) xlgmac_config_rx_mode(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) xlgmac_config_jumbo_enable(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) xlgmac_config_flow_control(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) xlgmac_config_mac_speed(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) xlgmac_config_checksum_offload(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) xlgmac_config_vlan_support(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) xlgmac_config_mmc(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) xlgmac_enable_mac_interrupts(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) static int xlgmac_hw_exit(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) unsigned int count = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) /* Issue a software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) regval = readl(pdata->mac_regs + DMA_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) DMA_MR_SWR_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) writel(regval, pdata->mac_regs + DMA_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) usleep_range(10, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) /* Poll Until Poll Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) while (--count &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + DMA_MR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) DMA_MR_SWR_POS, DMA_MR_SWR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) hw_ops->init = xlgmac_hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) hw_ops->exit = xlgmac_hw_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) hw_ops->tx_complete = xlgmac_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) hw_ops->enable_tx = xlgmac_enable_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) hw_ops->disable_tx = xlgmac_disable_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) hw_ops->enable_rx = xlgmac_enable_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) hw_ops->disable_rx = xlgmac_disable_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) hw_ops->dev_xmit = xlgmac_dev_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) hw_ops->dev_read = xlgmac_dev_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) hw_ops->enable_int = xlgmac_enable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) hw_ops->disable_int = xlgmac_disable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) hw_ops->set_mac_address = xlgmac_set_mac_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) hw_ops->config_rx_mode = xlgmac_config_rx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) hw_ops->enable_rx_csum = xlgmac_enable_rx_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) hw_ops->disable_rx_csum = xlgmac_disable_rx_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) /* For MII speed configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) hw_ops->set_xlgmii_25000_speed = xlgmac_set_xlgmii_25000_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) hw_ops->set_xlgmii_40000_speed = xlgmac_set_xlgmii_40000_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) hw_ops->set_xlgmii_50000_speed = xlgmac_set_xlgmii_50000_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) hw_ops->set_xlgmii_100000_speed = xlgmac_set_xlgmii_100000_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* For descriptor related operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) hw_ops->tx_desc_init = xlgmac_tx_desc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) hw_ops->rx_desc_init = xlgmac_rx_desc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) hw_ops->tx_desc_reset = xlgmac_tx_desc_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) hw_ops->rx_desc_reset = xlgmac_rx_desc_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) hw_ops->is_last_desc = xlgmac_is_last_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) hw_ops->is_context_desc = xlgmac_is_context_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) hw_ops->tx_start_xmit = xlgmac_tx_start_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* For Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) hw_ops->config_tx_flow_control = xlgmac_config_tx_flow_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) hw_ops->config_rx_flow_control = xlgmac_config_rx_flow_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) /* For Vlan related config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) hw_ops->enable_rx_vlan_stripping = xlgmac_enable_rx_vlan_stripping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) hw_ops->disable_rx_vlan_stripping = xlgmac_disable_rx_vlan_stripping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) hw_ops->enable_rx_vlan_filtering = xlgmac_enable_rx_vlan_filtering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) hw_ops->disable_rx_vlan_filtering = xlgmac_disable_rx_vlan_filtering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) hw_ops->update_vlan_hash_table = xlgmac_update_vlan_hash_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) /* For RX coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) hw_ops->config_rx_coalesce = xlgmac_config_rx_coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) hw_ops->config_tx_coalesce = xlgmac_config_tx_coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) hw_ops->usec_to_riwt = xlgmac_usec_to_riwt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) hw_ops->riwt_to_usec = xlgmac_riwt_to_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) /* For RX and TX threshold config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) hw_ops->config_rx_threshold = xlgmac_config_rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) hw_ops->config_tx_threshold = xlgmac_config_tx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) /* For RX and TX Store and Forward Mode config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) hw_ops->config_rsf_mode = xlgmac_config_rsf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) hw_ops->config_tsf_mode = xlgmac_config_tsf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) /* For TX DMA Operating on Second Frame config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) hw_ops->config_osp_mode = xlgmac_config_osp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) /* For RX and TX PBL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) hw_ops->config_rx_pbl_val = xlgmac_config_rx_pbl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) hw_ops->get_rx_pbl_val = xlgmac_get_rx_pbl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) hw_ops->config_tx_pbl_val = xlgmac_config_tx_pbl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) hw_ops->get_tx_pbl_val = xlgmac_get_tx_pbl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) hw_ops->config_pblx8 = xlgmac_config_pblx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) /* For MMC statistics support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) hw_ops->tx_mmc_int = xlgmac_tx_mmc_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) hw_ops->rx_mmc_int = xlgmac_rx_mmc_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) hw_ops->read_mmc_stats = xlgmac_read_mmc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* For Receive Side Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) hw_ops->enable_rss = xlgmac_enable_rss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) hw_ops->disable_rss = xlgmac_disable_rss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) hw_ops->set_rss_hash_key = xlgmac_set_rss_hash_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) hw_ops->set_rss_lookup_table = xlgmac_set_rss_lookup_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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