^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is dual-licensed; you may select either version 2 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License ("GPL") or BSD license ("BSD").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This Synopsys DWC XLGMAC software driver and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (hereinafter the "Software") is an unsupported proprietary work of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Synopsys, Inc. unless otherwise expressly agreed to in writing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Synopsys and you. The Software IS NOT an item of Licensed Software or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Licensed Product under any End User Software License Agreement or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Agreement for Licensed Products with Synopsys or any supplement thereto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Synopsys is a registered trademark of Synopsys, Inc. Other names included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * in the SOFTWARE may be the trademarks of their respective owners.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "dwc-xlgmac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dwc-xlgmac-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int debug = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) NETIF_MSG_IFUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Currently it uses a static mac address for test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void xlgmac_default_config(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pdata->tx_osp_mode = DMA_OSP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pdata->tx_sf_mode = MTL_TSF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pdata->rx_sf_mode = MTL_RSF_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pdata->pblx8 = DMA_PBL_X8_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pdata->tx_pbl = DMA_PBL_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pdata->rx_pbl = DMA_PBL_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pdata->tx_threshold = MTL_TX_THRESHOLD_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pdata->rx_threshold = MTL_RX_THRESHOLD_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pdata->tx_pause = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pdata->rx_pause = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pdata->phy_speed = SPEED_25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pdata->sysclk_rate = XLGMAC_SYSCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xlgmac_init_desc_ops(&pdata->desc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) xlgmac_init_hw_ops(&pdata->hw_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int xlgmac_init(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct net_device *netdev = pdata->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Set default configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) xlgmac_default_config(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Set irq, base_addr, MAC address, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) netdev->irq = pdata->dev_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) netdev->base_addr = (unsigned long)pdata->mac_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) xlgmac_read_mac_addr(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Set all the function pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) xlgmac_init_all_ops(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Issue software reset to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) hw_ops->exit(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Populate the hardware features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) xlgmac_get_all_hw_features(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) xlgmac_print_all_hw_features(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* TODO: Set the PHY mode to XLGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Set the DMA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = dma_set_mask_and_coherent(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DMA_BIT_MASK(pdata->hw_feat.dma_width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Channel and ring params initializtion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * pdata->channel_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * pdata->tx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * pdata->rx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * pdata->tx_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * pdata->rx_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pdata->tx_desc_count = XLGMAC_TX_DESC_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pdata->tx_desc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pdata->rx_desc_count = XLGMAC_RX_DESC_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pdata->rx_desc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pdata->hw_feat.tx_ch_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pdata->hw_feat.tx_q_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pdata->tx_q_count = pdata->tx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(pdata->dev, "error setting real tx queue count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pdata->rx_ring_count = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) netif_get_num_default_rss_queues(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pdata->hw_feat.rx_ch_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pdata->hw_feat.rx_q_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pdata->rx_q_count = pdata->rx_ring_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(pdata->dev, "error setting real rx queue count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pdata->channel_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Initialize RSS hash key and lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pdata->rss_table[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MAC_RSSDR_DMCH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MAC_RSSDR_DMCH_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) i % pdata->rx_ring_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pdata->rss_options = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pdata->rss_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MAC_RSSCR_IP2TE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MAC_RSSCR_IP2TE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pdata->rss_options = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pdata->rss_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MAC_RSSCR_TCP4TE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MAC_RSSCR_TCP4TE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pdata->rss_options = XLGMAC_SET_REG_BITS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pdata->rss_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MAC_RSSCR_UDP4TE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MAC_RSSCR_UDP4TE_LEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Set device operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) netdev->netdev_ops = xlgmac_get_netdev_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) netdev->ethtool_ops = xlgmac_get_ethtool_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Set device features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (pdata->hw_feat.tso) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) netdev->hw_features = NETIF_F_TSO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) netdev->hw_features |= NETIF_F_TSO6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) netdev->hw_features |= NETIF_F_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) netdev->hw_features |= NETIF_F_IP_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) netdev->hw_features |= NETIF_F_IPV6_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else if (pdata->hw_feat.tx_coe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) netdev->hw_features = NETIF_F_IP_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) netdev->hw_features |= NETIF_F_IPV6_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (pdata->hw_feat.rx_coe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) netdev->hw_features |= NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) netdev->hw_features |= NETIF_F_GRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pdata->hw_feat.rss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) netdev->hw_features |= NETIF_F_RXHASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) netdev->vlan_features |= netdev->hw_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (pdata->hw_feat.sa_vlan_ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (pdata->hw_feat.vlhash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) netdev->features |= netdev->hw_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pdata->netdev_features = netdev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) netdev->priv_flags |= IFF_UNICAST_FLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Use default watchdog timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) netdev->watchdog_timeo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Tx coalesce parameters initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Rx coalesce parameters initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct xlgmac_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) XLGMAC_MAX_DMA_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "alloc_etherdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SET_NETDEV_DEV(netdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_set_drvdata(dev, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pdata = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pdata->netdev = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pdata->dev_irq = res->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pdata->mac_regs = res->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mutex_init(&pdata->rss_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pdata->msg_enable = netif_msg_init(debug, default_msg_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = xlgmac_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(dev, "xlgmac init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto err_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = register_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(dev, "net device registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto err_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err_free_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int xlgmac_drv_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct net_device *netdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unregister_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct xlgmac_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct xlgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) desc_data->dma_desc, &desc_data->dma_desc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) netdev_dbg(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) le32_to_cpu(dma_desc->desc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) le32_to_cpu(dma_desc->desc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) le32_to_cpu(dma_desc->desc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) le32_to_cpu(dma_desc->desc3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct xlgmac_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct xlgmac_desc_data *desc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct xlgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dma_desc = desc_data->dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) desc_data->dma_desc, &desc_data->dma_desc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) netdev_dbg(pdata->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) le32_to_cpu(dma_desc->desc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) le32_to_cpu(dma_desc->desc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) le32_to_cpu(dma_desc->desc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) le32_to_cpu(dma_desc->desc3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void xlgmac_print_pkt(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct sk_buff *skb, bool tx_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ethhdr *eth = (struct ethhdr *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned char buffer[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) netdev_dbg(netdev, "\n************** SKB dump ****************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) netdev_dbg(netdev, "%s packet of %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (tx_rx ? "TX" : "RX"), skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < skb->len; i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int len = min(skb->len - i, 32U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hex_dump_to_buffer(&skb->data[i], len, 32, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) buffer, sizeof(buffer), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) netdev_dbg(netdev, "\n************** SKB dump ****************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct xlgmac_hw_features *hw_feat = &pdata->hw_feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) memset(hw_feat, 0, sizeof(*hw_feat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hw_feat->version = readl(pdata->mac_regs + MAC_VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Hardware feature register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MAC_HWF0R_PHYIFSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MAC_HWF0R_PHYIFSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MAC_HWF0R_VLHASH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MAC_HWF0R_VLHASH_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MAC_HWF0R_SMASEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MAC_HWF0R_SMASEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MAC_HWF0R_RWKSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MAC_HWF0R_RWKSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MAC_HWF0R_MGKSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MAC_HWF0R_MGKSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MAC_HWF0R_MMCSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MAC_HWF0R_MMCSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MAC_HWF0R_ARPOFFSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MAC_HWF0R_ARPOFFSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MAC_HWF0R_TSSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MAC_HWF0R_TSSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MAC_HWF0R_EEESEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MAC_HWF0R_EEESEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MAC_HWF0R_TXCOESEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MAC_HWF0R_TXCOESEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MAC_HWF0R_RXCOESEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MAC_HWF0R_RXCOESEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MAC_HWF0R_ADDMACADRSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MAC_HWF0R_ADDMACADRSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MAC_HWF0R_TSSTSSEL_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MAC_HWF0R_TSSTSSEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MAC_HWF0R_SAVLANINS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MAC_HWF0R_SAVLANINS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Hardware feature register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MAC_HWF1R_RXFIFOSIZE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MAC_HWF1R_RXFIFOSIZE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MAC_HWF1R_TXFIFOSIZE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MAC_HWF1R_TXFIFOSIZE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MAC_HWF1R_ADVTHWORD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MAC_HWF1R_ADVTHWORD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MAC_HWF1R_ADDR64_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MAC_HWF1R_ADDR64_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MAC_HWF1R_DCBEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MAC_HWF1R_DCBEN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MAC_HWF1R_SPHEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MAC_HWF1R_SPHEN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MAC_HWF1R_TSOEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MAC_HWF1R_TSOEN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MAC_HWF1R_DBGMEMA_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MAC_HWF1R_DBGMEMA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MAC_HWF1R_RSSEN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MAC_HWF1R_RSSEN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MAC_HWF1R_NUMTC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MAC_HWF1R_NUMTC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MAC_HWF1R_HASHTBLSZ_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MAC_HWF1R_HASHTBLSZ_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MAC_HWF1R_L3L4FNUM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MAC_HWF1R_L3L4FNUM_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Hardware feature register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MAC_HWF2R_RXQCNT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MAC_HWF2R_RXQCNT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MAC_HWF2R_TXQCNT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MAC_HWF2R_TXQCNT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MAC_HWF2R_RXCHCNT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MAC_HWF2R_RXCHCNT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MAC_HWF2R_TXCHCNT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MAC_HWF2R_TXCHCNT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MAC_HWF2R_PPSOUTNUM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MAC_HWF2R_PPSOUTNUM_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MAC_HWF2R_AUXSNAPNUM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MAC_HWF2R_AUXSNAPNUM_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Translate the Hash Table size into actual number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch (hw_feat->hash_table_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hw_feat->hash_table_size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hw_feat->hash_table_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hw_feat->hash_table_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Translate the address width setting into actual number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (hw_feat->dma_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hw_feat->dma_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hw_feat->dma_width = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hw_feat->dma_width = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hw_feat->dma_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* The Queue, Channel and TC counts are zero based so increment them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * to get the actual number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) hw_feat->rx_q_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hw_feat->tx_q_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hw_feat->rx_ch_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hw_feat->tx_ch_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hw_feat->tc_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) char __maybe_unused *str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) XLGMAC_PR("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) XLGMAC_PR("=====================================================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) XLGMAC_PR("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) XLGMAC_PR("HW support following features\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) XLGMAC_PR("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* HW Feature Register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) XLGMAC_PR("VLAN Hash Filter Selected : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pdata->hw_feat.vlhash ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) XLGMAC_PR("SMA (MDIO) Interface : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pdata->hw_feat.sma ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pdata->hw_feat.rwk ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) XLGMAC_PR("PMT Magic Packet Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdata->hw_feat.mgk ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) XLGMAC_PR("RMON/MMC Module Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pdata->hw_feat.mmc ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) XLGMAC_PR("ARP Offload Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pdata->hw_feat.aoe ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pdata->hw_feat.ts ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pdata->hw_feat.eee ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pdata->hw_feat.tx_coe ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) XLGMAC_PR("Receive Checksum Offload Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pdata->hw_feat.rx_coe ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pdata->hw_feat.addn_mac ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) switch (pdata->hw_feat.ts_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) str = "RESERVED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) str = "INTERNAL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) str = "EXTERNAL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) str = "BOTH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) XLGMAC_PR("Timestamp System Time Source : %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pdata->hw_feat.sa_vlan_ins ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* HW Feature Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) switch (pdata->hw_feat.rx_fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) str = "128 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) str = "256 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) str = "512 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) str = "1 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) str = "2 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) str = "4 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) str = "8 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) str = "16 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) str = "32 kBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) str = "64 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) str = "128 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) str = "256 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) str = "RESERVED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) XLGMAC_PR("MTL Receive FIFO Size : %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (pdata->hw_feat.tx_fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) str = "128 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) str = "256 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) str = "512 bytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) str = "1 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) str = "2 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) str = "4 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) str = "8 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) str = "16 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) str = "32 kBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) str = "64 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) str = "128 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) str = "256 KBytes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) str = "RESERVED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pdata->hw_feat.adv_ts_hi ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) XLGMAC_PR("Address width : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pdata->hw_feat.dma_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) XLGMAC_PR("DCB Feature Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pdata->hw_feat.dcb ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) XLGMAC_PR("Split Header Feature Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pdata->hw_feat.sph ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) XLGMAC_PR("TCP Segmentation Offload Enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pdata->hw_feat.tso ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) XLGMAC_PR("DMA Debug Registers Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pdata->hw_feat.dma_debug ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) XLGMAC_PR("RSS Feature Enabled : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pdata->hw_feat.rss ? "YES" : "NO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) XLGMAC_PR("Number of Traffic classes : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (pdata->hw_feat.tc_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) XLGMAC_PR("Hash Table Size : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pdata->hw_feat.hash_table_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) XLGMAC_PR("Total number of L3 or L4 Filters : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pdata->hw_feat.l3l4_filter_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* HW Feature Register2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) XLGMAC_PR("Number of MTL Receive Queues : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pdata->hw_feat.rx_q_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) XLGMAC_PR("Number of MTL Transmit Queues : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pdata->hw_feat.tx_q_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) XLGMAC_PR("Number of DMA Receive Channels : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) pdata->hw_feat.rx_ch_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) XLGMAC_PR("Number of DMA Transmit Channels : %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pdata->hw_feat.tx_ch_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (pdata->hw_feat.pps_out_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) str = "No PPS output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) str = "1 PPS output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) str = "2 PPS output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) str = "3 PPS output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) str = "4 PPS output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) str = "RESERVED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) XLGMAC_PR("Number of PPS Outputs : %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) switch (pdata->hw_feat.aux_snap_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) str = "No auxiliary input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) str = "1 auxiliary input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) str = "2 auxiliary input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) str = "3 auxiliary input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) str = "4 auxiliary input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) str = "RESERVED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) XLGMAC_PR("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) XLGMAC_PR("=====================================================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) XLGMAC_PR("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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