^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Once again I am out to prove that every ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * controller out there can be most efficiently programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * if you make it look like a LANCE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996, 1999, 2003, 2006, 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/idprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/openprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/auxio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "sunqe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRV_NAME "sunqe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRV_VERSION "4.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRV_RELDATE "August 27, 2008"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_AUTHOR(DRV_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct sunqec *root_qec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void qe_set_multicast(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QEC_RESET_TRIES 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline int qec_global_reset(void __iomem *gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int tries = QEC_RESET_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 tmp = sbus_readl(gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (tmp & GLOB_CTRL_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MACE_RESET_RETRIES 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QE_RESET_RETRIES 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int qe_stop(struct sunqe *qep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *cregs = qep->qcregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *mregs = qep->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Reset the MACE, then the QEC channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tries = MACE_RESET_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (tmp & MREGS_BCONFIG_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tries = QE_RESET_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 tmp = sbus_readl(cregs + CREG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (tmp & CREG_CTRL_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void qe_init_rings(struct sunqe *qep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct qe_init_block *qb = qep->qe_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct sunqe_buffers *qbufs = qep->buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) __u32 qbufs_dvma = (__u32)qep->buffers_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) memset(qb, 0, sizeof(struct qe_init_block));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) memset(qbufs, 0, sizeof(struct sunqe_buffers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) qb->qe_rxd[i].rx_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int qe_init(struct sunqe *qep, int from_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct sunqec *qecp = qep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __iomem *cregs = qep->qcregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *mregs = qep->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *gregs = qecp->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char *e = &qep->dev->dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __u32 qblk_dvma = (__u32)qep->qblock_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Shut it up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (qe_stop(qep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Setup initial rx/tx init block pointers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sbus_writel(qblk_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sbus_writel(qblk_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Enable/mask the various irq's. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sbus_writel(0, cregs + CREG_RIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sbus_writel(1, cregs + CREG_TIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sbus_writel(0, cregs + CREG_QMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Setup the FIFO pointers into QEC local memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sbus_readl(gregs + GLOB_RSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Clear the channel collision counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sbus_writel(0, cregs + CREG_CCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* For 10baseT, inter frame space nor throttle seems to be necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sbus_writel(0, cregs + CREG_PIPG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Now dork with the AMD MACE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sbus_writeb(0, mregs + MREGS_RXFCNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* The QEC dma's the rx'd packets from local memory out to main memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * and therefore it interrupts when the packet reception is "complete".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * So don't listen for the MACE talking about it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mregs + MREGS_FCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Only usable interface on QuadEther is twisted pair. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Tell MACE we are changing the ether address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sbus_writeb(e[0], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sbus_writeb(e[1], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sbus_writeb(e[2], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sbus_writeb(e[3], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sbus_writeb(e[4], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sbus_writeb(e[5], mregs + MREGS_ETHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Clear out the address filter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sbus_writeb(0, mregs + MREGS_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Address changes are now complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sbus_writeb(0, mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) qe_init_rings(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Wait a little bit for the link to come up... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int tries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (tries == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Missed packet counter is cleared on a read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sbus_readb(mregs + MREGS_MPCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Reload multicast information, this will enable the receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * and transmitter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) qe_set_multicast(qep->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* QEC should now start to show interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Grrr, certain error conditions completely lock up the AMD MACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * so when we get these we _must_ reset the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct net_device *dev = qep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int mace_hwbug_workaround = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (qe_status & CREG_STAT_EDEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (qe_status & CREG_STAT_CLOSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (qe_status & CREG_STAT_ERETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (qe_status & CREG_STAT_LCOLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (qe_status & CREG_STAT_FUFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (qe_status & CREG_STAT_JERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) printk(KERN_ERR "%s: Jabber error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (qe_status & CREG_STAT_BERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) printk(KERN_ERR "%s: Babble error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (qe_status & CREG_STAT_CCOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev->stats.tx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev->stats.collisions += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (qe_status & CREG_STAT_TXDERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (qe_status & CREG_STAT_TXLERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (qe_status & CREG_STAT_TXPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (qe_status & CREG_STAT_TXSERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (qe_status & CREG_STAT_RCCOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev->stats.rx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev->stats.collisions += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (qe_status & CREG_STAT_RUOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev->stats.rx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev->stats.rx_over_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (qe_status & CREG_STAT_MCOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev->stats.rx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev->stats.rx_missed_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (qe_status & CREG_STAT_RXFOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (qe_status & CREG_STAT_RLCOLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (qe_status & CREG_STAT_FCOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev->stats.rx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev->stats.rx_frame_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (qe_status & CREG_STAT_CECOFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev->stats.rx_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev->stats.rx_crc_errors += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (qe_status & CREG_STAT_RXDROP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev->stats.rx_missed_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (qe_status & CREG_STAT_RXSMALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (qe_status & CREG_STAT_RXLERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) printk(KERN_ERR "%s: Receive late error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (qe_status & CREG_STAT_RXPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev->stats.rx_missed_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (qe_status & CREG_STAT_RXSERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev->stats.rx_missed_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mace_hwbug_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (mace_hwbug_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) qe_init(qep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return mace_hwbug_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Per-QE receive interrupt service routine. Just like on the happy meal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * we receive directly into skb's with a small packet copy water mark.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void qe_rx(struct sunqe *qep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct net_device *dev = qep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct qe_rxd *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct sunqe_buffers *qbufs = qep->buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __u32 qbufs_dvma = (__u32)qep->buffers_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int elem = qep->rx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) this = &rxbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) while (!((flags = this->rx_flags) & RXD_OWN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned char *this_qbuf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __u32 this_qbuf_dvma = qbufs_dvma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct qe_rxd *end_rxd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Check for errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (len < ETH_ZLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) skb_reserve(skb, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) skb_copy_to_linear_data(skb, this_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) skb->protocol = eth_type_trans(skb, qep->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) end_rxd->rx_addr = this_qbuf_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) elem = NEXT_RX(elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) this = &rxbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) qep->rx_new = elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void qe_tx_reclaim(struct sunqe *qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Interrupts for all QE's get filtered out via the QEC master controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * so we just run through each qe and check to see who is signaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * and thus needs to be serviced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static irqreturn_t qec_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sunqec *qecp = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 qec_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Latch the status now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) while (channel < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (qec_status & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct sunqe *qep = qecp->qes[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 qe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) qe_status = sbus_readl(qep->qcregs + CREG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (qe_status & CREG_STAT_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (qe_is_bolixed(qep, qe_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (qe_status & CREG_STAT_RXIRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) qe_rx(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (netif_queue_stopped(qep->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (qe_status & CREG_STAT_TXIRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) spin_lock(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) qe_tx_reclaim(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (TX_BUFFS_AVAIL(qep) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Wake net queue and return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * lazy tx reclaim.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) netif_wake_queue(qep->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sbus_writel(1, qep->qcregs + CREG_TIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_unlock(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) qec_status >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int qe_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) qep->mconfig = (MREGS_MCONFIG_TXENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MREGS_MCONFIG_RXENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MREGS_MCONFIG_MBAENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return qe_init(qep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int qe_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) qe_stop(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Reclaim TX'd frames from the ring. This must always run under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * the IRQ protected qep->lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void qe_tx_reclaim(struct sunqe *qep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int elem = qep->tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) while (elem != qep->tx_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 flags = txbase[elem].tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (flags & TXD_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) elem = NEXT_TX(elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) qep->tx_old = elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void qe_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int tx_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spin_lock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Try to reclaim, if that frees up some tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * entries, we're fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) qe_tx_reclaim(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tx_full = TX_BUFFS_AVAIL(qep) <= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spin_unlock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (! tx_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) qe_init(qep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Get a packet queued to go onto the wire. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static netdev_tx_t qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct sunqe_buffers *qbufs = qep->buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __u32 txbuf_dvma, qbufs_dvma = (__u32)qep->buffers_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned char *txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int len, entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spin_lock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) qe_tx_reclaim(qep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) entry = qep->tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) txbuf_dvma = qbufs_dvma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Avoid a race... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) skb_copy_from_linear_data(skb, txbuf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) qep->qe_block->qe_txd[entry].tx_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) qep->tx_new = NEXT_TX(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Get it going. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev->stats.tx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (TX_BUFFS_AVAIL(qep) <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Halt the net queue and enable tx interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * When the tx queue empties the tx irq handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * will wake up the queue and return us back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * the lazy tx reclaim scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) sbus_writel(0, qep->qcregs + CREG_TIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void qe_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 new_mconfig = qep->mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Lock out others. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) qep->mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) new_mconfig |= MREGS_MCONFIG_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u16 hash_table[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 *hbytes = (unsigned char *) &hash_table[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) memset(hash_table, 0, sizeof(hash_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) crc = ether_crc_le(6, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) crc >>= 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) hash_table[crc >> 4] |= 1 << (crc & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Program the qe with the new filter value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) qep->mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 tmp = *hbytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Any change of the logical address filter, the physical address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * or enabling/disabling promiscuous mode causes the MACE to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * the receiver. So we must re-enable them here or else the MACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * refuses to listen to anything on the network. Sheesh, took
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * me a day or two to find this bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) qep->mconfig = new_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Let us get going again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Ethtool support... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const struct linux_prom_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) strlcpy(info->driver, "sunqe", sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) strlcpy(info->version, "3.0", sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) op = qep->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regs = of_get_property(op->dev.of_node, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) snprintf(info->bus_info, sizeof(info->bus_info), "SBUS:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) regs->which_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static u32 qe_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct sunqe *qep = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) void __iomem *mregs = qep->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 phyconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) spin_lock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) spin_unlock_irq(&qep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return phyconfig & MREGS_PHYCONFIG_LSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct ethtool_ops qe_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .get_drvinfo = qe_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .get_link = qe_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* This is only called once at boot time for each card probed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void qec_init_once(struct sunqec *qecp, struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 bsizes = qecp->qec_bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (sbus_can_burst64() && (bsizes & DMA_BURST64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else if (bsizes & DMA_BURST32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Packetsize only used in 100baseT BigMAC configurations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * set it to zero just to be on the safe side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Set the local memsize register, divided up to one piece per QE channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sbus_writel((resource_size(&op->resource[1]) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) qecp->gregs + GLOB_MSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Divide up the local QEC memory amongst the 4 QE receiver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * transmitter FIFOs. Basically it is (total / 2 / num_channels).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) qecp->gregs + GLOB_TSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) qecp->gregs + GLOB_RSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static u8 qec_get_burst(struct device_node *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u8 bsizes, bsizes_more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Find and set the burst sizes for the QEC, since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * does the actual dma for all 4 channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bsizes &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (bsizes_more != 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) bsizes &= bsizes_more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (bsizes & DMA_BURST32)==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) bsizes = (DMA_BURST32 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return bsizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static struct sunqec *get_qec(struct platform_device *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct platform_device *op = to_platform_device(child->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct sunqec *qecp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) qecp = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!qecp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (qecp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) qecp->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) qecp->gregs = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GLOB_REG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "QEC Global Registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!qecp->gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Make sure the QEC is in MACE mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ctrl &= 0xf0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ctrl != GLOB_CTRL_MMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) printk(KERN_ERR "qec: Not in MACE mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (qec_global_reset(qecp->gregs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) qecp->qec_bursts = qec_get_burst(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) qec_init_once(qecp, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (request_irq(op->archdata.irqs[0], qec_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) IRQF_SHARED, "qec", (void *) qecp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) printk(KERN_ERR "qec: Can't register irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) platform_set_drvdata(op, qecp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) qecp->next_module = root_qec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) root_qec_dev = qecp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return qecp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (qecp->gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) of_iounmap(&op->resource[0], qecp->gregs, GLOB_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) kfree(qecp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct net_device_ops qec_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .ndo_open = qe_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ndo_stop = qe_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .ndo_start_xmit = qe_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .ndo_set_rx_mode = qe_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .ndo_tx_timeout = qe_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int qec_ether_init(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static unsigned version_printed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct sunqec *qecp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct sunqe *qe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int i, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) printk(KERN_INFO "%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev = alloc_etherdev(sizeof(struct sunqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) qe = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) res = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) i = of_getintprop_default(op->dev.of_node, "channel#", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (i == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) qe->channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) spin_lock_init(&qe->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) qecp = get_qec(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!qecp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) qecp->qes[qe->channel] = qe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) qe->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) qe->parent = qecp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) qe->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) res = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) qe->qcregs = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) CREG_REG_SIZE, "QEC Channel Registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!qe->qcregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) printk(KERN_ERR "qe: Cannot map channel registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) qe->mregs = of_ioremap(&op->resource[1], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MREGS_REG_SIZE, "QE MACE Registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!qe->mregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) printk(KERN_ERR "qe: Cannot map MACE registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) qe->qe_block = dma_alloc_coherent(&op->dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &qe->qblock_dvma, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) qe->buffers = dma_alloc_coherent(&op->dev, sizeof(struct sunqe_buffers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &qe->buffers_dvma, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) qe->buffers == NULL || qe->buffers_dvma == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Stop this QE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) qe_stop(qe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SET_NETDEV_DEV(dev, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev->watchdog_timeo = 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev->irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev->dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev->ethtool_ops = &qe_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev->netdev_ops = &qec_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) res = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) platform_set_drvdata(op, qe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) printk(KERN_INFO "%s: qe channel[%d] %pM\n", dev->name, qe->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (qe->qcregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) of_iounmap(&op->resource[0], qe->qcregs, CREG_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (qe->mregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) of_iounmap(&op->resource[1], qe->mregs, MREGS_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (qe->qe_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dma_free_coherent(&op->dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) qe->qe_block, qe->qblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (qe->buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dma_free_coherent(&op->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sizeof(struct sunqe_buffers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) qe->buffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) qe->buffers_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int qec_sbus_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return qec_ether_init(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int qec_sbus_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct sunqe *qp = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct net_device *net_dev = qp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unregister_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) of_iounmap(&op->resource[0], qp->qcregs, CREG_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) of_iounmap(&op->resource[1], qp->mregs, MREGS_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dma_free_coherent(&op->dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) qp->qe_block, qp->qblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dma_free_coherent(&op->dev, sizeof(struct sunqe_buffers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) qp->buffers, qp->buffers_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) free_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct of_device_id qec_sbus_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = "qe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) MODULE_DEVICE_TABLE(of, qec_sbus_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct platform_driver qec_sbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .name = "qec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .of_match_table = qec_sbus_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .probe = qec_sbus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .remove = qec_sbus_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int __init qec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return platform_driver_register(&qec_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static void __exit qec_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) platform_driver_unregister(&qec_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) while (root_qec_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct sunqec *next = root_qec_dev->next_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct platform_device *op = root_qec_dev->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) free_irq(op->archdata.irqs[0], (void *) root_qec_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) of_iounmap(&op->resource[0], root_qec_dev->gregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GLOB_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) kfree(root_qec_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) root_qec_dev = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) module_init(qec_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) module_exit(qec_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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