^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: sunhme.h,v 1.33 2001/08/03 06:23:04 davem Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Also known as the "Happy Meal".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _SUNHME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _SUNHME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Happy Meal global registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GREG_SWRESET 0x000UL /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GREG_CFG 0x004UL /* Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GREG_STAT 0x100UL /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GREG_IMASK 0x104UL /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GREG_REG_SIZE 0x108UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Global reset register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GREG_RESET_ETX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GREG_RESET_ERX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GREG_RESET_ALL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Global config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GREG_CFG_BURSTMSK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GREG_CFG_BURST16 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GREG_CFG_BURST32 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GREG_CFG_BURST64 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GREG_CFG_64BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GREG_CFG_PARITY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GREG_CFG_RESV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Global status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* All interesting error conditions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GREG_STAT_ERRORS 0xfc7efefc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Global interrupt mask register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Happy Meal external transmitter registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ETX_PENDING 0x00UL /* Transmit pending/wakeup register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ETX_CFG 0x04UL /* Transmit config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ETX_RING 0x08UL /* Transmit ring pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ETX_BBASE 0x0cUL /* Transmit buffer base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ETX_BDISP 0x10UL /* Transmit buffer displacement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ETX_SMACHINE 0x28UL /* Transmitter state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ETX_RSIZE 0x2cUL /* Ring descriptor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ETX_BPTR 0x30UL /* Transmit data buffer ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ETX_REG_SIZE 0x34UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* ETX transmit pending register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* ETX config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ETX_RSIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Happy Meal external receiver registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ERX_CFG 0x00UL /* Receiver config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ERX_RING 0x04UL /* Receiver ring ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ERX_BPTR 0x08UL /* Receiver buffer ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ERX_FIFORPTR 0x14UL /* FIFO read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ERX_SMACHINE 0x1cUL /* Receiver state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ERX_REG_SIZE 0x20UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* ERX config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ERX_CFG_RESV1 0x00000006 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ERX_CFG_RESV2 0x000001c0 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ERX_CFG_RESV3 0x0000f800 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * in halfwords. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BMAC_XIFCFG 0x0000UL /* XIF config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 0x4-->0x204, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BMAC_STIME 0x21cUL /* Transmit slot time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BMAC_TXSDELIM 0x228UL /* Transmit delimiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BMAC_JSIZE 0x22cUL /* Jam size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BMAC_TXMAX 0x230UL /* Transmit max pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BMAC_TXMIN 0x234UL /* Transmit min pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BMAC_RSEED 0x250UL /* Transmit random number seed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* 0x258-->0x304, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BMAC_RXCFG 0x30cUL /* Receiver config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BMAC_RXMAX 0x310UL /* Receive max pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BMAC_RXMIN 0x314UL /* Receive min pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* 0x33c, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BMAC_AFMASK 0x35cUL /* Address filter mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BMAC_REG_SIZE 0x360UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* BigMac XIF config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* BigMac transmit config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* BigMac receive config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define BIGMAC_RXCFG_REJME 0x00000200 /* Reject packets addressed to me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* These are the "Management Interface" (ie. MIF) registers of the transceiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TCVR_BBCLOCK 0x00UL /* Bit bang clock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TCVR_BBDATA 0x04UL /* Bit bang data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TCVR_BBOENAB 0x08UL /* Bit bang output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TCVR_FRAME 0x0cUL /* Frame control/data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TCVR_CFG 0x10UL /* MIF config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TCVR_IMASK 0x14UL /* MIF interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TCVR_STATUS 0x18UL /* MIF status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TCVR_SMACHINE 0x1cUL /* MIF state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TCVR_REG_SIZE 0x20UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Frame commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FRAME_WRITE 0x50020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FRAME_READ 0x60020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Transceiver config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TCV_CFG_PSELECT 0x00000001 /* Select PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Here are some PHY addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TCV_PADDR_ETX 0 /* Internal transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TCV_PADDR_ITX 1 /* External transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Transceiver status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Inside the Happy Meal transceiver is the physical layer, they use an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * implementations for National Semiconductor, part number DP83840VCE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * You can retrieve the data sheets and programming docs for this beast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * from http://www.national.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * The DP83840 is capable of both 10 and 100Mbps ethernet, in both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * half and full duplex mode. It also supports auto negotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Debugging eeprom burnt code is more fun than programming this chip!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Generic MII registers defined in linux/mii.h, these below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * are DP83840 specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DP83840_CSCONFIG 0x17 /* CS configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* The Carrier Sense config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CSCONFIG_RESV1 0x0001 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CSCONFIG_RESV2 0x0008 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CSCONFIG_RESV3 0x0700 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CSCONFIG_RESV4 0x4000 /* Unused... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Happy Meal descriptor rings and such.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * All descriptor rings must be aligned on a 2K boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * All receive buffers must be 64 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Always write the address first before setting the ownership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * bits to avoid races with the hardware scanning the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) typedef u32 __bitwise hme32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct happy_meal_rxd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hme32 rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hme32 rx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct happy_meal_txd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) hme32 tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hme32 tx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TXFLAG_SOP 0x40000000 /* 1 = start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TXFLAG_EOP 0x20000000 /* 1 = end of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TXFLAG_SIZE 0x00003fff /* Size of the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TX_RING_SIZE 32 /* Must be >16 and <255, multiple of 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define RX_RING_SIZE 32 /* see ERX_CFG_SIZE* for possible values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #error TX_RING_SIZE holds illegal value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TX_RING_MAXSIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RX_RING_MAXSIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* We use a 14 byte offset for checksum computation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #if (RX_RING_SIZE == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #if (RX_RING_SIZE == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #if (RX_RING_SIZE == 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if (RX_RING_SIZE == 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #error RX_RING_SIZE holds illegal value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TX_BUFFS_AVAIL(hp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (((hp)->tx_old <= (hp)->tx_new) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (hp)->tx_old - (hp)->tx_new - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define RX_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define RX_COPY_THRESHOLD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct hmeal_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define hblock_offset(mem, elem) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Now software state stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) enum happy_transceiver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) external = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) internal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) none = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Timer state engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum happy_timer_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) arbwait = 0, /* Waiting for auto negotiation to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lupwait = 1, /* Auto-neg complete, awaiting link-up status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ltrywait = 2, /* Forcing try of all modes, from fastest to slowest. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) asleep = 3, /* Time inactive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct quattro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Happy happy, joy joy! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct happy_meal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) void __iomem *gregs; /* Happy meal global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 (*read_desc32)(hme32 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void (*write_txd)(struct happy_meal_txd *, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* This is either an platform_device or a pci_dev. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void *happy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spinlock_t happy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct sk_buff *rx_skbs[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct sk_buff *tx_skbs[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int rx_new, tx_new, rx_old, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 (*read32)(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void (*write32)(void __iomem *, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void __iomem *etxregs; /* External transmitter regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void __iomem *erxregs; /* External receiver regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void __iomem *bigmacregs; /* BIGMAC core regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void __iomem *tcvregs; /* MIF transceiver regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dma_addr_t hblock_dvma; /* DVMA visible address happy block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int happy_flags; /* Driver state flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum happy_transceiver tcvr_type; /* Kind of transceiver in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int happy_bursts; /* Get your mind out of the gutter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int paddr; /* PHY address for transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned short hm_revision; /* Happy meal revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned short sw_bmcr; /* SW copy of BMCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned short sw_bmsr; /* SW copy of BMSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned short sw_physid1; /* SW copy of PHYSID1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned short sw_physid2; /* SW copy of PHYSID2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned short sw_advertise; /* SW copy of ADVERTISE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned short sw_lpa; /* SW copy of LPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned short sw_expansion; /* SW copy of EXPANSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned short sw_csconfig; /* SW copy of CSCONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int auto_speed; /* Auto-nego link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int forced_speed; /* Force mode link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int poll_data; /* MIF poll data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int poll_flag; /* MIF poll flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int linkcheck; /* Have we checked the link yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int lnkup; /* Is the link up as far as we know? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int lnkdown; /* Trying to force the link down? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int lnkcnt; /* Counter for link-up attempts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct timer_list happy_timer; /* To watch the link when coming up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) enum happy_timer_state timer_state; /* State of the auto-neg timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int timer_ticks; /* Number of clicks at each state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct net_device *dev; /* Backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct quattro *qfe_parent; /* For Quattro cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int qfe_ent; /* Which instance on quattro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Here are the happy flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define HFLAG_POLL 0x00000001 /* We are doing MIF polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define HFLAG_FULL 0x00000020 /* Full duplex enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define HFLAG_POLLENABLE 0x00000080 /* Actually try MIF polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define HFLAG_INIT 0x00000200 /* Init called at least once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Support for QFE/Quattro cards. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct quattro {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct net_device *happy_meals[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* This is either a sbus_dev or a pci_dev. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void *quattro_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct quattro *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* PROM ranges, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct linux_prom_ranges ranges[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int nranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* We use this to acquire receive skb's that we can DMA directly into. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ALIGNED_RX_SKB_ADDR(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define happy_meal_alloc_skb(__length, __gfp_flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ({ struct sk_buff *__skb; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if(__skb) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if(__offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) skb_reserve(__skb, __offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __skb; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif /* !(_SUNHME_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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