^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * auto carrier detecting ethernet driver. Also known as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * "Happy Meal Ethernet" found on SunSwift SBUS cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996, 1998, 1999, 2002, 2003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2006, 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Changes :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - port to non-sparc architectures. Tested only on x86 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * only currently works with QFE PCI cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - ability to specify the MAC address at module load time by passing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/idprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/openprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/auxio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "sunhme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRV_NAME "sunhme"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRV_VERSION "3.10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRV_RELDATE "August 26, 2008"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_AUTHOR(DRV_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int macaddr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) module_param_array(macaddr, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct quattro *qfe_sbus_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct quattro *qfe_pci_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #undef HMEDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #undef SXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #undef RXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #undef TXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #undef TXLOGGING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifdef TXLOGGING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct hme_tx_logent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int tstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int tx_new, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TXLOG_ACTION_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TXLOG_ACTION_TXMIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TXLOG_ACTION_TBUSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TXLOG_ACTION_NBUFS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TX_LOG_LEN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct hme_tx_logent tx_log[TX_LOG_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int txlog_cur_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct hme_tx_logent *tlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tlp = &tx_log[txlog_cur_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tlp->tstamp = (unsigned int)jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tlp->tx_new = hp->tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tlp->tx_old = hp->tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tlp->action = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tlp->status = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static __inline__ void tx_dump_log(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i, this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) this = txlog_cur_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < TX_LOG_LEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tx_log[this].tstamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tx_log[this].tx_new, tx_log[this].tx_old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tx_log[this].action, tx_log[this].status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) this = (this + 1) & (TX_LOG_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static __inline__ void tx_dump_ring(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct hmeal_init_block *hb = hp->happy_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (i = 0; i < TX_RING_SIZE; i+=4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) i, i + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define tx_add_log(hp, a, s) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define tx_dump_log() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define tx_dump_ring(hp) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #ifdef HMEDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HMD(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HMD(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* #define AUTO_SWITCH_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef AUTO_SWITCH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ASD(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ASD(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DEFAULT_IPG0 16 /* For lance-mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DEFAULT_IPG1 8 /* For all modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DEFAULT_IPG2 4 /* For all modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DEFAULT_JAMSIZE 4 /* Toe jam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* NOTE: In the descriptor writes one _must_ write the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * member _first_. The card must not be allowed to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * the updated descriptor flags until the address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * correct. I've added a write memory barrier between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * the two stores so that I can sleep well at night... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void sbus_hme_write32(void __iomem *reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sbus_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u32 sbus_hme_read32(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return sbus_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rxd->rx_addr = (__force hme32)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rxd->rx_flags = (__force hme32)flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) txd->tx_addr = (__force hme32)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) txd->tx_flags = (__force hme32)flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static u32 sbus_hme_read_desc32(hme32 *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return (__force u32)*p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void pci_hme_write32(void __iomem *reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static u32 pci_hme_read32(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) txd->tx_addr = (__force hme32)cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) txd->tx_flags = (__force hme32)cpu_to_le32(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static u32 pci_hme_read_desc32(hme32 *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return le32_to_cpup((__le32 *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define hme_write32(__hp, __reg, __val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ((__hp)->write32((__reg), (__val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define hme_read32(__hp, __reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ((__hp)->read32(__reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define hme_write_txd(__hp, __txd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ((__hp)->write_txd((__txd), (__flags), (__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define hme_read_desc32(__hp, __p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ((__hp)->read_desc32(__p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define hme_dma_map(__hp, __ptr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define hme_dma_unmap(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* SBUS only compilation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define hme_write32(__hp, __reg, __val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sbus_writel((__val), (__reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define hme_read32(__hp, __reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sbus_readl(__reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_wmb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define hme_write_txd(__hp, __txd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dma_wmb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define hme_dma_map(__hp, __ptr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define hme_dma_unmap(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PCI only compilation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define hme_write32(__hp, __reg, __val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel((__val), (__reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define hme_read32(__hp, __reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) readl(__reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_wmb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define hme_write_txd(__hp, __txd, __flags, __addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dma_wmb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return le32_to_cpup((__le32 *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define hme_dma_map(__hp, __ptr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define hme_dma_unmap(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) hme_write32(hp, tregs + TCVR_BBDATA, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = hme_read32(hp, tregs + TCVR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret &= TCV_CFG_MDIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret &= TCV_CFG_MDIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) retval = hme_read32(hp, tregs + TCVR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) retval &= TCV_CFG_MDIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) retval &= TCV_CFG_MDIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int happy_meal_bb_read(struct happy_meal *hp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void __iomem *tregs, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ASD(("happy_meal_bb_read: reg=%d ", reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Enable the MIF BitBang outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hme_write32(hp, tregs + TCVR_BBOENAB, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Force BitBang into the idle state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Give it the read sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) BB_PUT_BIT(hp, tregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) BB_PUT_BIT(hp, tregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Give it the PHY address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tmp = hp->paddr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 4; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Tell it what register we want to read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) tmp = (reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (i = 4; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Close down the MIF BitBang outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hme_write32(hp, tregs + TCVR_BBOENAB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Now read in the value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (i = 15; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ASD(("value=%x\n", retval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void happy_meal_bb_write(struct happy_meal *hp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void __iomem *tregs, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Enable the MIF BitBang outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) hme_write32(hp, tregs + TCVR_BBOENAB, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Force BitBang into the idle state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Give it write sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) BB_PUT_BIT(hp, tregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BB_PUT_BIT(hp, tregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Give it the PHY address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tmp = (hp->paddr & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 4; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Tell it what register we will be writing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tmp = (reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (i = 4; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Tell it to become ready for the bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BB_PUT_BIT(hp, tregs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BB_PUT_BIT(hp, tregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (i = 15; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Close down the MIF BitBang outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hme_write32(hp, tregs + TCVR_BBOENAB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TCVR_READ_TRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int happy_meal_tcvr_read(struct happy_meal *hp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void __iomem *tregs, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int tries = TCVR_READ_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (hp->tcvr_type == none) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ASD(("no transceiver, value=TCVR_FAILURE\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return TCVR_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!(hp->happy_flags & HFLAG_FENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ASD(("doing bit bang\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return happy_meal_bb_read(hp, tregs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hme_write32(hp, tregs + TCVR_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return TCVR_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ASD(("value=%04x\n", retval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TCVR_WRITE_TRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void happy_meal_tcvr_write(struct happy_meal *hp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void __iomem *tregs, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int tries = TCVR_WRITE_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Welcome to Sun Microsystems, can I take your order please? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!(hp->happy_flags & HFLAG_FENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) happy_meal_bb_write(hp, tregs, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Would you like fries with that? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hme_write32(hp, tregs + TCVR_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (FRAME_WRITE | (hp->paddr << 23) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ((reg & 0xff) << 18) | (value & 0xffff)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Anything else? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Fifty-two cents is your change, have a nice day. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Auto negotiation. The scheme is very simple. We have a timer routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * that keeps watching the auto negotiation process as it progresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * The DP83840 is first told to start doing it's thing, we set up the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * and place the timer state machine in it's initial state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Here the timer peeks at the DP83840 status registers at each click to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * if the auto negotiation has completed, we assume here that the DP83840 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * will time out at some point and just tell us what (didn't) happen. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * complete coverage we only allow so many of the ticks at this level to run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * when this has expired we print a warning message and try another strategy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * This "other" strategy is to force the interface into various speed/duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * configurations and we stop when we see a link-up condition before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * maximum number of "peek" ticks have occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Once a valid link status has been detected we configure the BigMAC and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * the rest of the Happy Meal to speak the most efficient protocol we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * get a clean link for. The priority for link configurations, highest first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * 100 Base-T Full Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * 100 Base-T Half Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * 10 Base-T Full Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * 10 Base-T Half Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * We start a new timer now, after a successful auto negotiation status has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * been detected. This timer just waits for the link-up bit to get set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * the BMCR of the DP83840. When this occurs we print a kernel log message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * describing the link type in use and the fact that it is up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * If a fatal error of some sort is signalled and detected in the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * service routine, and the chip is reset, or the link is ifconfig'd down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * and then back up, this entire process repeats itself all over again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Downgrade from full to half duplex. Only possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * via ethtool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (hp->sw_bmcr & BMCR_FULLDPLX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hp->sw_bmcr &= ~(BMCR_FULLDPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Downgrade from 100 to 10. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (hp->sw_bmcr & BMCR_SPEED100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hp->sw_bmcr &= ~(BMCR_SPEED100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* We've tried everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (hp->tcvr_type == external)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) printk("external ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) printk("internal ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) printk("transceiver at ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (hp->sw_lpa & LPA_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) printk("100Mb/s, Full Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) printk("100Mb/s, Half Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (hp->sw_lpa & LPA_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) printk("10Mb/s, Full Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) printk("10Mb/s, Half Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (hp->tcvr_type == external)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) printk("external ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) printk("internal ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) printk("transceiver at ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (hp->sw_bmcr & BMCR_SPEED100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) printk("100Mb/s, ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) printk("10Mb/s, ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (hp->sw_bmcr & BMCR_FULLDPLX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) printk("Full Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) printk("Half Duplex.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* All we care about is making sure the bigmac tx_cfg has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * proper duplex setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (hp->timer_state == arbwait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto no_response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (hp->sw_lpa & LPA_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else if (hp->sw_lpa & LPA_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else if (hp->sw_lpa & LPA_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Forcing a link mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (hp->sw_bmcr & BMCR_FULLDPLX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Before changing other bits in the tx_cfg register, and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * general any of other the TX config registers too, you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * must:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * 1) Clear Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * 2) Poll with reads until that bit reads back as zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * 3) Make TX configuration changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * 4) Set Enable once more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ~(BIGMAC_TXCFG_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) hp->happy_flags |= HFLAG_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) BIGMAC_TXCFG_FULLDPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hp->happy_flags &= ~(HFLAG_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ~(BIGMAC_TXCFG_FULLDPLX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) BIGMAC_TXCFG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) no_response:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int happy_meal_init(struct happy_meal *hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int is_lucent_phy(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) void __iomem *tregs = hp->tcvregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned short mr2, mr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mr2 = happy_meal_tcvr_read(hp, tregs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mr3 = happy_meal_tcvr_read(hp, tregs, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if ((mr2 & 0xffff) == 0x0180 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ((mr3 & 0xffff) >> 10) == 0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void happy_meal_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct happy_meal *hp = from_timer(hp, t, happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void __iomem *tregs = hp->tcvregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int restart_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) hp->timer_ticks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) switch(hp->timer_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case arbwait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Only allow for 5 ticks, thats 10 seconds and much too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * long to wait for arbitration to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (hp->timer_ticks >= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Enter force mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) do_force_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hp->sw_bmcr = BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* OK, seems we need do disable the transceiver for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * tick to make sure we get an accurate link state at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * second tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) hp->timer_state = ltrywait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Anything interesting happen? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Just what we've been waiting for... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = set_happy_link_modes(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Ooops, something bad happened, go to force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * XXX Broken hubs which don't support 802.3u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * XXX auto-negotiation make this happen as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto do_force_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Success, at least so far, advance our state engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) hp->timer_state = lupwait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case lupwait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Auto negotiation was successful and we are awaiting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * link up status. I have decided to let this timer run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * forever until some sort of error is signalled, reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * a message to the user at 10 second intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (hp->sw_bmsr & BMSR_LSTATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Wheee, it's up, display the link mode in use and put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * the timer to sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) display_link_mode(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) hp->timer_state = asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) restart_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (hp->timer_ticks >= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "not completely up.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case ltrywait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Making the timeout here too long can make it take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * annoyingly long to attempt all of the link mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * permutations, but then again this is essentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * error recovery code for the most part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (hp->timer_ticks == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Re-enable transceiver, we'll re-enable the transceiver next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * tick, then check link state on the following tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) hp->sw_csconfig |= CSCONFIG_TCVDISAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) happy_meal_tcvr_write(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DP83840_CSCONFIG, hp->sw_csconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (hp->timer_ticks == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) happy_meal_tcvr_write(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DP83840_CSCONFIG, hp->sw_csconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (hp->sw_bmsr & BMSR_LSTATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Force mode selection success. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) display_forced_link_mode(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) set_happy_link_modes(hp, tregs); /* XXX error? then what? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) hp->timer_state = asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) restart_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = try_next_permutation(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Aieee, tried them all, reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * chip and try all over again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Let the user know... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) printk(KERN_NOTICE "%s: Link down, cable problem?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = happy_meal_init(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* ho hum... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) printk(KERN_ERR "%s: Error, cannot re-init the "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "Happy Meal.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) DP83840_CSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hp->sw_csconfig |= CSCONFIG_TCVDISAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) happy_meal_tcvr_write(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) DP83840_CSCONFIG, hp->sw_csconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) restart_timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case asleep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Can't happens.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) restart_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hp->timer_state = asleep; /* foo on you */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (restart_timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) add_timer(&hp->happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define TX_RESET_TRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define RX_RESET_TRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int tries = TX_RESET_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) HMD(("happy_meal_tx_reset: reset, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Would you like to try our SMCC Delux? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Lettuce, tomato, buggy hardware (no extra charge)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Take care. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int tries = RX_RESET_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) HMD(("happy_meal_rx_reset: reset, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* We have a special on GNU/Viking hardware bugs today. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* Will that be all? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Don't forget your vik_1137125_wa. Have a nice day. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define STOP_TRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int tries = STOP_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) HMD(("happy_meal_stop: reset, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* We're consolidating our STB products, it's your lucky day. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Come back next week when we are "Sun Microelectronics". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) printk(KERN_ERR "happy meal: Fry guys.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Remember: "Different name, same old buggy as shit hardware." */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct net_device_stats *stats = &hp->dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hme_write32(hp, bregs + BMAC_UNALECTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hme_write32(hp, bregs + BMAC_GLECTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) stats->collisions +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (hme_read32(hp, bregs + BMAC_EXCTR) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) hme_read32(hp, bregs + BMAC_LTCTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) hme_write32(hp, bregs + BMAC_EXCTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) hme_write32(hp, bregs + BMAC_LTCTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ASD(("happy_meal_poll_stop: "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* If polling disabled or not polling already, nothing to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) (HFLAG_POLLENABLE | HFLAG_POLL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) HMD(("not polling, return\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Shut up the MIF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ASD(("were polling, mif ints off, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Turn off polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ASD(("polling off, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* We are no longer polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) hp->happy_flags &= ~(HFLAG_POLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* Let the bits set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ASD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Only Sun can take such nice parts and fuck up the programming interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * like this. Good job guys...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define TCVR_RESET_TRIES 16 /* It should reset quickly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 tconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int result, tries = TCVR_RESET_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) tconfig = hme_read32(hp, tregs + TCVR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (hp->tcvr_type == external) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ASD(("external<"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) hp->tcvr_type = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) hp->paddr = TCV_PADDR_ITX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ASD(("ISOLATE,"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) happy_meal_tcvr_write(hp, tregs, MII_BMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (result == TCVR_FAILURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ASD(("phyread_fail>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ASD(("phyread_ok,PSELECT>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) hp->tcvr_type = external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) hp->paddr = TCV_PADDR_ETX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (tconfig & TCV_CFG_MDIO1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ASD(("internal<PSELECT,"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ASD(("ISOLATE,"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) happy_meal_tcvr_write(hp, tregs, MII_BMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (result == TCVR_FAILURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ASD(("phyread_fail>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ASD(("phyread_ok,~PSELECT>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) hp->tcvr_type = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hp->paddr = TCV_PADDR_ITX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ASD(("BMCR_RESET "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (result == TCVR_FAILURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) hp->sw_bmcr = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!(result & BMCR_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ASD(("BMCR RESET FAILED!\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ASD(("RESET_OK\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Get fresh copies of the PHY registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ASD(("UNISOLATE"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) hp->sw_bmcr &= ~(BMCR_ISOLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) tries = TCVR_UNISOLATE_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) while (--tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (result == TCVR_FAILURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!(result & BMCR_ISOLATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ASD((" FAILED!\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) result = happy_meal_tcvr_read(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) DP83840_CSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) happy_meal_tcvr_write(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Figure out whether we have an internal or external transceiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * hp->happy_lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (hp->happy_flags & HFLAG_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* If we are polling, we must stop to get the transceiver type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ASD(("<polling> "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (hp->tcvr_type == internal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (tconfig & TCV_CFG_MDIO1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ASD(("<internal> <poll stop> "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) happy_meal_poll_stop(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) hp->paddr = TCV_PADDR_ETX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) hp->tcvr_type = external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ASD(("<external>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tconfig &= ~(TCV_CFG_PENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) tconfig |= TCV_CFG_PSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) hme_write32(hp, tregs + TCVR_CFG, tconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (hp->tcvr_type == external) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ASD(("<external> "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ASD(("<poll stop> "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) happy_meal_poll_stop(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) hp->paddr = TCV_PADDR_ITX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) hp->tcvr_type = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ASD(("<internal>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hme_read32(hp, tregs + TCVR_CFG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ~(TCV_CFG_PSELECT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ASD(("\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ASD(("<none>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 reread = hme_read32(hp, tregs + TCVR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Else we can just work off of the MDIO bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ASD(("<not polling> "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (reread & TCV_CFG_MDIO1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) hp->paddr = TCV_PADDR_ETX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) hp->tcvr_type = external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ASD(("<external>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (reread & TCV_CFG_MDIO0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tconfig & ~(TCV_CFG_PSELECT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) hp->paddr = TCV_PADDR_ITX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) hp->tcvr_type = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ASD(("<internal>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) printk(KERN_ERR "happy meal: Transceiver and a coke please.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) hp->tcvr_type = none; /* Grrr... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ASD(("<none>\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* The receive ring buffers are a bit tricky to get right. Here goes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * The buffers we dma into must be 64 byte aligned. So we use a special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * alloc_skb() routine for the happy meal to allocate 64 bytes more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * we really need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * We use skb_reserve() to align the data block we get in the skb. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * also program the etxregs->cfg register to use an offset of 2. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * imperical constant plus the ethernet header size will always leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * us with a nicely aligned ip header once we pass things up to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * protocol layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * The numbers work out to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * Max ethernet frame size 1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * Ethernet header size 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Happy Meal base offset 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * Say a skb data area is at 0xf001b010, and its size alloced is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * First our alloc_skb() routine aligns the data base to a 64 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * boundary. We now have 0xf001b040 as our skb data address. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * plug this into the receive descriptor address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * So now the data we will end up looking at starts at 0xf001b042. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * the packet arrives, we will check out the size received and subtract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * this from the skb->length. Then we just pass the packet up to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * protocols as is, and allocate a new skb to replace this slot we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * just received from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * The ethernet layer will strip the ether header from the front of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * skb we just sent to it, this leaves us with the ip header sitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Happy Meal has even checksummed the tcp/udp data for us. The 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * bit checksum is obtained from the low bits of the receive descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * flags, thus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * skb->csum = rxd->rx_flags & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * before sending off the skb to the protocols, and we are good as gold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static void happy_meal_clean_rings(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (hp->rx_skbs[i] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct sk_buff *skb = hp->rx_skbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct happy_meal_rxd *rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) rxd = &hp->happy_block->happy_meal_rxd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dma_unmap_single(hp->dma_dev, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) hp->rx_skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (hp->tx_skbs[i] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct sk_buff *skb = hp->tx_skbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct happy_meal_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u32 dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) hp->tx_skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) txd = &hp->happy_block->happy_meal_txd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dma_addr = hme_read_desc32(hp, &txd->tx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dma_unmap_single(hp->dma_dev, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) (hme_read_desc32(hp, &txd->tx_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) & TXFLAG_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dma_unmap_page(hp->dma_dev, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) (hme_read_desc32(hp, &txd->tx_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) & TXFLAG_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (frag != skb_shinfo(skb)->nr_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static void happy_meal_init_rings(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct hmeal_init_block *hb = hp->happy_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) HMD(("happy_meal_init_rings: counters to zero, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Free any skippy bufs left around in the rings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) HMD(("clean, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) happy_meal_clean_rings(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Now get new skippy bufs for the receive ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) HMD(("init rxring, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) hp->rx_skbs[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Because we reserve afterwards. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) mapping = dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (dma_mapping_error(hp->dma_dev, mapping)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) hme_write_rxd(hp, &hb->happy_meal_rxd[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) skb_reserve(skb, RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) HMD(("init txring, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) happy_meal_begin_auto_negotiation(struct happy_meal *hp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) void __iomem *tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) const struct ethtool_link_ksettings *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* Read all of the registers we are interested in now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!ep || ep->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Advertise everything we can support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (hp->sw_bmsr & BMSR_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) hp->sw_advertise |= (ADVERTISE_10HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) hp->sw_advertise &= ~(ADVERTISE_10HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (hp->sw_bmsr & BMSR_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hp->sw_advertise |= (ADVERTISE_10FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) hp->sw_advertise &= ~(ADVERTISE_10FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (hp->sw_bmsr & BMSR_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) hp->sw_advertise |= (ADVERTISE_100HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) hp->sw_advertise &= ~(ADVERTISE_100HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (hp->sw_bmsr & BMSR_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) hp->sw_advertise |= (ADVERTISE_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) hp->sw_advertise &= ~(ADVERTISE_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * XXX and this is because the DP83840 does not support it, changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * XXX would need to be made to the tx/rx logic in the driver as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * XXX so I completely skip checking for it in the BMSR for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #ifdef AUTO_SWITCH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ASD(("%s: Advertising [ ", hp->dev->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (hp->sw_advertise & ADVERTISE_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ASD(("10H "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (hp->sw_advertise & ADVERTISE_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ASD(("10F "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (hp->sw_advertise & ADVERTISE_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ASD(("100H "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (hp->sw_advertise & ADVERTISE_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ASD(("100F "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Enable Auto-Negotiation, this is usually on already... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) hp->sw_bmcr |= BMCR_ANENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Restart it to make sure it is going. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) hp->sw_bmcr |= BMCR_ANRESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* BMCR_ANRESTART self clears when the process has begun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) timeout = 64; /* More than enough. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!(hp->sw_bmcr & BMCR_ANRESTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break; /* got it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) printk(KERN_NOTICE "%s: Performing force link detection.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto force_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) hp->timer_state = arbwait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) force_link:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* Force the link up, trying first a particular mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * Either we are here at the request of ethtool or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * because the Happy Meal would not start to autoneg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Disable auto-negotiation in BMCR, enable the duplex and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * speed setting, init the timer state machine, and fire it off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!ep || ep->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) hp->sw_bmcr = BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (ep->base.speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) hp->sw_bmcr = BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) hp->sw_bmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ep->base.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) hp->sw_bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!is_lucent_phy(hp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* OK, seems we need do disable the transceiver for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * tick to make sure we get an accurate link state at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * second tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) DP83840_CSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hp->sw_csconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) hp->timer_state = ltrywait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) add_timer(&hp->happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int happy_meal_init(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) void __iomem *gregs = hp->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) void __iomem *etxregs = hp->etxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) void __iomem *erxregs = hp->erxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) void __iomem *bregs = hp->bigmacregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) void __iomem *tregs = hp->tcvregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u32 regtmp, rxcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) unsigned char *e = &hp->dev->dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* If auto-negotiation timer is running, kill it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) del_timer(&hp->happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) HMD(("happy_meal_init: happy_flags[%08x] ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) hp->happy_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!(hp->happy_flags & HFLAG_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) HMD(("set HFLAG_INIT, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) hp->happy_flags |= HFLAG_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) happy_meal_get_counters(hp, bregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Stop polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) HMD(("to happy_meal_poll_stop\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) happy_meal_poll_stop(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Stop transmitter and receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) HMD(("happy_meal_init: to happy_meal_stop\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) happy_meal_stop(hp, gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* Alloc and reset the tx/rx descriptor chains. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) HMD(("happy_meal_init: to happy_meal_init_rings\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) happy_meal_init_rings(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Shut up the MIF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) hme_read32(hp, tregs + TCVR_IMASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* See if we can enable the MIF frame on this card to speak to the DP83840. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (hp->happy_flags & HFLAG_FENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) HMD(("use frame old[%08x], ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) hme_read32(hp, tregs + TCVR_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) HMD(("use bitbang old[%08x], ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) hme_read32(hp, tregs + TCVR_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Check the state of the transceiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) HMD(("to happy_meal_transceiver_check\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) happy_meal_transceiver_check(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Put the Big Mac into a sane state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) HMD(("happy_meal_init: "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) switch(hp->tcvr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* Cannot operate if we don't know the transceiver type! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) HMD(("AAIEEE no transceiver type, EAGAIN"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case internal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Using the MII buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) HMD(("internal, using MII, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) hme_write32(hp, bregs + BMAC_XIFCFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) case external:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Not using the MII, disable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) HMD(("external, disable MII, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (happy_meal_tcvr_reset(hp, tregs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Reset the Happy Meal Big Mac transceiver and the receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) HMD(("tx/rx reset, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) happy_meal_tx_reset(hp, bregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) happy_meal_rx_reset(hp, bregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Set jam size and inter-packet gaps to reasonable defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) HMD(("jsize/ipg1/ipg2, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Load up the MAC address and random seed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) HMD(("rseed/macaddr, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* The docs recommend to use the 10LSB of our MAC here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) HMD(("htable, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if ((hp->dev->flags & IFF_ALLMULTI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) (netdev_mc_count(hp->dev) > 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) u16 hash_table[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) memset(hash_table, 0, sizeof(hash_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) netdev_for_each_mc_addr(ha, hp->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) crc = ether_crc_le(6, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) crc >>= 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) hash_table[crc >> 4] |= 1 << (crc & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) hme_write32(hp, bregs + BMAC_HTABLE3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) hme_write32(hp, bregs + BMAC_HTABLE2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) hme_write32(hp, bregs + BMAC_HTABLE1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) hme_write32(hp, bregs + BMAC_HTABLE0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* Set the RX and TX ring ptrs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) hme_write32(hp, erxregs + ERX_RING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) hme_write32(hp, etxregs + ETX_RING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* Parity issues in the ERX unit of some HME revisions can cause some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * registers to not be written unless their parity is even. Detect such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * lost writes and simply rewrite with a low bit set (which will be ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * since the rxring needs to be 2K aligned).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (hme_read32(hp, erxregs + ERX_RING) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) hme_write32(hp, erxregs + ERX_RING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) | 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* Set the supported burst sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) HMD(("happy_meal_init: old[%08x] bursts<",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) hme_read32(hp, gregs + GREG_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #ifndef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* It is always PCI and can handle 64byte bursts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if ((hp->happy_bursts & DMA_BURST64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ((hp->happy_flags & HFLAG_PCI) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) || sbus_can_burst64()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) || 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) u32 gcfg = GREG_CFG_BURST64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* I have no idea if I should set the extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * transfer mode bit for Cheerio, so for now I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * do not. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if ((hp->happy_flags & HFLAG_PCI) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct platform_device *op = hp->happy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (sbus_can_dma_64bit()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) sbus_set_sbus64(&op->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) hp->happy_bursts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) gcfg |= GREG_CFG_64BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) HMD(("64>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) hme_write32(hp, gregs + GREG_CFG, gcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) } else if (hp->happy_bursts & DMA_BURST32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) HMD(("32>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) } else if (hp->happy_bursts & DMA_BURST16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) HMD(("16>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) HMD(("XXX>"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) hme_write32(hp, gregs + GREG_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #endif /* CONFIG_SPARC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* Turn off interrupts we do not want to hear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) HMD((", enable global interrupts, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) hme_write32(hp, gregs + GREG_IMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* Set the transmit ring buffer size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) hme_read32(hp, etxregs + ETX_RSIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* Enable transmitter DVMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) HMD(("tx dma enable old[%08x], ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) hme_read32(hp, etxregs + ETX_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) hme_write32(hp, etxregs + ETX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* This chip really rots, for the receiver sometimes when you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * write to its control registers not all the bits get there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * properly. I cannot think of a sane way to provide complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * coverage for this hardware bug yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) HMD(("erx regs bug old[%08x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hme_read32(hp, erxregs + ERX_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) regtmp = hme_read32(hp, erxregs + ERX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* XXX Should return failure here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* Enable Big Mac hash table filter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) hme_read32(hp, bregs + BMAC_RXCFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (hp->dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) rxcfg |= BIGMAC_RXCFG_PMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* Let the bits settle in the chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* Ok, configure the Big Mac transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) HMD(("BIGMAC init, "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) regtmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (hp->happy_flags & HFLAG_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) regtmp |= BIGMAC_TXCFG_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* Don't turn on the "don't give up" bit for now. It could cause hme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * to deadlock with the PHY if a Jabber occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Give up after 16 TX attempts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) hme_write32(hp, bregs + BMAC_ALIMIT, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* Enable the output drivers no matter what. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) regtmp = BIGMAC_XCFG_ODENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* If card can do lance mode, enable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (hp->happy_flags & HFLAG_LANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* Disable the MII buffers if using external transceiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (hp->tcvr_type == external)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) regtmp |= BIGMAC_XCFG_MIIDISAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) HMD(("XIF config old[%08x], ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) hme_read32(hp, bregs + BMAC_XIFCFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* Start things up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) HMD(("tx old[%08x] and rx [%08x] ON!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) hme_read32(hp, bregs + BMAC_TXCFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) hme_read32(hp, bregs + BMAC_RXCFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Set larger TX/RX size to allow for 802.1q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) hme_write32(hp, bregs + BMAC_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) hme_write32(hp, bregs + BMAC_RXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* Get the autonegotiation started, and the watch timer ticking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) happy_meal_begin_auto_negotiation(hp, tregs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /* Success. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) void __iomem *tregs = hp->tcvregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) void __iomem *bregs = hp->bigmacregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) void __iomem *gregs = hp->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) happy_meal_stop(hp, gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (hp->happy_flags & HFLAG_FENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) hme_write32(hp, tregs + TCVR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) happy_meal_transceiver_check(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) switch(hp->tcvr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) case none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) case internal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) hme_write32(hp, bregs + BMAC_XIFCFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case external:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (happy_meal_tcvr_reset(hp, tregs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Latch PHY registers as of now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* Advertise everything we can support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (hp->sw_bmsr & BMSR_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) hp->sw_advertise |= (ADVERTISE_10HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) hp->sw_advertise &= ~(ADVERTISE_10HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (hp->sw_bmsr & BMSR_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) hp->sw_advertise |= (ADVERTISE_10FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) hp->sw_advertise &= ~(ADVERTISE_10FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (hp->sw_bmsr & BMSR_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) hp->sw_advertise |= (ADVERTISE_100HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) hp->sw_advertise &= ~(ADVERTISE_100HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (hp->sw_bmsr & BMSR_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) hp->sw_advertise |= (ADVERTISE_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) hp->sw_advertise &= ~(ADVERTISE_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Update the PHY advertisement register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* Once status is latched (by happy_meal_interrupt) it is cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * the hardware, so we cannot re-read it and get a correct value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * hp->happy_lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) int reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* Only print messages for non-counter related interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) GREG_STAT_SLVPERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) hp->dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (status & GREG_STAT_RFIFOVF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* Receive FIFO overflow is harmless and the hardware will take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) care of it, just some packets are lost. Who cares. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (status & GREG_STAT_STSTERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* BigMAC SQE link test failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (status & GREG_STAT_TFIFO_UND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* Transmit FIFO underrun, again DMA error likely. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (status & GREG_STAT_MAXPKTERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* Driver error, tried to transmit something larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * than ethernet max mtu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (status & GREG_STAT_NORXD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* This is harmless, it just means the system is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * quite loaded and the incoming packet rate was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * faster than the interrupt handler could keep up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) printk(KERN_INFO "%s: Happy Meal out of receive "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) "descriptors, packet dropped.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* All sorts of DMA receive errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (status & GREG_STAT_RXERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) printk("GenericError ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (status & GREG_STAT_RXPERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) printk("ParityError ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (status & GREG_STAT_RXTERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) printk("RxTagBotch ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (status & GREG_STAT_EOPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* Driver bug, didn't set EOP bit in tx descriptor given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * to the happy meal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (status & GREG_STAT_MIFIRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* MIF signalled an interrupt, were we polling it? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* All sorts of transmit DMA errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (status & GREG_STAT_TXEACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) printk("GenericError ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (status & GREG_STAT_TXLERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) printk("LateError ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (status & GREG_STAT_TXPERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) printk("ParityError ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (status & GREG_STAT_TXTERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) printk("TagBotch ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* Bus or parity error when cpu accessed happy meal registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * or it's internal FIFO's. Should never see this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) hp->dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) happy_meal_init(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static void happy_meal_mif_interrupt(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) void __iomem *tregs = hp->tcvregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* Use the fastest transmission protocol possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (hp->sw_lpa & LPA_100FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) } else if (hp->sw_lpa & LPA_100HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) hp->sw_bmcr |= BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) } else if (hp->sw_lpa & LPA_10FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) hp->sw_bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* Finally stop polling and shut up the MIF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) happy_meal_poll_stop(hp, tregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #ifdef TXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define TXD(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define TXD(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* hp->happy_lock must be held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void happy_meal_tx(struct happy_meal *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct happy_meal_txd *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct net_device *dev = hp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) int elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) elem = hp->tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) TXD(("TX<"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) while (elem != hp->tx_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u32 flags, dma_addr, dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) int frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) TXD(("[%d]", elem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) this = &txbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) flags = hme_read_desc32(hp, &this->tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (flags & TXFLAG_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) skb = hp->tx_skbs[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (skb_shinfo(skb)->nr_frags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) last = elem + skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) last &= (TX_RING_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) flags = hme_read_desc32(hp, &txbase[last].tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (flags & TXFLAG_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hp->tx_skbs[elem] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) dev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dma_addr = hme_read_desc32(hp, &this->tx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dma_len = hme_read_desc32(hp, &this->tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dma_len &= TXFLAG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (!frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) elem = NEXT_TX(elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) this = &txbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) hp->tx_old = elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) TXD((">"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (netif_queue_stopped(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #ifdef RXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define RXD(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define RXD(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* Originally I used to handle the allocation failure by just giving back just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * that one ring buffer to the happy meal. Problem is that usually when that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * condition is triggered, the happy meal expects you to do something reasonable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * with all of the packets it has DMA'd in. So now I just drop the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * ring when we cannot get a new skb and give them all back to the happy meal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * maybe things will be "happier" now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * hp->happy_lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct happy_meal_rxd *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) int elem = hp->rx_new, drops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) RXD(("RX<"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) this = &rxbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) int len = flags >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) u16 csum = flags & RXFLAG_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) RXD(("[%d ", elem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* Check for errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RXD(("ERR(%08x)]", flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (len < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (len & (RXFLAG_OVERFLOW >> 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* Return it to the Happy meal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) drop_it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) hme_write_rxd(hp, this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) skb = hp->rx_skbs[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (len > RX_COPY_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct sk_buff *new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) u32 mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* Now refill the entry, if we can. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (new_skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) drops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) goto drop_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) mapping = dma_map_single(hp->dma_dev, new_skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) RX_BUF_ALLOC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dev_kfree_skb_any(new_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) drops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) goto drop_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) hp->rx_skbs[elem] = new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) hme_write_rxd(hp, this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) skb_reserve(new_skb, RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* Trim the original skb for the netif. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) skb_trim(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (copy_skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) drops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) goto drop_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) skb_reserve(copy_skb, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) skb_put(copy_skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) skb_copy_from_linear_data(skb, copy_skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dma_sync_single_for_device(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* Reuse original ring buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) hme_write_rxd(hp, this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) skb = copy_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* This card is _fucking_ hot... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) skb->csum = csum_unfold(~(__force __sum16)htons(csum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) RXD(("len=%d csum=%4x]", len, csum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) elem = NEXT_RX(elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) this = &rxbase[elem];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) hp->rx_new = elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (drops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) RXD((">"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) HMD(("happy_meal_interrupt: status=%08x ", happy_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) spin_lock(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (happy_status & GREG_STAT_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) HMD(("ERRORS "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (happy_status & GREG_STAT_MIFIRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) HMD(("MIFIRQ "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) happy_meal_mif_interrupt(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (happy_status & GREG_STAT_TXALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) HMD(("TXALL "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) happy_meal_tx(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) if (happy_status & GREG_STAT_RXTOHOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) HMD(("RXTOHOST "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) happy_meal_rx(hp, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) spin_unlock(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct quattro *qp = (struct quattro *) cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) struct net_device *dev = qp->happy_meals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) HMD(("quattro_interrupt: status=%08x ", happy_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (!(happy_status & (GREG_STAT_ERRORS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) GREG_STAT_MIFIRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) GREG_STAT_TXALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) GREG_STAT_RXTOHOST)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) spin_lock(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (happy_status & GREG_STAT_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) HMD(("ERRORS "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (happy_meal_is_not_so_happy(hp, happy_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (happy_status & GREG_STAT_MIFIRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) HMD(("MIFIRQ "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) happy_meal_mif_interrupt(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (happy_status & GREG_STAT_TXALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) HMD(("TXALL "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) happy_meal_tx(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) if (happy_status & GREG_STAT_RXTOHOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) HMD(("RXTOHOST "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) happy_meal_rx(hp, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) spin_unlock(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) HMD(("done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static int happy_meal_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) HMD(("happy_meal_open: "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * into a single source which we register handling at probe time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) res = request_irq(hp->irq, happy_meal_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) HMD(("EAGAIN\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) hp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) HMD(("to happy_meal_init\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) res = happy_meal_init(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) free_irq(hp->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static int happy_meal_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) happy_meal_stop(hp, hp->gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) happy_meal_clean_rings(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* If auto-negotiation timer is running, kill it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) del_timer(&hp->happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* On Quattro QFE cards, all hme interrupts are concentrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * into a single source which we register handling at probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * time and never unregister.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) free_irq(hp->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #ifdef SXDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define SXD(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define SXD(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static void happy_meal_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) tx_dump_log();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) hme_read32(hp, hp->gregs + GREG_STAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) hme_read32(hp, hp->etxregs + ETX_CFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) happy_meal_init(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static void unmap_partial_tx_skb(struct happy_meal *hp, u32 first_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) u32 first_len, u32 first_entry, u32 entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) dma_unmap_single(hp->dma_dev, first_mapping, first_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) first_entry = NEXT_TX(first_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) while (first_entry != entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct happy_meal_txd *this = &txbase[first_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) u32 addr, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) addr = hme_read_desc32(hp, &this->tx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) len = hme_read_desc32(hp, &this->tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) len &= TXFLAG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) dma_unmap_page(hp->dma_dev, addr, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static netdev_tx_t happy_meal_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) int entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) u32 tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) tx_flags = TXFLAG_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) const u32 csum_start_off = skb_checksum_start_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) entry = hp->tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) SXD(("SX<l[%d]e[%d]>", len, entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) hp->tx_skbs[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) if (skb_shinfo(skb)->nr_frags == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) u32 mapping, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) if (unlikely(dma_mapping_error(hp->dma_dev, mapping)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) goto out_dma_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) (tx_flags | (len & TXFLAG_SIZE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) entry = NEXT_TX(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) u32 first_len, first_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) int frag, first_entry = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* We must give this initial chunk to the device last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * Otherwise we could race with the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) first_len = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (unlikely(dma_mapping_error(hp->dma_dev, first_mapping)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) goto out_dma_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) entry = NEXT_TX(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) u32 len, mapping, this_txflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) len = skb_frag_size(this_frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) mapping = skb_frag_dma_map(hp->dma_dev, this_frag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) 0, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) unmap_partial_tx_skb(hp, first_mapping, first_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) first_entry, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) goto out_dma_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) this_txflags = tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (frag == skb_shinfo(skb)->nr_frags - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) this_txflags |= TXFLAG_EOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) (this_txflags | (len & TXFLAG_SIZE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) entry = NEXT_TX(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) first_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) hp->tx_new = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* Get it going. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) out_dma_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) hp->tx_skbs[hp->tx_new] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) happy_meal_get_counters(hp, hp->bigmacregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static void happy_meal_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) void __iomem *bregs = hp->bigmacregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) } else if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) hme_write32(hp, bregs + BMAC_RXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) u16 hash_table[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) memset(hash_table, 0, sizeof(hash_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) crc = ether_crc_le(6, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) crc >>= 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) hash_table[crc >> 4] |= 1 << (crc & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* Ethtool support... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static int hme_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) u32 supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) supported =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /* XXX hardcoded stuff for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) cmd->base.port = PORT_TP; /* XXX no MII support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) cmd->base.phy_address = 0; /* XXX fixed PHYAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /* Record PHY settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (hp->sw_bmcr & BMCR_ANENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) cmd->base.autoneg = AUTONEG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) speed = ((hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) SPEED_100 : SPEED_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) cmd->base.duplex =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) (hp->sw_lpa & (LPA_100FULL)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) cmd->base.duplex =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) (hp->sw_lpa & (LPA_10FULL)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) cmd->base.autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) speed = (hp->sw_bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) cmd->base.duplex =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) (hp->sw_bmcr & BMCR_FULLDPLX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) cmd->base.speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static int hme_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* Verify the settings we care about. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (cmd->base.autoneg != AUTONEG_ENABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) cmd->base.autoneg != AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (cmd->base.autoneg == AUTONEG_DISABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ((cmd->base.speed != SPEED_100 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) cmd->base.speed != SPEED_10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) (cmd->base.duplex != DUPLEX_HALF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) cmd->base.duplex != DUPLEX_FULL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* Ok, do it to it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) del_timer(&hp->happy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) strlcpy(info->driver, "sunhme", sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) strlcpy(info->version, "2.02", sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (hp->happy_flags & HFLAG_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) struct pci_dev *pdev = hp->happy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) strlcpy(info->bus_info, pci_name(pdev), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) const struct linux_prom_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) struct platform_device *op = hp->happy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) regs = of_get_property(op->dev.of_node, "regs", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) if (regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) snprintf(info->bus_info, sizeof(info->bus_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) "SBUS:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) regs->which_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static u32 hme_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) struct happy_meal *hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return hp->sw_bmsr & BMSR_LSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const struct ethtool_ops hme_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .get_drvinfo = hme_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .get_link = hme_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .get_link_ksettings = hme_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .set_link_ksettings = hme_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static int hme_version_printed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /* Given a happy meal sbus device, find it's quattro parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * If none exist, allocate and return a new one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * Return NULL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static struct quattro *quattro_sbus_find(struct platform_device *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) struct device *parent = child->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) struct quattro *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) op = to_platform_device(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) qp = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (qp != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) qp->happy_meals[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) qp->quattro_dev = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) qp->next = qfe_sbus_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) qfe_sbus_list = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) platform_set_drvdata(op, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) /* After all quattro cards have been probed, we call these functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) * to register the IRQ handlers for the cards that have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) * successfully probed and skip the cards that failed to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static int __init quattro_sbus_register_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) struct quattro *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) struct platform_device *op = qp->quattro_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) int err, qfe_slot, skip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (!qp->happy_meals[qfe_slot])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) err = request_irq(op->archdata.irqs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) quattro_sbus_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) IRQF_SHARED, "Quattro",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) printk(KERN_ERR "Quattro HME: IRQ registration "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) "error %d.\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) static void quattro_sbus_free_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) struct quattro *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) struct platform_device *op = qp->quattro_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) int qfe_slot, skip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (!qp->happy_meals[qfe_slot])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) free_irq(op->archdata.irqs[0], qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #endif /* CONFIG_SBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static struct quattro *quattro_pci_find(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct pci_dev *bdev = pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) struct quattro *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (!bdev) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) struct pci_dev *qpdev = qp->quattro_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (qpdev == bdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (qp != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) qp->happy_meals[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) qp->quattro_dev = bdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) qp->next = qfe_pci_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) qfe_pci_list = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /* No range tricks necessary on PCI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) qp->nranges = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static const struct net_device_ops hme_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .ndo_open = happy_meal_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .ndo_stop = happy_meal_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .ndo_start_xmit = happy_meal_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .ndo_tx_timeout = happy_meal_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .ndo_get_stats = happy_meal_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .ndo_set_rx_mode = happy_meal_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static int happy_meal_sbus_probe_one(struct platform_device *op, int is_qfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) struct device_node *dp = op->dev.of_node, *sbus_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) struct quattro *qp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) struct happy_meal *hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) int i, qfe_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) sbus_dp = op->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) /* We can match PCI devices too, do not accept those here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (!of_node_name_eq(sbus_dp, "sbus") && !of_node_name_eq(sbus_dp, "sbi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (is_qfe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) qp = quattro_sbus_find(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (qp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (qp->happy_meals[qfe_slot] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if (qfe_slot == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) dev = alloc_etherdev(sizeof(struct happy_meal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) SET_NETDEV_DEV(dev, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (hme_version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) printk(KERN_INFO "%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* If user did not specify a MAC address specifically, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) * the Quattro local-mac-address property...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) if (macaddr[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (i < 6) { /* a mac address was given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) dev->dev_addr[i] = macaddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) macaddr[5]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) const unsigned char *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) addr = of_get_property(dp, "local-mac-address", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (qfe_slot != -1 && addr && len == ETH_ALEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) memcpy(dev->dev_addr, addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) hp->happy_dev = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) hp->dma_dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) spin_lock_init(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (qp != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) hp->qfe_parent = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) hp->qfe_ent = qfe_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) qp->happy_meals[qfe_slot] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) hp->gregs = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) GREG_REG_SIZE, "HME Global Regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (!hp->gregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) printk(KERN_ERR "happymeal: Cannot map global registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) goto err_out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) hp->etxregs = of_ioremap(&op->resource[1], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) ETX_REG_SIZE, "HME TX Regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (!hp->etxregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) hp->erxregs = of_ioremap(&op->resource[2], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) ERX_REG_SIZE, "HME RX Regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (!hp->erxregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) hp->bigmacregs = of_ioremap(&op->resource[3], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) BMAC_REG_SIZE, "HME BIGMAC Regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (!hp->bigmacregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) hp->tcvregs = of_ioremap(&op->resource[4], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) TCVR_REG_SIZE, "HME Tranceiver Regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (!hp->tcvregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (hp->hm_revision == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) hp->hm_revision = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) /* Now enable the feature flags we can. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) hp->happy_flags = HFLAG_20_21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) else if (hp->hm_revision != 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) hp->happy_flags = HFLAG_NOT_A0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (qp != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) hp->happy_flags |= HFLAG_QUATTRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) /* Get the supported DVMA burst sizes from our Happy SBUS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) hp->happy_bursts = of_getintprop_default(sbus_dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) "burst-sizes", 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) hp->happy_block = dma_alloc_coherent(hp->dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) &hp->hblock_dvma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (!hp->happy_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* Force check of the link first time we are brought up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) hp->linkcheck = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* Force timer state to 'asleep' with count of zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) hp->timer_state = asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) timer_setup(&hp->happy_timer, happy_meal_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) hp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) dev->netdev_ops = &hme_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) dev->watchdog_timeo = 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) dev->ethtool_ops = &hme_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* Happy Meal can do it all... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) dev->features |= dev->hw_features | NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) hp->irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) /* Hook up SBUS register/descriptor accessors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) hp->read_desc32 = sbus_hme_read_desc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) hp->write_txd = sbus_hme_write_txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) hp->write_rxd = sbus_hme_write_rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) hp->read32 = sbus_hme_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) hp->write32 = sbus_hme_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) /* Grrr, Happy Meal comes up by default not advertising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) * full duplex 100baseT capabilities, fix this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) happy_meal_set_initial_advertisement(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) err = register_netdev(hp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) printk(KERN_ERR "happymeal: Cannot register net device, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) "aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) goto err_out_free_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) platform_set_drvdata(op, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) if (qfe_slot != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) dev->name, qfe_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) printk("%pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) err_out_free_coherent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) dma_free_coherent(hp->dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) hp->happy_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) hp->hblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) if (hp->gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) if (hp->etxregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) if (hp->erxregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (hp->bigmacregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) if (hp->tcvregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) qp->happy_meals[qfe_slot] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) err_out_free_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) #ifndef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static int is_quattro_p(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) struct pci_dev *busdev = pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) struct pci_dev *this_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) int n_hmes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) if (busdev == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) busdev->vendor != PCI_VENDOR_ID_DEC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) busdev->device != PCI_DEVICE_ID_DEC_21153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) n_hmes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) list_for_each_entry(this_pdev, &pdev->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) n_hmes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) if (n_hmes != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /* Fetch MAC address from vital product data of PCI ROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) int this_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) for (this_offset = 0x20; this_offset < len; this_offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) void __iomem *p = rom_base + this_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) if (readb(p + 0) != 0x90 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) readb(p + 1) != 0x00 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) readb(p + 2) != 0x09 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) readb(p + 3) != 0x4e ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) readb(p + 4) != 0x41 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) readb(p + 5) != 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) this_offset += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) p += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) dev_addr[i] = readb(p + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) index--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) void __iomem *p = pci_map_rom(pdev, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (is_quattro_p(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) index = PCI_SLOT(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) found = readb(p) == 0x55 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) readb(p + 1) == 0xaa &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) pci_unmap_rom(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) if (found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) /* Sun MAC prefix then 3 random bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) dev_addr[0] = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) dev_addr[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) dev_addr[2] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) get_random_bytes(&dev_addr[3], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #endif /* !(CONFIG_SPARC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static int happy_meal_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) struct quattro *qp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) struct happy_meal *hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) void __iomem *hpreg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) unsigned long hpreg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) int i, qfe_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) char prom_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) /* Now make sure pci_dev cookie is there. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) dp = pci_device_to_OF_node(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) snprintf(prom_name, sizeof(prom_name), "%pOFn", dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (is_quattro_p(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) strcpy(prom_name, "SUNW,qfe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) strcpy(prom_name, "SUNW,hme");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) if (pci_enable_device(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) qp = quattro_pci_find(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) if (qp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) if (qp->happy_meals[qfe_slot] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (qfe_slot == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) dev = alloc_etherdev(sizeof(struct happy_meal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) if (hme_version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) printk(KERN_INFO "%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) hp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) hp->happy_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) hp->dma_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) spin_lock_init(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (qp != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) hp->qfe_parent = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) hp->qfe_ent = qfe_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) qp->happy_meals[qfe_slot] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) hpreg_res = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) goto err_out_clear_quattro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) if (pci_request_regions(pdev, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) "aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) goto err_out_clear_quattro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) goto err_out_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) if (macaddr[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) if (i < 6) { /* a mac address was given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) dev->dev_addr[i] = macaddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) macaddr[5]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) const unsigned char *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (qfe_slot != -1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) (addr = of_get_property(dp, "local-mac-address", &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) != NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) len == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) memcpy(dev->dev_addr, addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) /* Layout registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) hp->gregs = (hpreg_base + 0x0000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) hp->etxregs = (hpreg_base + 0x2000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) hp->erxregs = (hpreg_base + 0x4000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) hp->bigmacregs = (hpreg_base + 0x6000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) hp->tcvregs = (hpreg_base + 0x7000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) if (hp->hm_revision == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) /* works with this on non-sparc hosts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) hp->hm_revision = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) /* Now enable the feature flags we can. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) hp->happy_flags = HFLAG_20_21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) hp->happy_flags = HFLAG_NOT_A0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (qp != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) hp->happy_flags |= HFLAG_QUATTRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* And of course, indicate this is PCI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) hp->happy_flags |= HFLAG_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /* Assume PCI happy meals can handle all burst sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) hp->happy_bursts = DMA_BURSTBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) hp->happy_block = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) &hp->hblock_dvma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (!hp->happy_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) hp->linkcheck = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) hp->timer_state = asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) hp->timer_ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) timer_setup(&hp->happy_timer, happy_meal_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) hp->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) hp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) dev->netdev_ops = &hme_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) dev->watchdog_timeo = 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) dev->ethtool_ops = &hme_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* Happy Meal can do it all... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) dev->features |= dev->hw_features | NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /* Hook up PCI register/descriptor accessors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) hp->read_desc32 = pci_hme_read_desc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) hp->write_txd = pci_hme_write_txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) hp->write_rxd = pci_hme_write_rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) hp->read32 = pci_hme_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) hp->write32 = pci_hme_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) /* Grrr, Happy Meal comes up by default not advertising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) * full duplex 100baseT capabilities, fix this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) spin_lock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) happy_meal_set_initial_advertisement(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) spin_unlock_irq(&hp->happy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) err = register_netdev(hp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) "aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) goto err_out_free_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) pci_set_drvdata(pdev, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) if (!qfe_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) struct pci_dev *qpdev = qp->quattro_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) prom_name[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (!strncmp(dev->name, "eth", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) int i = simple_strtoul(dev->name + 3, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) sprintf(prom_name, "-%d", i + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) qpdev->device == PCI_DEVICE_ID_DEC_21153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) printk("DEC 21153 PCI Bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) printk("unknown bridge %04x.%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) qpdev->vendor, qpdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (qfe_slot != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) dev->name, qfe_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) printk("%pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) err_out_free_coherent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) dma_free_coherent(hp->dma_dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) hp->happy_block, hp->hblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) iounmap(hp->gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) err_out_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) err_out_clear_quattro:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) if (qp != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) qp->happy_meals[qfe_slot] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) static void happy_meal_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) struct happy_meal *hp = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) struct net_device *net_dev = hp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) unregister_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) dma_free_coherent(hp->dma_dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) hp->happy_block, hp->hblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) iounmap(hp->gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) pci_release_regions(hp->happy_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) free_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static const struct pci_device_id happymeal_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) { } /* Terminating entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) static struct pci_driver hme_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .name = "hme",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .id_table = happymeal_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .probe = happy_meal_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .remove = happy_meal_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) static int __init happy_meal_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) return pci_register_driver(&hme_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) static void happy_meal_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) pci_unregister_driver(&hme_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) while (qfe_pci_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) struct quattro *qfe = qfe_pci_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) struct quattro *next = qfe->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) kfree(qfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) qfe_pci_list = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) static const struct of_device_id hme_sbus_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static int hme_sbus_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) const char *model = of_get_property(dp, "model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) int is_qfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) match = of_match_device(hme_sbus_match, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) is_qfe = (match->data != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) is_qfe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) return happy_meal_sbus_probe_one(op, is_qfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) static int hme_sbus_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) struct happy_meal *hp = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) struct net_device *net_dev = hp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) unregister_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) /* XXX qfe parent interrupt... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) dma_free_coherent(hp->dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) hp->happy_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) hp->hblock_dvma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) free_netdev(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static const struct of_device_id hme_sbus_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) .name = "SUNW,hme",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) .name = "SUNW,qfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .data = (void *) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .name = "qfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .data = (void *) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) MODULE_DEVICE_TABLE(of, hme_sbus_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static struct platform_driver hme_sbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .name = "hme",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .of_match_table = hme_sbus_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .probe = hme_sbus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .remove = hme_sbus_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) static int __init happy_meal_sbus_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) err = platform_driver_register(&hme_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) err = quattro_sbus_register_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) static void happy_meal_sbus_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) platform_driver_unregister(&hme_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) quattro_sbus_free_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) while (qfe_sbus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) struct quattro *qfe = qfe_sbus_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) struct quattro *next = qfe->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) kfree(qfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) qfe_sbus_list = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static int __init happy_meal_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) err = happy_meal_sbus_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) err = happy_meal_pci_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) happy_meal_sbus_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) static void __exit happy_meal_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) happy_meal_sbus_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) happy_meal_pci_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) module_init(happy_meal_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) module_exit(happy_meal_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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