^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sungem.h: Definitions for Sun GEM ethernet driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SUNGEM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SUNGEM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Global Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GREG_CFG 0x0004UL /* Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GREG_STAT 0x000CUL /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GREG_SWRST 0x1010UL /* Software Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Global SEB State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Global Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GREG_CFG_RONPAULBIT 0x00000800 /* Use mem read multiple for PCI read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * after infinite burst (Apple) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Global Interrupt Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Reading this register automatically clears bits 0 through 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This auto-clearing does not occur when the alias at GREG_STAT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * is read instead. The rest of the interrupt bits only clear when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * the secondary interrupt status register corresponding to that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * reading PCS_ISTAT).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GREG_STAT_TXNR_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GREG_STAT_NAPI (GREG_STAT_TXALL | GREG_STAT_TXINTME | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GREG_STAT_RXDONE | GREG_STAT_ABNORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Bits set in GREG_IMASK will prevent that interrupt type from being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * signalled to the cpu. GREG_IACK can be used to clear specific top-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Setting the bit will clear that interrupt, clear bits will have no effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * on GREG_STAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Global PCI Error Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * signalled to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Global BIF Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Global BIF Diagnostics Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Global Software Reset Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * This register is used to perform a global reset of the RX and TX portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * of the GEM asic. Setting the RX or TX reset bit will start the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * The driver _MUST_ poll these bits until they clear. One may not attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * to program any other part of GEM until the bits clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GREG_SWRST_CACHE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* TX DMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TXDMA_KICK 0x2000UL /* TX Kick Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TXDMA_CFG 0x2004UL /* TX Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TXDMA_FSZ 0x2118UL /* TX FIFO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* TX Kick Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This 13-bit register is programmed by the driver to hold the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * entry index which follows the last valid transmit descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* TX Completion Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * This 13-bit register is updated by GEM to hold to descriptor entry index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * which follows the last descriptor already processed by GEM. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * this value is mirrored in GREG_STAT which eliminates the need to even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * access this register in the driver during interrupt processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* TX Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * that was meant to be used with jumbo packets. It should be set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* TX Descriptor Base Low/High.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * These two registers store the 53 most significant bits of the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * of the TX descriptor table. The 11 least significant bits are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * zero. As a result, the TX descriptor table must be 2K aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * them later. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* WakeOnLan Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define WOL_MATCH0 0x3000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WOL_MATCH1 0x3004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WOL_MATCH2 0x3008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WOL_MCOUNT 0x300CUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define WOL_WAKECSR 0x3010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* WOL Match count register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WOL_MCOUNT_N 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WOL_WAKECSR_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WOL_WAKECSR_MII 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WOL_WAKECSR_SEEN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define WOL_WAKECSR_FILT_UCAST 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define WOL_WAKECSR_FILT_MCAST 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define WOL_WAKECSR_FILT_BCAST 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define WOL_WAKECSR_FILT_SEEN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Receive DMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RXDMA_CFG 0x4000UL /* RX Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RXDMA_KICK 0x4100UL /* RX Kick Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RXDMA_DONE 0x4104UL /* RX Completion Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RXDMA_FSZ 0x4120UL /* RX FIFO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* RX Configuration Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* RX Descriptor Base Low/High.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * These two registers store the 53 most significant bits of the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * of the RX descriptor table. The 11 least significant bits are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * zero. As a result, the RX descriptor table must be 2K aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* RX PAUSE Thresholds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * These values determine when XOFF and XON PAUSE frames are emitted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* RX Kick Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * This 13-bit register is written by the host CPU and holds the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * valid RX descriptor number plus one. This is, if 'N' is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * this register, it means that all RX descriptors up to but excluding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 'N' are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * The hardware requires that RX descriptors are posted in increments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * of 4. This means 'N' must be a multiple of four. For the best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * performance, the first new descriptor being posted should be (PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * cache line aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* RX Completion Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This 13-bit register is updated by GEM to indicate which RX descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * have already been used for receive frames. All descriptors up to but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * excluding the value in this register are ready to be processed. GEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * updates this register value after the RX FIFO empties completely into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * the RX descriptor's buffer, but before the RX_DONE bit is set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * interrupt status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* RX Blanking Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * many packets received since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * previous RX_DONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * many clocks (measured in 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * PCI clocks) were counted since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * the previous RX_DONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* RX FIFO Size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * This 11-bit read-only register indicates how large, in units of 64-bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * the RX FIFO is. The driver uses this to properly configure the RX PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * thresholds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * them later. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* MAC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MAC_STIME 0x604CUL /* SlotTime Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MAC_PASIZE 0x6058UL /* PA Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MAC_JAMSIZE 0x605CUL /* JamSize Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MAC_NCOLL 0x6100UL /* Normal Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MAC_LCOLL 0x610CUL /* Late Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MAC_DTIMER 0x6110UL /* Defer Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MAC_PATMPS 0x6114UL /* Peak Attempts Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MAC_RFCTR 0x6118UL /* Receive Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MAC_LERR 0x611CUL /* Length Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MAC_AERR 0x6120UL /* Alignment Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MAC_FCSERR 0x6124UL /* FCS Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MAC_SMACHINE 0x6134UL /* State Machine Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* TX MAC Software Reset Command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* RX MAC Software Reset Command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Send Pause Command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Send_Pause and flow-control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * handshakes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * to send a Pause Flow Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * frame onto the network.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* TX MAC Status Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* RX MAC Status Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* MAC Control Status Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MAC_CSTAT_PS 0x00000002 /* Paused State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * that interrupt type from being signalled to front end of GEM. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * the interrupt to actually get sent to the cpu, it is necessary to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* TX MAC Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * NOTE: The TX MAC Enable bit must be cleared and polled until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * zero before any other bits in this register are changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Also, enabling the Carrier Extension feature of GEM is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * a 3 step process 1) Set TX Carrier Extension 2) Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * RX Carrier Extension 3) Set Slot Time to 0x200. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * mode must be enabled when in half-duplex at 1Gbps, else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * it must be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MAC_TXCFG_NBO 0x00000040 /* No Backoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MAC_TXCFG_SD 0x00000080 /* Slow Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MAC_TXCFG_NFCS 0x00000100 /* No FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* RX MAC Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * NOTE: The RX MAC Enable bit must be cleared and polled until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * zero before any other bits in this register are changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Similar rules apply to the Hash Filter Enable bit when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * programming the hash table registers, and the Address Filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Enable bit when programming the address filter registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* MAC Control Config Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* XIF Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * NOTE: When leaving or entering loopback mode, a global hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * init of GEM should be performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* InterPacketGap0 Register. This 8-bit value is used as an extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * to the InterPacketGap1 Register. Specifically it contributes to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * timing of the RX-to-TX IPG. This value is ignored and presumed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * is cleared in the TX MAC Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * This value in this register in terms of media byte time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Recommended value: 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * portion of the Inter Packet Gap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * This value in this register in terms of media byte time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Recommended value: 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * portion of the Inter Packet Gap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * This value in this register in terms of media byte time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Recommended value: 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Slot Time Register. This 10-bit value specifies the slot time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * parameter in units of media byte time. It determines the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * span of the network.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Recommended value: 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Minimum Frame Size Register. This 10-bit register specifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * smallest sized frame the TXMAC will send onto the medium, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * RXMAC will receive from the medium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Recommended value: 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Maximum Frame and Burst Size Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * This register specifies two things. First it specifies the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * sized frame the TXMAC will send and the RXMAC will recognize as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * valid. Second, it specifies the maximum run length of a burst of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * packets sent in half-duplex gigabit modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Recommended value: 0x200005ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* PA Size Register. This 10-bit register specifies the number of preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * bytes which will be transmitted at the beginning of each frame. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * value of two or greater should be programmed here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Recommended value: 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Jam Size Register. This 4-bit register specifies the duration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * the jam in units of media byte time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Recommended value: 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Attempts Limit Register. This 8-bit register specifies the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * of attempts that the TXMAC will make to transmit a frame, before it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * resets its Attempts Counter. After reaching the Attempts Limit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * TXMAC may or may not drop the frame, as determined by the NGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Recommended value: 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* MAX Control Type Register. This 16-bit register specifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * "type" field of a MAC Control frame. The TXMAC uses this field to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * encapsulate the MAC Control frame for transmission, and the RXMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * uses it for decoding valid MAC Control frames received from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * network.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Recommended value: 0x8808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* MAC Address Registers. Each of these registers specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * ethernet MAC of the interface, 16-bits at a time. Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * 0 specifies bits [47:32], register 1 bits [31:16], and register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * 2 bits [15:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Registers 3 through and including 5 specify an alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * MAC address for the interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Registers 6 through and including 8 specify the MAC Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Address, which must be the reserved multicast address for MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Control frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Example: To program primary station address a:b:c:d:e:f into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * MAC_Address_2 = (a << 8) | b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * MAC_Address_1 = (c << 8) | d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * MAC_Address_0 = (e << 8) | f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Address Filter Registers. Registers 0 through 2 specify bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * fields [47:32] through [15:0], respectively, of the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * nibble mask for Address Filter Registers 2 and 1. The Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Filter 0 Mask Register denotes the 16-bit mask for the Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Filter Register 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Hash Table Registers. Registers 0 through 15 specify bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * [255:240] through [15:0], respectively, of the hash table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Statistics Registers. All of these registers are 16-bits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * track occurrences of a specific event. GEM can be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * to interrupt the host cpu when any of these counters overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * They should all be explicitly initialized to zero when the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * is brought up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Random Number Seed Register. This 10-bit value is used as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * recommended to program this register to the 10 LSB of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * interfaces MAC address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Pause Timer, read-only. This 16-bit timer is used to time the pause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * interval as indicated by a received pause flow control frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * A non-zero value in this timer indicates that the MAC is currently in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * the paused state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* MIF Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define MIF_CFG 0x6210UL /* MIF Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MIF_MASK 0x6214UL /* MIF Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MIF_STATUS 0x6218UL /* MIF Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * MDC clock waveform on the MII Management Interface when the MIF is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * this register will create a rising edge on the MDC, while writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * a '0' after a '1' will create a falling edge. For every bit that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * is transferred on the management interface, both edges have to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* MIF Bit-Bang Data. This 1-bit register is used to generate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * outgoing data (MDO) on the MII Management Interface when the MIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * is programmed in the "Bit-Bang" mode. The daa will be steered to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * appropriate MDIO based on the state of the PHY_Select bit in the MIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * ('1') or disable ('0') the I-directional driver on the MII when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * when data bits are transferred from the MIF to the transceiver, and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * should be disabled when the interface is idle or when data bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * transferred from the transceiver to the MIF (data portion of a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * instruction). Only one MDIO will be enabled at a given time, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * on the state of the PHY_Select bit in the MIF Configuration Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* MIF Configuration Register. This 15-bit register controls the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * of the MIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* MIF Frame/Output Register. This 32-bit register allows the host to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * communicate with a transceiver in frame mode (as opposed to big-bang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * mode). Writes by the host specify an instrution. After being issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * the host must poll this register for completion. Also, after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * completion this register holds the data returned by the transceiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * if applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MIF_FRAME_ST 0xc0000000 /* STart of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define MIF_FRAME_OP 0x30000000 /* OPcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* MIF Status Register. This register reports status when the MIF is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * operating in the poll mode. The poll status field is auto-clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * on read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* MIF Mask Register. This 16-bit register is used when in poll mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * to say which bits of the polled register will cause an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * when changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* PCS/Serialink Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define PCS_CFG 0x9010UL /* PCS Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define PCS_DMODE 0x9050UL /* Datapath Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define PCS_SCTRL 0x9054UL /* Serialink Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define PCS_SOS 0x9058UL /* Shared Output Select Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define PCS_SSTATE 0x905CUL /* Serialink State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* PCD MII Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * input side of Serialink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* PCS MII Status Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* PCS MII Advertisement Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define PCS_MIIADV_RF 0x00003000 /* Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* PCS MII Link Partner Ability Register. This register is equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * to the Link Partnet Ability Register of the standard MII register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * It's layout corresponds to the PCS MII Advertisement Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* PCS Configuration Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * PCS MII advertisement reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define PCS_CFG_SDO 0x00000002 /* Signal detect override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define PCS_CFG_SDL 0x00000004 /* Signal detect active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define PCS_CFG_JS 0x00000018 /* Jitter-study:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * 0 = normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * 1 = high-frequency test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * 2 = low-frequency test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * 3 = reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* PCS Interrupt Status Register. This register is self-clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Datapath Mode Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Serialink Control Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * NOTE: When in SERDES mode, the loopback bit has inverse logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Shared Output Select Register. For test and debug, allows multiplexing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * test outputs into the PROM address pins. Set to zero for normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define PCS_SOS_PADDR 0x00000003 /* PROM Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* PROM Image Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define PROM_START 0x100000UL /* Expansion ROM run time access*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define PROM_SIZE 0x0fffffUL /* Size of ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define PROM_END 0x200000UL /* End of ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* MII definitions missing from mii.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define LPA_PAUSE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* More PHY registers (specific to Broadcom models) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* MII BCM5201 MULTIPHY interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MII_BCM5201_INTERRUPT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define MII_BCM5201_AUXMODE2 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define MII_BCM5201_MULTIPHY 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* MII BCM5201 MULTIPHY register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* MII BCM5400 1000-BASET Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MII_BCM5400_GB_CONTROL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* MII BCM5400 AUXCONTROL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MII_BCM5400_AUXCONTROL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* MII BCM5400 AUXSTATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define MII_BCM5400_AUXSTATUS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* When it can, GEM internally caches 4 aligned TX descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * at a time, so that it can use full cacheline DMA reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Note that unlike HME, there is no ownership bit in the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * control word. The same functionality is obtained via the TX-Kick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * and TX-Complete registers. As a result, GEM need not write back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * updated values to the TX descriptor ring, it only performs reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Since TX descriptors are never modified by GEM, the driver can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * use the buffer DMA address as a place to keep track of allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * DMA mappings for a transmitted packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct gem_txd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __le64 control_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __le64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* GEM requires that RX descriptors are provided four at a time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * aligned. Also, the RX ring may not wrap around. This means that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * there will be at least 4 unused descriptor entries in the middle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * of the RX ring at all times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * Similar to HME, GEM assumes that it can write garbage bytes before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * the beginning of the buffer and right after the end in order to DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * whole cachelines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Unlike for TX, GEM does update the status word in the RX descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * when packets arrive. Therefore an ownership bit does exist in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * RX descriptors. It is advisory, GEM clears it but does not check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * it in any way. So when buffers are posted to the RX ring (via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * RX Kick register) by the driver it must make sure the buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * truly ready and that the ownership bits are set properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Even though GEM modifies the RX descriptors, it guarantees that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * buffer DMA address field will stay the same when it performs these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * updates. Therefore it can be used to keep track of DMA mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * by the host driver just as in the TX descriptor case above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct gem_rxd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) __le64 status_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) __le64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define RXDCTRL_FRESH(gp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RXDCTRL_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define TX_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define RX_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #if TX_RING_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #elif TX_RING_SIZE == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #elif TX_RING_SIZE == 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #elif TX_RING_SIZE == 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #elif TX_RING_SIZE == 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #elif TX_RING_SIZE == 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #elif TX_RING_SIZE == 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #elif TX_RING_SIZE == 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #elif TX_RING_SIZE == 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #error TX_RING_SIZE value is illegal...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #if RX_RING_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #elif RX_RING_SIZE == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #elif RX_RING_SIZE == 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #elif RX_RING_SIZE == 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #elif RX_RING_SIZE == 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #elif RX_RING_SIZE == 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #elif RX_RING_SIZE == 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #elif RX_RING_SIZE == 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #elif RX_RING_SIZE == 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #error RX_RING_SIZE is illegal...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define TX_BUFFS_AVAIL(GP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) (((GP)->tx_old <= (GP)->tx_new) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) (GP)->tx_old - (GP)->tx_new - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define RX_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define RX_COPY_THRESHOLD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #if TX_RING_SIZE < 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define INIT_BLOCK_TX_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #if RX_RING_SIZE < 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define INIT_BLOCK_RX_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct gem_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) enum gem_phy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) phy_mii_mdio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) phy_mii_mdio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) phy_serialink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) phy_serdes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) enum link_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) link_down = 0, /* No link, will retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) link_aneg, /* Autoneg in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) link_force_try, /* Try Forced link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) link_force_ret, /* Forced mode worked, retrying autoneg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) link_force_ok, /* Stay in forced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) link_up /* Link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct gem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int rx_new, rx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int tx_new, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned int has_wol : 1; /* chip supports wake-on-lan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int asleep_wol : 1; /* was asleep with WOL enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int cell_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int tx_fifo_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int rx_fifo_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int rx_pause_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int rx_pause_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int rx_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u64 pause_entered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u16 pause_last_time_recvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 mac_rx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 swrst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int want_autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int last_forced_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) enum link_state lstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct timer_list link_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int timer_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int wake_on_lan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) volatile int reset_task_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) enum gem_phy_type phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct mii_phy phy_mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int mii_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct gem_init_block *init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct sk_buff *rx_skbs[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct sk_buff *tx_skbs[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dma_addr_t gblock_dvma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) gp->phy_mii.def && gp->phy_mii.def->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #endif /* _SUNGEM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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