^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: sunbmac.h,v 1.7 2000/07/11 22:35:22 davem Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SUNBMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SUNBMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* QEC global registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GLOB_CTRL 0x00UL /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GLOB_STAT 0x04UL /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GLOB_PSIZE 0x08UL /* Packet Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GLOB_RSIZE 0x10UL /* Receive partition size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GLOB_TSIZE 0x14UL /* Transmit partition size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GLOB_REG_SIZE 0x18UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* QEC BigMAC channel registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CREG_CTRL 0x00UL /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CREG_STAT 0x04UL /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CREG_CCNT 0x30UL /* Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CREG_REG_SIZE 0x34UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CREG_STAT_BERROR 0x80000000 /* BigMAC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CREG_STAT_RXSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* BIGMAC core registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BMAC_XIFCFG 0x000UL /* XIF config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 0x004-->0x0fc, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BMAC_STATUS 0x100UL /* Status register, clear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BMAC_IMASK 0x104UL /* Interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 0x108-->0x204, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BMAC_STIME 0x21cUL /* Transmit slot time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BMAC_TXDELIM 0x228UL /* Transmit delimiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BMAC_JSIZE 0x22cUL /* Toe jam... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BMAC_TXPMAX 0x230UL /* Transmit max pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BMAC_TXPMIN 0x234UL /* Transmit min pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BMAC_RSEED 0x250UL /* Transmit random number seed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* 0x258-->0x304, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BMAC_RXCFG 0x30cUL /* Receiver config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BMAC_RXPMAX 0x310UL /* Receive max pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BMAC_RXPMIN 0x314UL /* Receive min pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 0x33c, reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BMAC_AFMASK 0x35cUL /* Address filter mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BMAC_REG_SIZE 0x360UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* BigMac XIF config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BIGMAC_XCFG_RESV 0x00000002 /* Reserved, write always as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BIGMAC_XCFG_SMODE 0x00000008 /* Enable serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* BigMAC status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BIGMAC_STAT_GOTFRAME 0x00000001 /* Received a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BIGMAC_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BIGMAC_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BIGMAC_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BIGMAC_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BIGMAC_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* BigMAC interrupt mask register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BIGMAC_IMASK_GOTFRAME 0x00000001 /* Received a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BIGMAC_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BIGMAC_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* BigMac transmit config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BIGMAC_TXCFG_FIFO 0x00000010 /* Default tx fthresh... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* BigMac receive config register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BIGMAC_RXCFG_FIFO 0x0000000e /* Default rx fthresh... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* The BigMAC PHY transceiver. Not nearly as sophisticated as the happy meal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * one. But it does have the "bit banger", oh baby.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TCVR_TPAL 0x00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TCVR_MPAL 0x04UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TCVR_REG_SIZE 0x08UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Frame commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FRAME_WRITE 0x50020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define FRAME_READ 0x60020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Tranceiver registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TCVR_PAL_MSENSE 0x00000004 /* Media sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TCVR_PAL_LTENABLE 0x00000008 /* Link test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TCVR_PAL_LTSTATUS 0x00000010 /* Link test status (P1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Management PAL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MGMT_PAL_DCLOCK 0x00000001 /* Data clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MGMT_PAL_OENAB 0x00000002 /* Output enabler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MGMT_PAL_MDIO 0x00000004 /* MDIO Data/attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MGMT_PAL_TIMEO 0x00000008 /* Transmit enable timeout error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Here are some PHY addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Ring descriptors and such, same as Quad Ethernet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct be_rxd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 rx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RXD_OWN 0x80000000 /* Ownership. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RXD_UPDATE 0x10000000 /* Being Updated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RXD_LENGTH 0x000007ff /* Packet Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct be_txd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 tx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TXD_OWN 0x80000000 /* Ownership. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TXD_SOP 0x40000000 /* Start Of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TXD_EOP 0x20000000 /* End Of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TXD_UPDATE 0x10000000 /* Being Updated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TXD_LENGTH 0x000007ff /* Packet Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TX_RING_MAXSIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RX_RING_MAXSIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TX_BUFFS_AVAIL(bp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (((bp)->tx_old <= (bp)->tx_new) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (bp)->tx_old - (bp)->tx_new - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RX_COPY_THRESHOLD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct bmac_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct be_rxd be_rxd[RX_RING_MAXSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct be_txd be_txd[TX_RING_MAXSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define bib_offset(mem, elem) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Now software state stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) enum bigmac_transceiver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) external = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) internal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) none = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Timer state engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum bigmac_timer_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ltrywait = 1, /* Forcing try of all modes, from fastest to slowest. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) asleep = 2, /* Timer inactive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct bigmac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __iomem *gregs; /* QEC Global Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *creg; /* QEC BigMAC Channel Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void __iomem *bregs; /* BigMAC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *tregs; /* BigMAC Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct bmac_init_block *bmac_block; /* RX and TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dma_addr_t bblock_dvma; /* RX and TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct sk_buff *rx_skbs[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct sk_buff *tx_skbs[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int rx_new, tx_new, rx_old, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int board_rev; /* BigMAC board revision. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum bigmac_transceiver tcvr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int bigmac_bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned short sw_bmsr; /* SW copy of PHY BMSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned short sw_bmcr; /* SW copy of PHY BMCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct timer_list bigmac_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum bigmac_timer_state timer_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int timer_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct platform_device *qec_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct platform_device *bigmac_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* We use this to acquire receive skb's that we can DMA directly into. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ALIGNED_RX_SKB_ADDR(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) skb = alloc_skb(length + 64, gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if(skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int offset = ALIGNED_RX_SKB_ADDR(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if(offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) skb_reserve(skb, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif /* !(_SUNBMAC_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags