^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* niu.h: Definitions for Neptune ethernet driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _NIU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _NIU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PIO 0x000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FZC_PIO 0x080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FZC_MAC 0x180000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FZC_IPP 0x280000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FFLP 0x300000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FZC_FFLP 0x380000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PIO_VADDR 0x400000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ZCP 0x500000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FZC_ZCP 0x580000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMC 0x600000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FZC_DMC 0x680000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TXC 0x700000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FZC_TXC 0x780000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PIO_LDSV 0x800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIO_PIO_LDGIM 0x900000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIO_IMASK0 0xa00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PIO_IMASK1 0xb00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FZC_PROM 0xc80000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FZC_PIM 0xd80000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LDSV0(LDG) (PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LDSV1(LDG) (PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LDSV2(LDG) (PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LDG_IMGMT(LDG) (PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LDG_IMGMT_ARM 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LDG_IMGMT_TIMER 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LD_IM0(IDX) (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LD_IM0_MASK 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LD_IM1(IDX) (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LD_IM1_MASK 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LDG_TIMER_RES (FZC_PIO + 0x00008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LDG_TIMER_RES_VAL 0x00000000000fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DIRTY_TID_CTL (FZC_PIO + 0x00010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DIRTY_TID_CTL_NPTHRED 0x00000000003f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DIRTY_TID_CTL_RDTHRED 0x00000000000003f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DIRTY_TID_CTL_DTIDCLR 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DIRTY_TID_CTL_DTIDENAB 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DIRTY_TID_STAT (FZC_PIO + 0x00018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DIRTY_TID_STAT_NPWSTAT 0x0000000000003f00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DIRTY_TID_STAT_RDSTAT 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RST_CTL (FZC_PIO + 0x00038UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RST_CTL_MAC_RST3 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RST_CTL_MAC_RST2 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RST_CTL_MAC_RST1 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RST_CTL_MAC_RST0 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RST_CTL_ACK_TO_EN 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RST_CTL_ACK_TO_VAL 0x00000000000007feULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SMX_CFIG_DAT (FZC_PIO + 0x00040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SMX_CFIG_DAT_RAS_DET 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SMX_CFIG_DAT_RAS_INJ 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMX_CFIG_DAT_XACT_TO 0x000000000fffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SMX_INT_STAT (FZC_PIO + 0x00048UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SMX_INT_STAT_STAT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMX_CTL (FZC_PIO + 0x00050UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SMX_CTL_CTL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SMX_DBG_VEC (FZC_PIO + 0x00058UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SMX_DBG_VEC_VEC 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PIO_DBG_SEL (FZC_PIO + 0x00060UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PIO_DBG_SEL_SEL 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PIO_TRAIN_VEC (FZC_PIO + 0x00068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PIO_TRAIN_VEC_VEC 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PIO_ARB_CTL (FZC_PIO + 0x00070UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PIO_ARB_CTL_CTL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PIO_ARB_DBG_VEC (FZC_PIO + 0x00078UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PIO_ARB_DBG_VEC_VEC 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SYS_ERR_MASK (FZC_PIO + 0x00090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SYS_ERR_MASK_META2 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SYS_ERR_MASK_META1 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SYS_ERR_MASK_PEU 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SYS_ERR_MASK_TXC 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SYS_ERR_MASK_RDMC 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SYS_ERR_MASK_TDMC 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SYS_ERR_MASK_ZCP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SYS_ERR_MASK_FFLP 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SYS_ERR_MASK_IPP 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SYS_ERR_MASK_MAC 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SYS_ERR_MASK_SMX 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SYS_ERR_STAT (FZC_PIO + 0x00098UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SYS_ERR_STAT_META2 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SYS_ERR_STAT_META1 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SYS_ERR_STAT_PEU 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SYS_ERR_STAT_TXC 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SYS_ERR_STAT_RDMC 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SYS_ERR_STAT_TDMC 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SYS_ERR_STAT_ZCP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SYS_ERR_STAT_FFLP 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SYS_ERR_STAT_IPP 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SYS_ERR_STAT_MAC 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SYS_ERR_STAT_SMX 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SID(LDG) (FZC_PIO + 0x10200UL + (LDG) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SID_FUNC 0x0000000000000060ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SID_FUNC_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SID_VECTOR 0x000000000000001fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SID_VECTOR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LDG_NUM(LDN) (FZC_PIO + 0x20000UL + (LDN) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XMAC_PORT0_OFF (FZC_MAC + 0x000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XMAC_PORT1_OFF (FZC_MAC + 0x006000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BMAC_PORT2_OFF (FZC_MAC + 0x00c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BMAC_PORT3_OFF (FZC_MAC + 0x010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* XMAC registers, offset from np->mac_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XTXMAC_SW_RST 0x00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XTXMAC_SW_RST_REG_RS 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XTXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XRXMAC_SW_RST 0x00008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XRXMAC_SW_RST_REG_RS 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XRXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define XTXMAC_STATUS 0x00020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define XTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XTXMAC_STATUS_TXFIFO_XFR_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XTXMAC_STATUS_TXMAC_OFLOW 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XTXMAC_STATUS_MAX_PSIZE_ERR 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XTXMAC_STATUS_TXMAC_UFLOW 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XTXMAC_STATUS_FRAME_XMITED 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define XRXMAC_STATUS 0x00028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define XRXMAC_STATUS_RXHIST7_CNT_EXP 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define XRXMAC_STATUS_LCL_FLT_STATUS 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define XRXMAC_STATUS_RFLT_DET 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XRXMAC_STATUS_LFLT_CNT_EXP 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define XRXMAC_STATUS_PHY_MDINT 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define XRXMAC_STATUS_ALIGNERR_CNT_EXP 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define XRXMAC_STATUS_RXFRAG_CNT_EXP 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define XRXMAC_STATUS_RXMULTF_CNT_EXP 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define XRXMAC_STATUS_RXBCAST_CNT_EXP 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XRXMAC_STATUS_RXHIST6_CNT_EXP 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define XRXMAC_STATUS_RXHIST5_CNT_EXP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define XRXMAC_STATUS_RXHIST4_CNT_EXP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XRXMAC_STATUS_RXHIST3_CNT_EXP 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define XRXMAC_STATUS_RXHIST2_CNT_EXP 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define XRXMAC_STATUS_RXHIST1_CNT_EXP 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define XRXMAC_STATUS_RXOCTET_CNT_EXP 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define XRXMAC_STATUS_CVIOLERR_CNT_EXP 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define XRXMAC_STATUS_LENERR_CNT_EXP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define XRXMAC_STATUS_CRCERR_CNT_EXP 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define XRXMAC_STATUS_RXUFLOW 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define XRXMAC_STATUS_RXOFLOW 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define XRXMAC_STATUS_FRAME_RCVD 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define XMAC_FC_STAT 0x00030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define XMAC_FC_STAT_RX_RCV_PAUSE_TIME 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define XMAC_FC_STAT_TX_MAC_NPAUSE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define XMAC_FC_STAT_TX_MAC_PAUSE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define XMAC_FC_STAT_RX_MAC_RPAUSE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define XTXMAC_STAT_MSK 0x00040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define XTXMAC_STAT_MSK_FRAME_CNT_EXP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define XTXMAC_STAT_MSK_BYTE_CNT_EXP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define XTXMAC_STAT_MSK_TXFIFO_XFR_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define XTXMAC_STAT_MSK_TXMAC_OFLOW 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define XTXMAC_STAT_MSK_MAX_PSIZE_ERR 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define XTXMAC_STAT_MSK_TXMAC_UFLOW 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define XTXMAC_STAT_MSK_FRAME_XMITED 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define XRXMAC_STAT_MSK 0x00048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XRXMAC_STAT_MSK_RFLT_DET 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XRXMAC_STAT_MSK_LFLT_CNT_EXP 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XRXMAC_STAT_MSK_PHY_MDINT 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XRXMAC_STAT_MSK_RXFRAG_CNT_EXP 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XRXMAC_STAT_MSK_RXMULTF_CNT_EXP 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XRXMAC_STAT_MSK_RXBCAST_CNT_EXP 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XRXMAC_STAT_MSK_RXHIST6_CNT_EXP 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XRXMAC_STAT_MSK_RXHIST5_CNT_EXP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XRXMAC_STAT_MSK_RXHIST4_CNT_EXP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define XRXMAC_STAT_MSK_RXHIST3_CNT_EXP 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define XRXMAC_STAT_MSK_RXHIST2_CNT_EXP 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define XRXMAC_STAT_MSK_RXHIST1_CNT_EXP 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define XRXMAC_STAT_MSK_RXOCTET_CNT_EXP 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define XRXMAC_STAT_MSK_LENERR_CNT_EXP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define XRXMAC_STAT_MSK_CRCERR_CNT_EXP 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define XRXMAC_STAT_MSK_FRAME_RCVD 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define XMAC_FC_MSK 0x00050UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define XMAC_FC_MSK_TX_MAC_NPAUSE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define XMAC_FC_MSK_TX_MAC_PAUSE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define XMAC_FC_MSK_RX_MAC_RPAUSE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define XMAC_CONFIG 0x00060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define XMAC_CONFIG_SEL_CLK_25MHZ 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define XMAC_CONFIG_1G_PCS_BYPASS 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define XMAC_CONFIG_10G_XPCS_BYPASS 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define XMAC_CONFIG_MODE_MASK 0x0000000018000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define XMAC_CONFIG_MODE_XGMII 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define XMAC_CONFIG_MODE_GMII 0x0000000008000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define XMAC_CONFIG_MODE_MII 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define XMAC_CONFIG_LFS_DISABLE 0x0000000004000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define XMAC_CONFIG_LOOPBACK 0x0000000002000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define XMAC_CONFIG_TX_OUTPUT_EN 0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define XMAC_CONFIG_SEL_POR_CLK_SRC 0x0000000000800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define XMAC_CONFIG_LED_POLARITY 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define XMAC_CONFIG_FORCE_LED_ON 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define XMAC_CONFIG_PASS_FLOW_CTRL 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define XMAC_CONFIG_RCV_PAUSE_ENABLE 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define XMAC_CONFIG_MAC2IPP_PKT_CNT_EN 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define XMAC_CONFIG_STRIP_CRC 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define XMAC_CONFIG_ADDR_FILTER_EN 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define XMAC_CONFIG_HASH_FILTER_EN 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define XMAC_CONFIG_RX_CODEV_CHK_DIS 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define XMAC_CONFIG_RESERVED_MULTICAST 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define XMAC_CONFIG_RX_CRC_CHK_DIS 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define XMAC_CONFIG_ERR_CHK_DIS 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define XMAC_CONFIG_PROMISC_GROUP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define XMAC_CONFIG_PROMISCUOUS 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define XMAC_CONFIG_RX_MAC_ENABLE 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define XMAC_CONFIG_WARNING_MSG_EN 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define XMAC_CONFIG_ALWAYS_NO_CRC 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define XMAC_CONFIG_VAR_MIN_IPG_EN 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define XMAC_CONFIG_STRETCH_MODE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define XMAC_CONFIG_TX_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define XMAC_IPG 0x00080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define XMAC_IPG_STRETCH_CONST 0x0000000000e00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define XMAC_IPG_STRETCH_CONST_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define XMAC_IPG_STRETCH_RATIO 0x00000000001f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define XMAC_IPG_STRETCH_RATIO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define XMAC_IPG_IPG_MII_GMII 0x000000000000ff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define XMAC_IPG_IPG_MII_GMII_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define XMAC_IPG_IPG_XGMII 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define XMAC_IPG_IPG_XGMII_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IPG_12_15_XGMII 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IPG_16_19_XGMII 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IPG_20_23_XGMII 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IPG_12_MII_GMII 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IPG_13_MII_GMII 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IPG_14_MII_GMII 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IPG_15_MII_GMII 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IPG_16_MII_GMII 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define XMAC_MIN 0x00088UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define XMAC_MIN_RX_MIN_PKT_SIZE 0x000000003ff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define XMAC_MIN_RX_MIN_PKT_SIZE_SHFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define XMAC_MIN_SLOT_TIME 0x000000000003fc00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define XMAC_MIN_SLOT_TIME_SHFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define XMAC_MIN_TX_MIN_PKT_SIZE 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define XMAC_MIN_TX_MIN_PKT_SIZE_SHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define XMAC_MAX 0x00090UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define XMAC_MAX_FRAME_SIZE 0x0000000000003fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define XMAC_MAX_FRAME_SIZE_SHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define XMAC_ADDR0 0x000a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define XMAC_ADDR0_ADDR0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define XMAC_ADDR1 0x000a8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define XMAC_ADDR1_ADDR1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define XMAC_ADDR2 0x000b0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define XMAC_ADDR2_ADDR2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define XMAC_ADDR_CMPEN 0x00208UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define XMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define XMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define XMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define XMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define XMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define XMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define XMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define XMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define XMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define XMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define XMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define XMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define XMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define XMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define XMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define XMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define XMAC_NUM_ALT_ADDR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define XMAC_ALT_ADDR0(NUM) (0x00218UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define XMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define XMAC_ALT_ADDR1(NUM) (0x00220UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define XMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define XMAC_ALT_ADDR2(NUM) (0x00228UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define XMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define XMAC_ADD_FILT0 0x00818UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define XMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define XMAC_ADD_FILT1 0x00820UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define XMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define XMAC_ADD_FILT2 0x00828UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define XMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define XMAC_ADD_FILT12_MASK 0x00830UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define XMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define XMAC_ADD_FILT00_MASK 0x00838UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define XMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define XMAC_HASH_TBL(NUM) (0x00840UL + (NUM) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define XMAC_HASH_TBL_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define XMAC_NUM_HOST_INFO 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define XMAC_HOST_INFO(NUM) (0x00900UL + (NUM) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define XMAC_PA_DATA0 0x00b80UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define XMAC_PA_DATA0_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define XMAC_PA_DATA1 0x00b88UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define XMAC_PA_DATA1_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define XMAC_DEBUG_SEL 0x00b90UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define XMAC_DEBUG_SEL_XMAC 0x0000000000000078ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define XMAC_DEBUG_SEL_MAC 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define XMAC_TRAIN_VEC 0x00b98UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define XMAC_TRAIN_VEC_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RXMAC_BT_CNT 0x00100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RXMAC_BT_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define RXMAC_BC_FRM_CNT 0x00108UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RXMAC_BC_FRM_CNT_COUNT 0x00000000001fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define RXMAC_MC_FRM_CNT 0x00110UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define RXMAC_MC_FRM_CNT_COUNT 0x00000000001fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define RXMAC_FRAG_CNT 0x00118UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define RXMAC_FRAG_CNT_COUNT 0x00000000001fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define RXMAC_HIST_CNT1 0x00120UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define RXMAC_HIST_CNT1_COUNT 0x00000000001fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define RXMAC_HIST_CNT2 0x00128UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define RXMAC_HIST_CNT2_COUNT 0x00000000001fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define RXMAC_HIST_CNT3 0x00130UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RXMAC_HIST_CNT3_COUNT 0x00000000000fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define RXMAC_HIST_CNT4 0x00138UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define RXMAC_HIST_CNT4_COUNT 0x000000000007ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define RXMAC_HIST_CNT5 0x00140UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define RXMAC_HIST_CNT5_COUNT 0x000000000003ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define RXMAC_HIST_CNT6 0x00148UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define RXMAC_HIST_CNT6_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define RXMAC_MPSZER_CNT 0x00150UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define RXMAC_MPSZER_CNT_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define RXMAC_CRC_ER_CNT 0x00158UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define RXMAC_CRC_ER_CNT_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define RXMAC_CD_VIO_CNT 0x00160UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define RXMAC_CD_VIO_CNT_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define RXMAC_ALIGN_ERR_CNT 0x00168UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RXMAC_ALIGN_ERR_CNT_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TXMAC_FRM_CNT 0x00170UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TXMAC_BYTE_CNT 0x00178UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define LINK_FAULT_CNT 0x00180UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define LINK_FAULT_CNT_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RXMAC_HIST_CNT7 0x00188UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RXMAC_HIST_CNT7_COUNT 0x0000000007ffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define XMAC_SM_REG 0x001a8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define XMAC_SM_REG_STATE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define XMAC_INTER1 0x001b0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define XMAC_INTERN1_SIGNALS1 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define XMAC_INTER2 0x001b8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define XMAC_INTERN2_SIGNALS2 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* BMAC registers, offset from np->mac_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BTXMAC_SW_RST 0x00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BTXMAC_SW_RST_RESET 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BRXMAC_SW_RST 0x00008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BRXMAC_SW_RST_RESET 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BMAC_SEND_PAUSE 0x00010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BMAC_SEND_PAUSE_SEND 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BMAC_SEND_PAUSE_TIME 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BTXMAC_STATUS 0x00020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BTXMAC_STATUS_XMIT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BTXMAC_STATUS_UNDERRUN 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BTXMAC_STATUS_MAX_PKT_ERR 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define BTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define BRXMAC_STATUS 0x00028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define BRXMAC_STATUS_RX_PKT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define BRXMAC_STATUS_OVERFLOW 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define BRXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define BRXMAC_STATUS_ALIGN_ERR_EXP 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define BRXMAC_STATUS_CRC_ERR_EXP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define BRXMAC_STATUS_LEN_ERR_EXP 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define BMAC_CTRL_STATUS 0x00030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define BMAC_CTRL_STATUS_PAUSE_RECV 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define BMAC_CTRL_STATUS_PAUSE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define BMAC_CTRL_STATUS_NOPAUSE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define BMAC_CTRL_STATUS_TIME 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define BMAC_CTRL_STATUS_TIME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define BTXMAC_STATUS_MASK 0x00040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define BRXMAC_STATUS_MASK 0x00048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define BMAC_CTRL_STATUS_MASK 0x00050UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define BTXMAC_CONFIG 0x00060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define BTXMAC_CONFIG_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define BTXMAC_CONFIG_FCS_DISABLE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define BRXMAC_CONFIG 0x00068UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define BRXMAC_CONFIG_DISCARD_DIS 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define BRXMAC_CONFIG_ADDR_FILT_EN 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define BRXMAC_CONFIG_HASH_FILT_EN 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define BRXMAC_CONFIG_PROMISC_GRP 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define BRXMAC_CONFIG_PROMISC 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define BRXMAC_CONFIG_STRIP_FCS 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define BRXMAC_CONFIG_STRIP_PAD 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define BRXMAC_CONFIG_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define BMAC_CTRL_CONFIG 0x00070UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define BMAC_CTRL_CONFIG_TX_PAUSE_EN 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define BMAC_CTRL_CONFIG_RX_PAUSE_EN 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define BMAC_CTRL_CONFIG_PASS_CTRL 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define BMAC_XIF_CONFIG 0x00078UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define BMAC_XIF_CONFIG_TX_OUTPUT_EN 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define BMAC_XIF_CONFIG_MII_LOOPBACK 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define BMAC_XIF_CONFIG_GMII_MODE 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define BMAC_XIF_CONFIG_LINK_LED 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define BMAC_XIF_CONFIG_LED_POLARITY 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define BMAC_XIF_CONFIG_25MHZ_CLOCK 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define BMAC_MIN_FRAME 0x000a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define BMAC_MIN_FRAME_VAL 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define BMAC_MAX_FRAME 0x000a8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define BMAC_MAX_FRAME_MAX_BURST 0x000000003fff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define BMAC_MAX_FRAME_MAX_BURST_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define BMAC_MAX_FRAME_MAX_FRAME 0x0000000000003fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define BMAC_MAX_FRAME_MAX_FRAME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define BMAC_PREAMBLE_SIZE 0x000b0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define BMAC_PREAMBLE_SIZE_VAL 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define BMAC_CTRL_TYPE 0x000c8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define BMAC_ADDR0 0x00100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define BMAC_ADDR0_ADDR0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define BMAC_ADDR1 0x00108UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define BMAC_ADDR1_ADDR1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define BMAC_ADDR2 0x00110UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define BMAC_ADDR2_ADDR2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define BMAC_NUM_ALT_ADDR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define BMAC_ALT_ADDR0(NUM) (0x00118UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define BMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define BMAC_ALT_ADDR1(NUM) (0x00120UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define BMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define BMAC_ALT_ADDR2(NUM) (0x00128UL + (NUM)*0x18UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define BMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define BMAC_FC_ADDR0 0x00268UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define BMAC_FC_ADDR0_ADDR0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define BMAC_FC_ADDR1 0x00270UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define BMAC_FC_ADDR1_ADDR1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define BMAC_FC_ADDR2 0x00278UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define BMAC_FC_ADDR2_ADDR2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define BMAC_ADD_FILT0 0x00298UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define BMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define BMAC_ADD_FILT1 0x002a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define BMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define BMAC_ADD_FILT2 0x002a8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define BMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define BMAC_ADD_FILT12_MASK 0x002b0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define BMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define BMAC_ADD_FILT00_MASK 0x002b8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define BMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define BMAC_HASH_TBL(NUM) (0x002c0UL + (NUM) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define BMAC_HASH_TBL_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define BRXMAC_FRAME_CNT 0x00370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define BRXMAC_FRAME_CNT_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define BRXMAC_MAX_LEN_ERR_CNT 0x00378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define BRXMAC_ALIGN_ERR_CNT 0x00380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define BRXMAC_CRC_ERR_CNT 0x00388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define BRXMAC_CODE_VIOL_ERR_CNT 0x00390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define BRXMAC_CODE_VIOL_ERR_CNT_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define BMAC_STATE_MACHINE 0x003a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define BMAC_ADDR_CMPEN 0x003f8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define BMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define BMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define BMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define BMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define BMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define BMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define BMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define BMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define BMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define BMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define BMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define BMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define BMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define BMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define BMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define BMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define BMAC_NUM_HOST_INFO 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define BMAC_HOST_INFO(NUM) (0x00400UL + (NUM) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define BTXMAC_BYTE_CNT 0x00448UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define BTXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define BTXMAC_FRM_CNT 0x00450UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define BTXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define BRXMAC_BYTE_CNT 0x00458UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define BRXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define HOST_INFO_MPR 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define HOST_INFO_MACRDCTBLN 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* XPCS registers, offset from np->regs + np->xpcs_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define XPCS_CONTROL1 (FZC_MAC + 0x00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define XPCS_CONTROL1_RESET 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define XPCS_CONTROL1_LOOPBACK 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define XPCS_CONTROL1_SPEED_SELECT3 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define XPCS_CONTROL1_CSR_LOW_PWR 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define XPCS_CONTROL1_CSR_SPEED1 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define XPCS_CONTROL1_CSR_SPEED0 0x000000000000003cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define XPCS_STATUS1 (FZC_MAC + 0x00008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define XPCS_STATUS1_CSR_FAULT 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define XPCS_STATUS1_CSR_RXLNK_STAT 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define XPCS_STATUS1_CSR_LPWR_ABLE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define XPCS_DEVICE_IDENTIFIER_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define XPCS_SPEED_ABILITY_10GIG 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define XPCS_DEV_IN_PKG_CSR_VEND2 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define XPCS_DEV_IN_PKG_CSR_VEND1 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define XPCS_DEV_IN_PKG_DTE_XS 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define XPCS_DEV_IN_PKG_PHY_XS 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define XPCS_DEV_IN_PKG_PCS 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define XPCS_DEV_IN_PKG_WIS 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define XPCS_DEV_IN_PKG_PMD_PMA 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define XPCS_DEV_IN_PKG_CLS22 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define XPCS_CONTROL2 (FZC_MAC + 0x00028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define XPCS_CONTROL2_CSR_PSC_SEL 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define XPCS_STATUS2 (FZC_MAC + 0x00030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define XPCS_STATUS2_CSR_DEV_PRES 0x000000000000c000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define XPCS_STATUS2_CSR_TX_FAULT 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define XPCS_STATUS2_CSR_RCV_FAULT 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define XPCS_STATUS2_TEN_GBASE_W 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define XPCS_STATUS2_TEN_GBASE_X 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define XPCS_STATUS2_TEN_GBASE_R 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define XPCS_PKG_ID (FZC_MAC + 0x00038UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define XPCS_PKG_ID_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define XPCS_STATUS_CSR_LANE_ALIGN 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define XPCS_STATUS_CSR_PATTEST_CAP 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define XPCS_STATUS_CSR_LANE3_SYNC 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define XPCS_STATUS_CSR_LANE2_SYNC 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define XPCS_STATUS_CSR_LANE1_SYNC 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define XPCS_STATUS_CSR_LANE0_SYNC 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define XPCS_TEST_CONTROL_TXTST_EN 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define XPCS_TEST_CONTROL_TPAT_SEL 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define XPCS_CFG_VENDOR1_DBG_IOTST 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define XPCS_CFG_VENDOR1_DBG_SEL 0x0000000000000078ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define XPCS_CFG_VENDOR1_BYPASS_DET 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define XPCS_CFG_VENDOR1_TXBUF_EN 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define XPCS_CFG_VENDOR1_XPCS_EN 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define XPCS_DIAG_VENDOR2_SSM_LANE3 0x0000000001e00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define XPCS_DIAG_VENDOR2_SSM_LANE2 0x00000000001e0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define XPCS_DIAG_VENDOR2_SSM_LANE1 0x000000000001e000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define XPCS_DIAG_VENDOR2_SSM_LANE0 0x0000000000001e00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define XPCS_DIAG_VENDOR2_EBUF_SM 0x00000000000001feULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define XPCS_DIAG_VENDOR2_RCV_SM 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define XPCS_MASK1 (FZC_MAC + 0x00060UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define XPCS_MASK1_FAULT_MASK 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define XPCS_MASK1_RXALIGN_STAT_MSK 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define XPCS_PKT_COUNT_TX 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define XPCS_PKT_COUNT_RX 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define XPCS_TX_SM (FZC_MAC + 0x00070UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define XPCS_TX_SM_VAL 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define XPCS_DESKEW_ERR_CNT_VAL 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define XPCS_SYMERR_CNT01_LANE1 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define XPCS_SYMERR_CNT01_LANE0 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define XPCS_SYMERR_CNT23_LANE3 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define XPCS_SYMERR_CNT23_LANE2 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define XPCS_TRAINING_VECTOR_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* PCS registers, offset from np->regs + np->pcs_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define PCS_MII_CTL (FZC_MAC + 0x00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define PCS_MII_CTL_RST 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define PCS_MII_CTL_10_100_SPEED 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define PCS_MII_AUTONEG_EN 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define PCS_MII_PWR_DOWN 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define PCS_MII_ISOLATE 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define PCS_MII_AUTONEG_RESTART 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define PCS_MII_DUPLEX 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define PCS_MII_COLL_TEST 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define PCS_MII_1000MB_SPEED 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define PCS_MII_STAT (FZC_MAC + 0x00008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PCS_MII_STAT_EXT_STATUS 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define PCS_MII_STAT_AUTONEG_DONE 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define PCS_MII_STAT_REMOTE_FAULT 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define PCS_MII_STAT_AUTONEG_ABLE 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define PCS_MII_STAT_LINK_STATUS 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define PCS_MII_STAT_JABBER_DET 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define PCS_MII_STAT_EXT_CAP 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PCS_MII_ADV (FZC_MAC + 0x00010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define PCS_MII_ADV_NEXT_PAGE 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define PCS_MII_ADV_ACK 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define PCS_MII_ADV_REMOTE_FAULT 0x0000000000003000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define PCS_MII_ADV_ASM_DIR 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define PCS_MII_ADV_PAUSE 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PCS_MII_ADV_HALF_DUPLEX 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define PCS_MII_ADV_FULL_DUPLEX 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define PCS_MII_PARTNER (FZC_MAC + 0x00018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define PCS_MII_PARTNER_NEXT_PAGE 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define PCS_MII_PARTNER_ACK 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define PCS_MII_PARTNER_REMOTE_FAULT 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define PCS_MII_PARTNER_PAUSE 0x0000000000000180ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define PCS_MII_PARTNER_HALF_DUPLEX 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define PCS_MII_PARTNER_FULL_DUPLEX 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define PCS_CONF (FZC_MAC + 0x00020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define PCS_CONF_MASK 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define PCS_CONF_10MS_TMR_OVERRIDE 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define PCS_CONF_JITTER_STUDY 0x0000000000000018ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define PCS_CONF_SIGDET_ACTIVE_LOW 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define PCS_CONF_SIGDET_OVERRIDE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define PCS_CONF_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define PCS_STATE (FZC_MAC + 0x00028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define PCS_STATE_D_PARTNER_FAIL 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define PCS_STATE_D_WAIT_C_CODES_ACK 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define PCS_STATE_D_SYNC_LOSS 0x0000000008000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define PCS_STATE_D_NO_GOOD_C_CODES 0x0000000004000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define PCS_STATE_D_SERDES 0x0000000002000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define PCS_STATE_D_BREAKLINK_C_CODES 0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define PCS_STATE_L_SIGDET 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define PCS_STATE_L_SYNC_LOSS 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define PCS_STATE_L_C_CODES 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define PCS_STATE_LINK_CFG_STATE 0x000000000001e000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define PCS_STATE_SEQ_DET_STATE 0x0000000000001800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define PCS_STATE_WORD_SYNC_STATE 0x0000000000000700ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define PCS_STATE_NO_IDLE 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define PCS_INTERRUPT (FZC_MAC + 0x00030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define PCS_INTERRUPT_LSTATUS 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define PCS_DPATH_MODE_PCS 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PCS_DPATH_MODE_MII 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PCS_DPATH_MODE_LINKUP_F_ENAB 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PCS_PKT_CNT (FZC_MAC + 0x000c0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PCS_PKT_CNT_RX 0x0000000007ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PCS_PKT_CNT_TX 0x00000000000007ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define MIF_BB_MDC (FZC_MAC + 0x16000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define MIF_BB_MDC_CLK 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define MIF_BB_MDO (FZC_MAC + 0x16008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define MIF_BB_MDO_DAT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define MIF_BB_MDO_EN_VAL 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MIF_FRAME_OUTPUT_ST 0x00000000c0000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define MIF_FRAME_OUTPUT_ST_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define MIF_FRAME_OUTPUT_OP_ADDR 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define MIF_FRAME_OUTPUT_OP_WRITE 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define MIF_FRAME_OUTPUT_OP_READ_INC 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define MIF_FRAME_OUTPUT_OP_READ 0x0000000030000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MIF_FRAME_OUTPUT_OP_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define MIF_FRAME_OUTPUT_PORT 0x000000000f800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MIF_FRAME_OUTPUT_PORT_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MIF_FRAME_OUTPUT_REG 0x00000000007c0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MIF_FRAME_OUTPUT_REG_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MIF_FRAME_OUTPUT_TA 0x0000000000030000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MIF_FRAME_OUTPUT_TA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MIF_FRAME_OUTPUT_DATA 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MIF_FRAME_OUTPUT_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MDIO_ADDR_OP(port, dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) MIF_FRAME_OUTPUT_OP_ADDR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define MDIO_READ_OP(port, dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MIF_FRAME_OUTPUT_OP_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define MDIO_WRITE_OP(port, dev, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MIF_FRAME_OUTPUT_OP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MII_READ_OP(port, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define MII_WRITE_OP(port, reg, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define MIF_CONFIG (FZC_MAC + 0x16020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define MIF_CONFIG_ATCA_GE 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define MIF_CONFIG_INDIRECT_MODE 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MIF_CONFIG_POLL_PRT_PHYADDR 0x0000000000003c00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MIF_CONFIG_POLL_DEV_REG_ADDR 0x00000000000003e0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MIF_CONFIG_BB_MODE 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define MIF_CONFIG_POLL_EN 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define MIF_CONFIG_BB_SER_SEL 0x0000000000000006ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define MIF_CONFIG_MANUAL_MODE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MIF_POLL_STATUS (FZC_MAC + 0x16028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MIF_POLL_STATUS_DATA 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MIF_POLL_STATUS_STAT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MIF_POLL_MASK (FZC_MAC + 0x16030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MIF_POLL_MASK_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define MIF_SM (FZC_MAC + 0x16038UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define MIF_SM_PORT_ADDR 0x00000000001f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define MIF_SM_MDI_1 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define MIF_SM_MDI_0 0x0000000000002400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define MIF_SM_MDCLK 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define MIF_SM_MDO_EN 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define MIF_SM_MDO 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define MIF_SM_MDI 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define MIF_SM_CTL 0x00000000000001c0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define MIF_SM_EX 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define MIF_STATUS (FZC_MAC + 0x16040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define MIF_STATUS_MDINT1 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MIF_STATUS_MDINT0 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MIF_MASK (FZC_MAC + 0x16048UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define MIF_MASK_MDINT1 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define MIF_MASK_MDINT0 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define MIF_MASK_PEU_ERR 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define MIF_MASK_YC 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define MIF_MASK_XGE_ERR0 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define MIF_MASK_MIF_INIT_DONE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define ENET_SERDES_RESET (FZC_MAC + 0x14000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define ENET_SERDES_RESET_1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define ENET_SERDES_RESET_0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define ENET_SERDES_CFG (FZC_MAC + 0x14008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define ENET_SERDES_BE_LOOPBACK 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define ENET_SERDES_CFG_FORCE_RDY 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define ENET_SERDES_PLL_FBDIV0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define ENET_SERDES_PLL_FBDIV1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define ENET_SERDES_PLL_FBDIV2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define ENET_SERDES_PLL_HRATE0 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ENET_SERDES_PLL_HRATE1 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define ENET_SERDES_PLL_HRATE2 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define ENET_SERDES_PLL_HRATE3 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define ENET_SERDES_CTRL_SDET_0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define ENET_SERDES_CTRL_SDET_1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define ENET_SERDES_CTRL_SDET_2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define ENET_SERDES_CTRL_SDET_3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define ENET_SERDES_CTRL_EMPH_0 0x0000000000000070ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define ENET_SERDES_CTRL_EMPH_0_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define ENET_SERDES_CTRL_EMPH_1 0x0000000000000380ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ENET_SERDES_CTRL_EMPH_1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define ENET_SERDES_CTRL_EMPH_2 0x0000000000001c00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define ENET_SERDES_CTRL_EMPH_2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define ENET_SERDES_CTRL_EMPH_3 0x000000000000e000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define ENET_SERDES_CTRL_EMPH_3_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define ENET_SERDES_CTRL_LADJ_0 0x0000000000070000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define ENET_SERDES_CTRL_LADJ_0_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define ENET_SERDES_CTRL_LADJ_1 0x0000000000380000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define ENET_SERDES_CTRL_LADJ_1_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define ENET_SERDES_CTRL_LADJ_2 0x0000000001c00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define ENET_SERDES_CTRL_LADJ_2_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define ENET_SERDES_CTRL_LADJ_3 0x000000000e000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define ENET_SERDES_CTRL_LADJ_3_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define ENET_SERDES_CTRL_RXITERM_0 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define ENET_SERDES_CTRL_RXITERM_1 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define ENET_SERDES_CTRL_RXITERM_2 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define ENET_SERDES_CTRL_RXITERM_3 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define ENET_SERDES_TEST_MD_0 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define ENET_SERDES_TEST_MD_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define ENET_SERDES_TEST_MD_1 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define ENET_SERDES_TEST_MD_1_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define ENET_SERDES_TEST_MD_2 0x0000000000000030ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define ENET_SERDES_TEST_MD_2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define ENET_SERDES_TEST_MD_3 0x00000000000000c0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define ENET_SERDES_TEST_MD_3_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define ENET_TEST_MD_NO_LOOPBACK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define ENET_TEST_MD_EWRAP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define ENET_TEST_MD_PAD_LOOPBACK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define ENET_TEST_MD_REV_LOOPBACK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define ESR_INT_SIGNALS_ALL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define ESR_INT_SIGNALS_P0_BITS 0x0000000033e0000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define ESR_INT_SIGNALS_P1_BITS 0x000000000c1f00f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define ESR_INT_SRDY0_P0 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define ESR_INT_DET0_P0 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define ESR_INT_SRDY0_P1 0x0000000008000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define ESR_INT_DET0_P1 0x0000000004000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define ESR_INT_XSRDY_P0 0x0000000002000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define ESR_INT_XDP_P0_CH3 0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define ESR_INT_XDP_P0_CH2 0x0000000000800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define ESR_INT_XDP_P0_CH1 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define ESR_INT_XDP_P0_CH0 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define ESR_INT_XSRDY_P1 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define ESR_INT_XDP_P1_CH3 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define ESR_INT_XDP_P1_CH2 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define ESR_INT_XDP_P1_CH1 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define ESR_INT_XDP_P1_CH0 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ESR_INT_SLOSS_P1_CH3 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define ESR_INT_SLOSS_P1_CH2 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define ESR_INT_SLOSS_P1_CH1 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define ESR_INT_SLOSS_P1_CH0 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define ESR_INT_SLOSS_P0_CH3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define ESR_INT_SLOSS_P0_CH2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define ESR_INT_SLOSS_P0_CH1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define ESR_INT_SLOSS_P0_CH0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define ESR_DEBUG_SEL_VAL 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* SerDes registers behind MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define NIU_ESR_DEV_ADDR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define ESR_BASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define ESR_RXTX_COMM_CTRL_L (ESR_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define ESR_RXTX_COMM_CTRL_H (ESR_BASE + 0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define ESR_RXTX_RESET_CTRL_L (ESR_BASE + 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define ESR_RXTX_RESET_CTRL_H (ESR_BASE + 0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define ESR_RX_POWER_CTRL_L (ESR_BASE + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define ESR_RX_POWER_CTRL_H (ESR_BASE + 0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define ESR_TX_POWER_CTRL_L (ESR_BASE + 0x0006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define ESR_TX_POWER_CTRL_H (ESR_BASE + 0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define ESR_MISC_POWER_CTRL_L (ESR_BASE + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define ESR_MISC_POWER_CTRL_H (ESR_BASE + 0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define ESR_RXTX_CTRL_L(CHAN) (ESR_BASE + 0x0080 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define ESR_RXTX_CTRL_H(CHAN) (ESR_BASE + 0x0081 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define ESR_RXTX_CTRL_BIASCNTL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define ESR_RXTX_CTRL_RESV1 0x7c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define ESR_RXTX_CTRL_TDENFIFO 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define ESR_RXTX_CTRL_TDWS20 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define ESR_RXTX_CTRL_VMUXLO 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define ESR_RXTX_CTRL_VMUXLO_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define ESR_RXTX_CTRL_VPULSELO 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define ESR_RXTX_CTRL_VPULSELO_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define ESR_RXTX_CTRL_RESV2 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define ESR_RXTX_CTRL_RESV3 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define ESR_RXTX_CTRL_RXPRESWIN 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define ESR_RXTX_CTRL_RXPRESWIN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define ESR_RXTX_CTRL_RESV4 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define ESR_RXTX_CTRL_RISEFALL 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define ESR_RXTX_CTRL_RISEFALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define ESR_RXTX_CTRL_RESV5 0x000000fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define ESR_RXTX_CTRL_ENSTRETCH 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define ESR_RXTX_TUNING_L(CHAN) (ESR_BASE + 0x0082 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define ESR_RXTX_TUNING_H(CHAN) (ESR_BASE + 0x0083 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define ESR_RX_SYNCCHAR_L(CHAN) (ESR_BASE + 0x0084 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define ESR_RX_SYNCCHAR_H(CHAN) (ESR_BASE + 0x0085 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define ESR_RXTX_TEST_L(CHAN) (ESR_BASE + 0x0086 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define ESR_RXTX_TEST_H(CHAN) (ESR_BASE + 0x0087 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define ESR_GLUE_CTRL0_L(CHAN) (ESR_BASE + 0x0088 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define ESR_GLUE_CTRL0_H(CHAN) (ESR_BASE + 0x0089 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define ESR_GLUE_CTRL0_RESV1 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define ESR_GLUE_CTRL0_BLTIME 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define ESR_GLUE_CTRL0_BLTIME_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define ESR_GLUE_CTRL0_RESV2 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define ESR_GLUE_CTRL0_RXLOS_TEST 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define ESR_GLUE_CTRL0_RESV3 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define ESR_GLUE_CTRL0_RXLOSENAB 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define ESR_GLUE_CTRL0_FASTRESYNC 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define ESR_GLUE_CTRL0_SRATE 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define ESR_GLUE_CTRL0_SRATE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define ESR_GLUE_CTRL0_THCNT 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define ESR_GLUE_CTRL0_THCNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define BLTIME_64_CYCLES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define BLTIME_128_CYCLES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define BLTIME_256_CYCLES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define BLTIME_300_CYCLES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define BLTIME_384_CYCLES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define BLTIME_512_CYCLES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define BLTIME_1024_CYCLES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define BLTIME_2048_CYCLES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define ESR_GLUE_CTRL1_L(CHAN) (ESR_BASE + 0x008a + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define ESR_GLUE_CTRL1_H(CHAN) (ESR_BASE + 0x008b + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define ESR_RXTX_TUNING1_L(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define ESR_RXTX_TUNING1_H(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define ESR_RXTX_TUNING2_L(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define ESR_RXTX_TUNING2_H(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define ESR_RXTX_TUNING3_L(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define ESR_RXTX_TUNING3_H(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define NIU_ESR2_DEV_ADDR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define ESR2_BASE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define ESR2_TI_PLL_CFG_L (ESR2_BASE + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define ESR2_TI_PLL_CFG_H (ESR2_BASE + 0x001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define PLL_CFG_STD 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define PLL_CFG_STD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define PLL_CFG_LD 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define PLL_CFG_LD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define PLL_CFG_MPY 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define PLL_CFG_MPY_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define PLL_CFG_MPY_4X 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define PLL_CFG_MPY_5X 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define PLL_CFG_MPY_6X 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define PLL_CFG_MPY_8X 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define PLL_CFG_MPY_10X 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define PLL_CFG_MPY_12X 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define PLL_CFG_MPY_12P5X 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define PLL_CFG_ENPLL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define ESR2_TI_PLL_STS_H (ESR2_BASE + 0x003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define PLL_STS_LOCK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define ESR2_TI_PLL_TEST_CFG_L (ESR2_BASE + 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define ESR2_TI_PLL_TEST_CFG_H (ESR2_BASE + 0x005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define PLL_TEST_INVPATT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define PLL_TEST_RATE 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define PLL_TEST_RATE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define PLL_TEST_CFG_ENBSAC 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define PLL_TEST_CFG_ENBSRX 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define PLL_TEST_CFG_ENBSTX 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define PLL_TEST_CFG_LOOPBACK_PAD 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define PLL_TEST_CFG_LOOPBACK_CML_DIS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define PLL_TEST_CFG_LOOPBACK_CML_EN 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define PLL_TEST_CFG_CLKBYP 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define PLL_TEST_CFG_CLKBYP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define PLL_TEST_CFG_EN_RXPATT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define PLL_TEST_CFG_EN_TXPATT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define PLL_TEST_CFG_TPATT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define PLL_TEST_CFG_TPATT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define ESR2_TI_PLL_TX_CFG_L(CHAN) (ESR2_BASE + 0x100 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define ESR2_TI_PLL_TX_CFG_H(CHAN) (ESR2_BASE + 0x101 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define PLL_TX_CFG_RDTCT 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define PLL_TX_CFG_RDTCT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define PLL_TX_CFG_ENIDL 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define PLL_TX_CFG_BSTX 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define PLL_TX_CFG_ENFTP 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define PLL_TX_CFG_DE 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define PLL_TX_CFG_DE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define PLL_TX_CFG_SWING_125MV 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define PLL_TX_CFG_SWING_250MV 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define PLL_TX_CFG_SWING_500MV 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define PLL_TX_CFG_SWING_625MV 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define PLL_TX_CFG_SWING_750MV 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define PLL_TX_CFG_SWING_1000MV 0x00000a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define PLL_TX_CFG_SWING_1250MV 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define PLL_TX_CFG_SWING_1375MV 0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define PLL_TX_CFG_CM 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define PLL_TX_CFG_INVPAIR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define PLL_TX_CFG_RATE 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define PLL_TX_CFG_RATE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define PLL_TX_CFG_RATE_FULL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define PLL_TX_CFG_RATE_HALF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define PLL_TX_CFG_RATE_QUAD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define PLL_TX_CFG_BUSWIDTH 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define PLL_TX_CFG_BUSWIDTH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define PLL_TX_CFG_ENTEST 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define PLL_TX_CFG_ENTX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define ESR2_TI_PLL_TX_STS_L(CHAN) (ESR2_BASE + 0x102 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define ESR2_TI_PLL_TX_STS_H(CHAN) (ESR2_BASE + 0x103 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define PLL_TX_STS_RDTCTIP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define PLL_TX_STS_TESTFAIL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define ESR2_TI_PLL_RX_CFG_L(CHAN) (ESR2_BASE + 0x120 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define ESR2_TI_PLL_RX_CFG_H(CHAN) (ESR2_BASE + 0x121 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define PLL_RX_CFG_BSINRXN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define PLL_RX_CFG_BSINRXP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define PLL_RX_CFG_EQ_MAX_LF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define PLL_RX_CFG_EQ_LP_ADAPTIVE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define PLL_RX_CFG_EQ_LP_1084MHZ 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define PLL_RX_CFG_EQ_LP_805MHZ 0x00480000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define PLL_RX_CFG_EQ_LP_573MHZ 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define PLL_RX_CFG_EQ_LP_402MHZ 0x00580000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define PLL_RX_CFG_EQ_LP_304MHZ 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define PLL_RX_CFG_EQ_LP_216MHZ 0x00680000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define PLL_RX_CFG_EQ_LP_156MHZ 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define PLL_RX_CFG_EQ_LP_135MHZ 0x00780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define PLL_RX_CFG_EQ_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define PLL_RX_CFG_CDR 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define PLL_RX_CFG_CDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define PLL_RX_CFG_LOS_DIS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define PLL_RX_CFG_LOS_HTHRESH 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define PLL_RX_CFG_LOS_LTHRESH 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define PLL_RX_CFG_ALIGN_DIS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define PLL_RX_CFG_ALIGN_ENA 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define PLL_RX_CFG_ALIGN_JOG 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define PLL_RX_CFG_TERM_VDDT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define PLL_RX_CFG_TERM_0P8VDDT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define PLL_RX_CFG_TERM_FLOAT 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define PLL_RX_CFG_INVPAIR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define PLL_RX_CFG_RATE 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define PLL_RX_CFG_RATE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define PLL_RX_CFG_RATE_FULL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define PLL_RX_CFG_RATE_HALF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define PLL_RX_CFG_RATE_QUAD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define PLL_RX_CFG_BUSWIDTH 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define PLL_RX_CFG_BUSWIDTH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define PLL_RX_CFG_ENTEST 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define PLL_RX_CFG_ENRX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define ESR2_TI_PLL_RX_STS_L(CHAN) (ESR2_BASE + 0x122 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define ESR2_TI_PLL_RX_STS_H(CHAN) (ESR2_BASE + 0x123 + (CHAN) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define PLL_RX_STS_CRCIDTCT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define PLL_RX_STS_CWDTCT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define PLL_RX_STS_BSRXN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define PLL_RX_STS_BSRXP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define PLL_RX_STS_LOSDTCT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define PLL_RX_STS_ODDCG 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define PLL_RX_STS_SYNC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define PLL_RX_STS_TESTFAIL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define ENET_VLAN_TBL(IDX) (FZC_FFLP + 0x00000UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define ENET_VLAN_TBL_PARITY1 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define ENET_VLAN_TBL_PARITY0 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define ENET_VLAN_TBL_VPR 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define ENET_VLAN_TBL_VLANRDCTBLN 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define ENET_VLAN_TBL_SHIFT(PORT) ((PORT) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define ENET_VLAN_TBL_NUM_ENTRIES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define FFLP_VLAN_PAR_ERR (FZC_FFLP + 0x0800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define FFLP_VLAN_PAR_ERR_ERR 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define FFLP_VLAN_PAR_ERR_M_ERR 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define FFLP_VLAN_PAR_ERR_ADDR 0x000000003ffc0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define FFLP_VLAN_PAR_ERR_DATA 0x000000000003ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define L2_CLS(IDX) (FZC_FFLP + 0x20000UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define L2_CLS_VLD 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define L2_CLS_ETYPE 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define L2_CLS_ETYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define L3_CLS(IDX) (FZC_FFLP + 0x20010UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define L3_CLS_VALID 0x0000000002000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define L3_CLS_IPVER 0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define L3_CLS_PID 0x0000000000ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define L3_CLS_PID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define L3_CLS_TOSMASK 0x000000000000ff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define L3_CLS_TOSMASK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define L3_CLS_TOS 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define L3_CLS_TOS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define TCAM_KEY(IDX) (FZC_FFLP + 0x20030UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define TCAM_KEY_DISC 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define TCAM_KEY_TSEL 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define TCAM_KEY_IPADDR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define TCAM_KEY_0 (FZC_FFLP + 0x20090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define TCAM_KEY_1 (FZC_FFLP + 0x20098UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define TCAM_KEY_2 (FZC_FFLP + 0x200a0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define TCAM_KEY_3 (FZC_FFLP + 0x200a8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define TCAM_KEY_MASK_0 (FZC_FFLP + 0x200b0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define TCAM_KEY_MASK_0_KEY_SEL 0x00000000000000ffULL /* bits 192-199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define TCAM_KEY_MASK_1 (FZC_FFLP + 0x200b8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define TCAM_KEY_MASK_1_KEY_SEL 0xffffffffffffffffULL /* bits 128-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define TCAM_KEY_MASK_2 (FZC_FFLP + 0x200c0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define TCAM_KEY_MASK_2_KEY_SEL 0xffffffffffffffffULL /* bits 64-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define TCAM_KEY_MASK_3 (FZC_FFLP + 0x200c8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define TCAM_KEY_MASK_3_KEY_SEL 0xffffffffffffffffULL /* bits 0-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define TCAM_CTL (FZC_FFLP + 0x200d0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define TCAM_CTL_RWC 0x00000000001c0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define TCAM_CTL_RWC_TCAM_WRITE 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define TCAM_CTL_RWC_TCAM_READ 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define TCAM_CTL_RWC_TCAM_COMPARE 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define TCAM_CTL_RWC_RAM_WRITE 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define TCAM_CTL_RWC_RAM_READ 0x0000000000140000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define TCAM_CTL_STAT 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define TCAM_CTL_MATCH 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define TCAM_CTL_LOC 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define TCAM_ERR (FZC_FFLP + 0x200d8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define TCAM_ERR_ERR 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define TCAM_ERR_P_ECC 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define TCAM_ERR_MULT 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define TCAM_ERR_ADDR 0x0000000000ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define TCAM_ERR_SYNDROME 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define HASH_LOOKUP_ERR_LOG1 (FZC_FFLP + 0x200e0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define HASH_LOOKUP_ERR_LOG1_ERR 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define HASH_LOOKUP_ERR_LOG1_MULT_LK 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define HASH_LOOKUP_ERR_LOG1_CU 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define HASH_LOOKUP_ERR_LOG1_MULT_BIT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define HASH_LOOKUP_ERR_LOG2 (FZC_FFLP + 0x200e8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define HASH_LOOKUP_ERR_LOG2_H1 0x000000007ffff800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define HASH_LOOKUP_ERR_LOG2_SUBAREA 0x0000000000000700ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define HASH_LOOKUP_ERR_LOG2_SYNDROME 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define FFLP_CFG_1 (FZC_FFLP + 0x20100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define FFLP_CFG_1_TCAM_DIS 0x0000000004000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define FFLP_CFG_1_PIO_DBG_SEL 0x0000000003800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define FFLP_CFG_1_PIO_FIO_RST 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define FFLP_CFG_1_PIO_FIO_LAT 0x0000000000300000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define FFLP_CFG_1_CAMLAT 0x00000000000f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define FFLP_CFG_1_CAMLAT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define FFLP_CFG_1_CAMRATIO 0x000000000000f000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define FFLP_CFG_1_CAMRATIO_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define FFLP_CFG_1_FCRAMRATIO 0x0000000000000f00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define FFLP_CFG_1_FCRAMRATIO_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define FFLP_CFG_1_FCRAMOUTDR_MASK 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define FFLP_CFG_1_FCRAMOUTDR_NORMAL 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define FFLP_CFG_1_FCRAMOUTDR_STRONG 0x0000000000000050ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define FFLP_CFG_1_FCRAMOUTDR_WEAK 0x00000000000000a0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define FFLP_CFG_1_FCRAMQS 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define FFLP_CFG_1_ERRORDIS 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define FFLP_CFG_1_FFLPINITDONE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define FFLP_CFG_1_LLCSNAP 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define DEFAULT_FCRAMRATIO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define DEFAULT_TCAM_LATENCY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define DEFAULT_TCAM_ACCESS_RATIO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define TCP_CFLAG_MSK (FZC_FFLP + 0x20108UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define TCP_CFLAG_MSK_MASK 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define FCRAM_REF_TMR (FZC_FFLP + 0x20110UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define FCRAM_REF_TMR_MAX 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define FCRAM_REF_TMR_MAX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define FCRAM_REF_TMR_MIN 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define FCRAM_REF_TMR_MIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define DEFAULT_FCRAM_REFRESH_MAX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define DEFAULT_FCRAM_REFRESH_MIN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define FCRAM_FIO_ADDR (FZC_FFLP + 0x20118UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define FCRAM_FIO_ADDR_ADDR 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define FCRAM_FIO_DAT (FZC_FFLP + 0x20120UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define FCRAM_FIO_DAT_DATA 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define FCRAM_ERR_TST0 (FZC_FFLP + 0x20128UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define FCRAM_ERR_TST0_SYND 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define FCRAM_ERR_TST1 (FZC_FFLP + 0x20130UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define FCRAM_ERR_TST1_DAT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define FCRAM_ERR_TST2 (FZC_FFLP + 0x20138UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define FCRAM_ERR_TST2_DAT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define FFLP_ERR_MASK (FZC_FFLP + 0x20140UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define FFLP_ERR_MASK_HSH_TBL_DAT 0x00000000000007f8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define FFLP_ERR_MASK_HSH_TBL_LKUP 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define FFLP_ERR_MASK_TCAM 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define FFLP_ERR_MASK_VLAN 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define FFLP_DBG_TRAIN_VCT (FZC_FFLP + 0x20148UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define FFLP_DBG_TRAIN_VCT_VECTOR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define FCRAM_PHY_RD_LAT (FZC_FFLP + 0x20150UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define FCRAM_PHY_RD_LAT_LAT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* Ethernet TCAM format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define TCAM_ETHKEY0_RESV1 0xffffffffffffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define TCAM_ETHKEY0_CLASS_CODE 0x00000000000000f8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define TCAM_ETHKEY0_CLASS_CODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define TCAM_ETHKEY0_RESV2 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define TCAM_ETHKEY2_FRAME_BYTE8 0xff00000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define TCAM_ETHKEY2_FRAME_BYTE9 0x00ff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define TCAM_ETHKEY2_FRAME_BYTE10 0x0000ff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define TCAM_ETHKEY2_FRAME_RESV 0x000000ffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define TCAM_ETHKEY3_FRAME_RESV 0xffffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* IPV4 TCAM format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define TCAM_V4KEY0_RESV1 0xffffffffffffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define TCAM_V4KEY0_CLASS_CODE 0x00000000000000f8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define TCAM_V4KEY0_CLASS_CODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define TCAM_V4KEY0_RESV2 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define TCAM_V4KEY1_L2RDCNUM 0xf800000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define TCAM_V4KEY1_L2RDCNUM_SHIFT 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define TCAM_V4KEY1_NOPORT 0x0400000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define TCAM_V4KEY1_RESV 0x03ffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define TCAM_V4KEY2_RESV 0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define TCAM_V4KEY2_TOS 0x0000ff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define TCAM_V4KEY2_TOS_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define TCAM_V4KEY2_PROTO 0x000000ff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define TCAM_V4KEY2_PROTO_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define TCAM_V4KEY2_PORT_SPI 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define TCAM_V4KEY2_PORT_SPI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define TCAM_V4KEY3_SADDR 0xffffffff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define TCAM_V4KEY3_SADDR_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define TCAM_V4KEY3_DADDR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define TCAM_V4KEY3_DADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* IPV6 TCAM format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define TCAM_V6KEY0_RESV1 0xffffffffffffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define TCAM_V6KEY0_CLASS_CODE 0x00000000000000f8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define TCAM_V6KEY0_CLASS_CODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define TCAM_V6KEY0_RESV2 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define TCAM_V6KEY1_L2RDCNUM 0xf800000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define TCAM_V6KEY1_L2RDCNUM_SHIFT 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define TCAM_V6KEY1_NOPORT 0x0400000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define TCAM_V6KEY1_RESV 0x03ff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define TCAM_V6KEY1_TOS 0x0000ff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define TCAM_V6KEY1_TOS_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define TCAM_V6KEY1_NEXT_HDR 0x000000ff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define TCAM_V6KEY1_NEXT_HDR_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define TCAM_V6KEY1_PORT_SPI 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define TCAM_V6KEY1_PORT_SPI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define TCAM_V6KEY2_ADDR_HIGH 0xffffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define TCAM_V6KEY3_ADDR_LOW 0xffffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define TCAM_ASSOCDATA_SYNDROME 0x000003fffc000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define TCAM_ASSOCDATA_SYNDROME_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define TCAM_ASSOCDATA_ZFID 0x0000000003ffc000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define TCAM_ASSOCDATA_ZFID_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define TCAM_ASSOCDATA_V4_ECC_OK 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define TCAM_ASSOCDATA_DISC 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define TCAM_ASSOCDATA_TRES_MASK 0x0000000000000c00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define TCAM_ASSOCDATA_TRES_USE_L2RDC 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define TCAM_ASSOCDATA_TRES_USE_OFFSET 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define TCAM_ASSOCDATA_TRES_OVR_RDC 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF 0x0000000000000c00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define TCAM_ASSOCDATA_RDCTBL 0x0000000000000380ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define TCAM_ASSOCDATA_RDCTBL_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define TCAM_ASSOCDATA_OFFSET 0x000000000000007cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define TCAM_ASSOCDATA_OFFSET_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define TCAM_ASSOCDATA_ZFVLD 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define TCAM_ASSOCDATA_AGE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define FLOW_KEY(IDX) (FZC_FFLP + 0x40000UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define FLOW_KEY_PORT 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define FLOW_KEY_L2DA 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define FLOW_KEY_VLAN 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define FLOW_KEY_IPSA 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define FLOW_KEY_IPDA 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define FLOW_KEY_PROTO 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define FLOW_KEY_L4_0 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define FLOW_KEY_L4_0_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define FLOW_KEY_L4_1 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define FLOW_KEY_L4_1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define FLOW_KEY_L4_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define FLOW_KEY_L4_RESV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define FLOW_KEY_L4_BYTE12 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define FLOW_KEY_L4_BYTE56 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define H1POLY (FZC_FFLP + 0x40060UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define H1POLY_INITVAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define H2POLY (FZC_FFLP + 0x40068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define H2POLY_INITVAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define FLW_PRT_SEL(IDX) (FZC_FFLP + 0x40070UL + (IDX) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define FLW_PRT_SEL_EXT 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define FLW_PRT_SEL_MASK 0x0000000000001f00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define FLW_PRT_SEL_MASK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define FLW_PRT_SEL_BASE 0x000000000000001fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define FLW_PRT_SEL_BASE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define HASH_TBL_ADDR(IDX) (FFLP + 0x00000UL + (IDX) * 8192UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define HASH_TBL_ADDR_AUTOINC 0x0000000000800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define HASH_TBL_ADDR_ADDR 0x00000000007fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define HASH_TBL_DATA(IDX) (FFLP + 0x00008UL + (IDX) * 8192UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define HASH_TBL_DATA_DATA 0xffffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* FCRAM hash table entries are up to 8 64-bit words in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * The layout of each entry is determined by the settings in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * first word, which is the header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * The indexing is controllable per partition (there is one partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * per RDC group, thus a total of eight) using the BASE and MASK fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * of FLW_PRT_SEL above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define FCRAM_SIZE 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define FCRAM_NUM_PARTITIONS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Generic HASH entry header, used for all non-optimized formats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define HASH_HEADER_FMT 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define HASH_HEADER_EXT 0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define HASH_HEADER_VALID 0x2000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define HASH_HEADER_RESVD 0x1000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define HASH_HEADER_L2_DADDR 0x0ffffffffffff000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define HASH_HEADER_L2_DADDR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define HASH_HEADER_VLAN 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define HASH_HEADER_VLAN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Optimized format, just a header with a special layout defined below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * Set FMT and EXT both to zero to indicate this layout is being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define HASH_OPT_HEADER_FMT 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define HASH_OPT_HEADER_EXT 0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define HASH_OPT_HEADER_VALID 0x2000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define HASH_OPT_HEADER_RDCOFF 0x1f00000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define HASH_OPT_HEADER_RDCOFF_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define HASH_OPT_HEADER_HASH2 0x00ffff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define HASH_OPT_HEADER_HASH2_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define HASH_OPT_HEADER_RESVD 0x000000ff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define HASH_OPT_HEADER_USERINFO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define HASH_OPT_HEADER_USERINFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* Port and protocol word used for ipv4 and ipv6 layouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define HASH_PORT_DPORT 0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define HASH_PORT_DPORT_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define HASH_PORT_SPORT 0x0000ffff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define HASH_PORT_SPORT_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define HASH_PORT_PROTO 0x00000000ff000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define HASH_PORT_PROTO_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define HASH_PORT_PORT_OFF 0x0000000000c00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define HASH_PORT_PORT_OFF_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define HASH_PORT_PORT_RESV 0x00000000003fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* Action word used for ipv4 and ipv6 layouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define HASH_ACTION_RESV1 0xe000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define HASH_ACTION_RDCOFF 0x1f00000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define HASH_ACTION_RDCOFF_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define HASH_ACTION_ZFVALID 0x0080000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define HASH_ACTION_RESV2 0x0070000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define HASH_ACTION_ZFID 0x000fff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define HASH_ACTION_ZFID_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define HASH_ACTION_RESV3 0x000000ff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define HASH_ACTION_USERINFO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define HASH_ACTION_USERINFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* IPV4 address word. Addresses are in network endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define HASH_IP4ADDR_SADDR 0xffffffff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define HASH_IP4ADDR_SADDR_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define HASH_IP4ADDR_DADDR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define HASH_IP4ADDR_DADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* IPV6 address layout is 4 words, first two are saddr, next two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * are daddr. Addresses are in network endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct fcram_hash_opt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) u64 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* EXT=1, FMT=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct fcram_hash_ipv4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u64 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) u64 addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) u64 ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) u64 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* EXT=1, FMT=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct fcram_hash_ipv6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) u64 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) u64 addrs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) u64 ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) u64 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define HASH_TBL_DATA_LOG(IDX) (FFLP + 0x00010UL + (IDX) * 8192UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define HASH_TBL_DATA_LOG_ERR 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define HASH_TBL_DATA_LOG_ADDR 0x000000007fffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define HASH_TBL_DATA_LOG_SYNDROME 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define RX_DMA_CK_DIV (FZC_DMC + 0x00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define RX_DMA_CK_DIV_CNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define DEF_RDC_VAL 0x000000000000001fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define PT_DRR_WT_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define PT_DRR_WEIGHT_DEFAULT_10G 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define PT_DRR_WEIGHT_DEFAULT_1G 0x0066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define PT_USE_CNT 0x00000000000fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define RED_RAN_INIT (FZC_DMC + 0x00068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define RED_RAN_INIT_OPMODE 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define RED_RAN_INIT_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define RX_ADDR_MD (FZC_DMC + 0x00070UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define RX_ADDR_MD_DBG_PT_MUX_SEL 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define RX_ADDR_MD_RAM_ACC 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define RX_ADDR_MD_MODE32 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define RDMC_PRE_PAR_ERR (FZC_DMC + 0x00078UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define RDMC_PRE_PAR_ERR_ERR 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define RDMC_PRE_PAR_ERR_MERR 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define RDMC_PRE_PAR_ERR_ADDR 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define RDMC_SHA_PAR_ERR (FZC_DMC + 0x00080UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define RDMC_SHA_PAR_ERR_ERR 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define RDMC_SHA_PAR_ERR_MERR 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define RDMC_SHA_PAR_ERR_ADDR 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define RDMC_MEM_ADDR (FZC_DMC + 0x00088UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define RDMC_MEM_ADDR_PRE_SHAD 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define RDMC_MEM_ADDR_ADDR 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define RDMC_MEM_DAT0 (FZC_DMC + 0x00090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define RDMC_MEM_DAT0_DATA 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define RDMC_MEM_DAT1 (FZC_DMC + 0x00098UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define RDMC_MEM_DAT1_DATA 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define RDMC_MEM_DAT2 (FZC_DMC + 0x000a0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define RDMC_MEM_DAT2_DATA 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define RDMC_MEM_DAT3 (FZC_DMC + 0x000a8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define RDMC_MEM_DAT3_DATA 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define RDMC_MEM_DAT4 (FZC_DMC + 0x000b0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define RDMC_MEM_DAT4_DATA 0x00000000000fffffULL /* bits 147:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define RX_CTL_DAT_FIFO_STAT (FZC_DMC + 0x000b8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define RX_CTL_DAT_FIFO_STAT_ID_MISMATCH 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define RX_CTL_DAT_FIFO_MASK (FZC_DMC + 0x000c0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define RX_CTL_DAT_FIFO_MASK_ID_MISMATCH 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define RDMC_TRAINING_VECTOR (FZC_DMC + 0x000c8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define RDMC_TRAINING_VECTOR_TRAINING_VECTOR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define RX_CTL_DAT_FIFO_STAT_DBG (FZC_DMC + 0x000d0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define RDC_TBL(TBL,SLOT) (FZC_ZCP + 0x10000UL + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) (TBL) * (8UL * 16UL) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) (SLOT) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define RDC_TBL_RDC 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define RX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define RX_LOG_PAGE_VLD_FUNC_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define RX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define RX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define RX_LOG_MASK1_MASK 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define RX_LOG_VAL1_VALUE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define RX_LOG_MASK2_MASK 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define RX_LOG_VAL2_VALUE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define RX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define RX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define RX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define TX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define TX_LOG_PAGE_VLD_FUNC_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define TX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define TX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define TX_LOG_MASK1_MASK 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define TX_LOG_VAL1_VALUE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define TX_LOG_MASK2_MASK 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define TX_LOG_VAL2_VALUE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define TX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define TX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define TX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define TX_ADDR_MD (FZC_DMC + 0x45000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define TX_ADDR_MD_MODE32 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define RDC_RED_PARA_THRE_SYN 0x00000000fff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define RDC_RED_PARA_THRE_SYN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define RDC_RED_PARA_WIN_SYN 0x00000000000f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define RDC_RED_PARA_WIN_SYN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define RDC_RED_PARA_THRE 0x000000000000fff0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define RDC_RED_PARA_THRE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define RDC_RED_PARA_WIN 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define RDC_RED_PARA_WIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define RED_DIS_CNT_OFLOW 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define RED_DIS_CNT_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define IPP_CFIG (FZC_IPP + 0x00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define IPP_CFIG_SOFT_RST 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define IPP_CFIG_IP_MAX_PKT 0x0000000001ffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define IPP_CFIG_IP_MAX_PKT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define IPP_CFIG_FFLP_CS_PIO_W 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define IPP_CFIG_PFIFO_PIO_W 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define IPP_CFIG_DFIFO_PIO_W 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define IPP_CFIG_CKSUM_EN 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define IPP_CFIG_DROP_BAD_CRC 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define IPP_CFIG_DFIFO_ECC_EN 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define IPP_CFIG_DEBUG_BUS_OUT_EN 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define IPP_CFIG_IPP_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define IPP_PKT_DIS (FZC_IPP + 0x00020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define IPP_PKT_DIS_COUNT 0x0000000000003fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define IPP_BAD_CS_CNT (FZC_IPP + 0x00028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define IPP_BAD_CS_CNT_COUNT 0x0000000000003fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define IPP_ECC (FZC_IPP + 0x00030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define IPP_ECC_COUNT 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define IPP_INT_STAT (FZC_IPP + 0x00040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define IPP_INT_STAT_SOP_MISS 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define IPP_INT_STAT_EOP_MISS 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define IPP_INT_STAT_DFIFO_UE 0x0000000030000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define IPP_INT_STAT_DFIFO_CE 0x000000000c000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define IPP_INT_STAT_DFIFO_ECC 0x0000000003000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define IPP_INT_STAT_DFIFO_ECC_IDX 0x00000000007ff000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define IPP_INT_STAT_PFIFO_PERR 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define IPP_INT_STAT_ECC_ERR_MAX 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define IPP_INT_STAT_PFIFO_ERR_IDX 0x00000000000003f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define IPP_INT_STAT_PFIFO_OVER 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define IPP_INT_STAT_PFIFO_UND 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define IPP_INT_STAT_BAD_CS_MX 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define IPP_INT_STAT_PKT_DIS_MX 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define IPP_INT_STAT_ALL 0x00000000ff7fffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define IPP_MSK (FZC_IPP + 0x00048UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define IPP_MSK_ECC_ERR_MX 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define IPP_MSK_DFIFO_EOP_SOP 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define IPP_MSK_DFIFO_UC 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define IPP_MSK_PFIFO_PAR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define IPP_MSK_PFIFO_OVER 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define IPP_MSK_PFIFO_UND 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define IPP_MSK_BAD_CS 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define IPP_MSK_PKT_DIS_CNT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define IPP_MSK_ALL 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define IPP_PFIFO_RD0 (FZC_IPP + 0x00060UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define IPP_PFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define IPP_PFIFO_RD1 (FZC_IPP + 0x00068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define IPP_PFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define IPP_PFIFO_RD2 (FZC_IPP + 0x00070UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define IPP_PFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define IPP_PFIFO_RD3 (FZC_IPP + 0x00078UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define IPP_PFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define IPP_PFIFO_RD4 (FZC_IPP + 0x00080UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define IPP_PFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define IPP_PFIFO_WR0 (FZC_IPP + 0x00088UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define IPP_PFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define IPP_PFIFO_WR1 (FZC_IPP + 0x00090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define IPP_PFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define IPP_PFIFO_WR2 (FZC_IPP + 0x00098UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define IPP_PFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define IPP_PFIFO_WR3 (FZC_IPP + 0x000a0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define IPP_PFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define IPP_PFIFO_WR4 (FZC_IPP + 0x000a8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define IPP_PFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define IPP_PFIFO_RD_PTR (FZC_IPP + 0x000b0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define IPP_PFIFO_RD_PTR_PTR 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define IPP_PFIFO_WR_PTR (FZC_IPP + 0x000b8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define IPP_PFIFO_WR_PTR_PTR 0x000000000000007fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define IPP_DFIFO_RD0 (FZC_IPP + 0x000c0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define IPP_DFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define IPP_DFIFO_RD1 (FZC_IPP + 0x000c8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define IPP_DFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define IPP_DFIFO_RD2 (FZC_IPP + 0x000d0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define IPP_DFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define IPP_DFIFO_RD3 (FZC_IPP + 0x000d8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define IPP_DFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define IPP_DFIFO_RD4 (FZC_IPP + 0x000e0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define IPP_DFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define IPP_DFIFO_WR0 (FZC_IPP + 0x000e8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define IPP_DFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define IPP_DFIFO_WR1 (FZC_IPP + 0x000f0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define IPP_DFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define IPP_DFIFO_WR2 (FZC_IPP + 0x000f8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define IPP_DFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define IPP_DFIFO_WR3 (FZC_IPP + 0x00100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define IPP_DFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define IPP_DFIFO_WR4 (FZC_IPP + 0x00108UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define IPP_DFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define IPP_DFIFO_RD_PTR (FZC_IPP + 0x00110UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define IPP_DFIFO_RD_PTR_PTR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define IPP_DFIFO_WR_PTR (FZC_IPP + 0x00118UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define IPP_DFIFO_WR_PTR_PTR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define IPP_SM (FZC_IPP + 0x00120UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define IPP_SM_SM 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define IPP_CS_STAT (FZC_IPP + 0x00128UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define IPP_CS_STAT_BCYC_CNT 0x00000000ff000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define IPP_CS_STAT_IP_LEN 0x0000000000fff000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define IPP_CS_STAT_CS_FAIL 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define IPP_CS_STAT_TERM 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define IPP_CS_STAT_BAD_NUM 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define IPP_CS_STAT_CS_STATE 0x00000000000001ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define IPP_FFLP_CS_INFO (FZC_IPP + 0x00130UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define IPP_FFLP_CS_INFO_PKT_ID 0x0000000000003c00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define IPP_FFLP_CS_INFO_L4_PROTO 0x0000000000000300ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define IPP_FFLP_CS_INFO_V4_HD_LEN 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define IPP_FFLP_CS_INFO_L3_VER 0x000000000000000cULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define IPP_FFLP_CS_INFO_L2_OP 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define IPP_DBG_SEL (FZC_IPP + 0x00138UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define IPP_DBG_SEL_SEL 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define IPP_DFIFO_ECC_SYND (FZC_IPP + 0x00140UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define IPP_DFIFO_ECC_SYND_SYND 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define IPP_DFIFO_EOP_RD_PTR (FZC_IPP + 0x00148UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define IPP_DFIFO_EOP_RD_PTR_PTR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define IPP_ECC_CTL (FZC_IPP + 0x00150UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define IPP_ECC_CTL_DIS_DBL 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define IPP_ECC_CTL_COR_DBL 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define IPP_ECC_CTL_COR_SNG 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define IPP_ECC_CTL_COR_ALL 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define IPP_ECC_CTL_COR_1 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define IPP_ECC_CTL_COR_LST 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define IPP_ECC_CTL_COR_SND 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define IPP_ECC_CTL_COR_FSR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define NIU_DFIFO_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define ATLAS_P0_P1_DFIFO_ENTRIES 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define ATLAS_P2_P3_DFIFO_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define ZCP_CFIG (FZC_ZCP + 0x00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define ZCP_CFIG_ZCP_32BIT_MODE 0x0000000001000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define ZCP_CFIG_ZCP_DEBUG_SEL 0x0000000000ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define ZCP_CFIG_DMA_TH 0x000000000000ffe0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define ZCP_CFIG_ECC_CHK_DIS 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define ZCP_CFIG_PAR_CHK_DIS 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define ZCP_CFIG_DIS_BUFF_RSP_IF 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define ZCP_CFIG_DIS_BUFF_REQ_IF 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define ZCP_CFIG_ZC_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define ZCP_INT_STAT (FZC_ZCP + 0x00008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define ZCP_INT_STAT_RRFIFO_UNDERRUN 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define ZCP_INT_STAT_RRFIFO_OVERRUN 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define ZCP_INT_STAT_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define ZCP_INT_STAT_BUFFER_OVERFLOW 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define ZCP_INT_STAT_STAT_TBL_PERR 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define ZCP_INT_STAT_DYN_TBL_PERR 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define ZCP_INT_STAT_BUF_TBL_PERR 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define ZCP_INT_STAT_TT_PROGRAM_ERR 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define ZCP_INT_STAT_RSP_TT_INDEX_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define ZCP_INT_STAT_SLV_TT_INDEX_ERR 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define ZCP_INT_STAT_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define ZCP_INT_STAT_CFIFO_ECC3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define ZCP_INT_STAT_CFIFO_ECC2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define ZCP_INT_STAT_CFIFO_ECC1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define ZCP_INT_STAT_CFIFO_ECC0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define ZCP_INT_STAT_ALL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define ZCP_INT_MASK (FZC_ZCP + 0x00010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define ZCP_INT_MASK_RRFIFO_UNDERRUN 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define ZCP_INT_MASK_RRFIFO_OVERRUN 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define ZCP_INT_MASK_LOJ 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define ZCP_INT_MASK_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define ZCP_INT_MASK_BUFFER_OVERFLOW 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define ZCP_INT_MASK_STAT_TBL_PERR 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define ZCP_INT_MASK_DYN_TBL_PERR 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define ZCP_INT_MASK_BUF_TBL_PERR 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define ZCP_INT_MASK_TT_PROGRAM_ERR 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define ZCP_INT_MASK_RSP_TT_INDEX_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define ZCP_INT_MASK_SLV_TT_INDEX_ERR 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define ZCP_INT_MASK_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define ZCP_INT_MASK_CFIFO_ECC3 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define ZCP_INT_MASK_CFIFO_ECC2 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define ZCP_INT_MASK_CFIFO_ECC1 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define ZCP_INT_MASK_CFIFO_ECC0 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define ZCP_INT_MASK_ALL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define BAM4BUF (FZC_ZCP + 0x00018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define BAM4BUF_LOJ 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define BAM4BUF_EN_CK 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define BAM4BUF_IDX_END0 0x000000003ff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define BAM4BUF_IDX_ST0 0x00000000000ffc00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define BAM4BUF_OFFSET0 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define BAM8BUF (FZC_ZCP + 0x00020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define BAM8BUF_LOJ 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define BAM8BUF_EN_CK 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define BAM8BUF_IDX_END1 0x000000003ff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define BAM8BUF_IDX_ST1 0x00000000000ffc00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define BAM8BUF_OFFSET1 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define BAM16BUF (FZC_ZCP + 0x00028UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define BAM16BUF_LOJ 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define BAM16BUF_EN_CK 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define BAM16BUF_IDX_END2 0x000000003ff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define BAM16BUF_IDX_ST2 0x00000000000ffc00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define BAM16BUF_OFFSET2 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define BAM32BUF (FZC_ZCP + 0x00030UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define BAM32BUF_LOJ 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define BAM32BUF_EN_CK 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define BAM32BUF_IDX_END3 0x000000003ff00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define BAM32BUF_IDX_ST3 0x00000000000ffc00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define BAM32BUF_OFFSET3 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define DST4BUF (FZC_ZCP + 0x00038UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define DST4BUF_DS_OFFSET0 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define DST8BUF (FZC_ZCP + 0x00040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define DST8BUF_DS_OFFSET1 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define DST16BUF (FZC_ZCP + 0x00048UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define DST16BUF_DS_OFFSET2 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define DST32BUF (FZC_ZCP + 0x00050UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define DST32BUF_DS_OFFSET3 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define ZCP_RAM_DATA0 (FZC_ZCP + 0x00058UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define ZCP_RAM_DATA0_DAT0 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define ZCP_RAM_DATA1 (FZC_ZCP + 0x00060UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define ZCP_RAM_DAT10_DAT1 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define ZCP_RAM_DATA2 (FZC_ZCP + 0x00068UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define ZCP_RAM_DATA2_DAT2 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define ZCP_RAM_DATA3 (FZC_ZCP + 0x00070UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define ZCP_RAM_DATA3_DAT3 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define ZCP_RAM_DATA4 (FZC_ZCP + 0x00078UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define ZCP_RAM_DATA4_DAT4 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define ZCP_RAM_BE (FZC_ZCP + 0x00080UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define ZCP_RAM_BE_VAL 0x000000000001ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define ZCP_RAM_ACC (FZC_ZCP + 0x00088UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define ZCP_RAM_ACC_BUSY 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define ZCP_RAM_ACC_READ 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define ZCP_RAM_ACC_WRITE 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define ZCP_RAM_ACC_LOJ 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define ZCP_RAM_ACC_ZFCID 0x000000001ffe0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define ZCP_RAM_ACC_ZFCID_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define ZCP_RAM_ACC_RAM_SEL 0x000000000001f000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define ZCP_RAM_ACC_RAM_SEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define ZCP_RAM_ACC_CFIFOADDR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define ZCP_RAM_ACC_CFIFOADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define ZCP_RAM_SEL_BAM(INDEX) (0x00 + (INDEX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define ZCP_RAM_SEL_TT_STATIC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define ZCP_RAM_SEL_TT_DYNAMIC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define ZCP_RAM_SEL_CFIFO(PORT) (0x10 + (PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define NIU_CFIFO_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define ATLAS_P0_P1_CFIFO_ENTRIES 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define ATLAS_P2_P3_CFIFO_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define CHK_BIT_DATA (FZC_ZCP + 0x00090UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define CHK_BIT_DATA_DATA 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define RESET_CFIFO (FZC_ZCP + 0x00098UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define RESET_CFIFO_RST(PORT) (0x1 << (PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define CFIFO_ECC(PORT) (FZC_ZCP + 0x000a0UL + (PORT) * 8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define CFIFO_ECC_DIS_DBLBIT_ERR 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define CFIFO_ECC_DBLBIT_ERR 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define CFIFO_ECC_SINGLEBIT_ERR 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define CFIFO_ECC_ALL_PKT 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define CFIFO_ECC_LAST_LINE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define CFIFO_ECC_2ND_LINE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define CFIFO_ECC_1ST_LINE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define ZCP_TRAINING_VECTOR (FZC_ZCP + 0x000c0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define ZCP_TRAINING_VECTOR_VECTOR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define ZCP_STATE_MACHINE (FZC_ZCP + 0x000c8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define ZCP_STATE_MACHINE_SM 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* Same bits as ZCP_INT_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define ZCP_INT_STAT_TEST (FZC_ZCP + 0x00108UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define RXDMA_CFIG1_EN 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define RXDMA_CFIG1_RST 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define RXDMA_CFIG1_QST 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define RXDMA_CFIG1_MBADDR_H 0x0000000000000fffULL /* mboxaddr 43:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define RXDMA_CFIG2_MBADDR_L 0x00000000ffffffc0ULL /* mboxaddr 31:6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define RXDMA_CFIG2_OFFSET 0x0000000000000006ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define RXDMA_CFIG2_OFFSET_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define RBR_CFIG_A_LEN 0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define RBR_CFIG_A_LEN_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define RBR_CFIG_A_STADDR_BASE 0x00000ffffffc0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define RBR_CFIG_A_STADDR 0x000000000003ffc0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define RBR_CFIG_B_BLKSIZE 0x0000000003000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define RBR_CFIG_B_BLKSIZE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define RBR_CFIG_B_VLD2 0x0000000000800000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define RBR_CFIG_B_BUFSZ2 0x0000000000030000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define RBR_CFIG_B_BUFSZ2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define RBR_CFIG_B_VLD1 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define RBR_CFIG_B_BUFSZ1 0x0000000000000300ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define RBR_CFIG_B_BUFSZ1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define RBR_CFIG_B_VLD0 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define RBR_CFIG_B_BUFSZ0 0x0000000000000003ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define RBR_CFIG_B_BUFSZ0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define RBR_BLKSIZE_4K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #define RBR_BLKSIZE_8K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define RBR_BLKSIZE_16K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define RBR_BLKSIZE_32K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define RBR_BUFSZ2_2K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define RBR_BUFSZ2_4K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define RBR_BUFSZ2_8K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define RBR_BUFSZ2_16K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define RBR_BUFSZ1_1K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define RBR_BUFSZ1_2K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #define RBR_BUFSZ1_4K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #define RBR_BUFSZ1_8K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define RBR_BUFSZ0_256 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define RBR_BUFSZ0_512 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define RBR_BUFSZ0_1K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define RBR_BUFSZ0_2K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define RBR_KICK_BKADD 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define RBR_STAT_QLEN 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define RBR_HDH_HEAD_H 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define RBR_HDL_HEAD_L 0x00000000fffffffcULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define RCRCFIG_A_LEN 0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define RCRCFIG_A_LEN_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define RCRCFIG_A_STADDR_BASE 0x00000ffffff80000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define RCRCFIG_A_STADDR 0x000000000007ffc0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define RCRCFIG_B_PTHRES 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define RCRCFIG_B_PTHRES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #define RCRCFIG_B_ENTOUT 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #define RCRCFIG_B_TIMEOUT 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define RCRCFIG_B_TIMEOUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define RCRSTAT_A_QLEN 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define RCRSTAT_B_TIPTR_H 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define RCRSTAT_C_TIPTR_L 0x00000000fffffff8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define RX_DMA_CTL_STAT_RCRSHADOW_FULL 0x0000008000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define RX_DMA_CTL_STAT_RBR_EMPTY 0x0000000800000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define RX_DMA_CTL_STAT_RBRLOGPAGE 0x0000000200000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define RX_DMA_CTL_STAT_CFIGLOGPAGE 0x0000000100000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define RX_DMA_CTL_STAT_PTRREAD 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define RX_DMA_CTL_STAT_PKTREAD 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define RX_DMA_CTL_STAT_CHAN_FATAL (RX_DMA_CTL_STAT_RBR_TMOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) RX_DMA_CTL_STAT_RSP_CNT_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) RX_DMA_CTL_STAT_BYTE_EN_BUS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) RX_DMA_CTL_STAT_RSP_DAT_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) RX_DMA_CTL_STAT_RCR_ACK_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) RX_DMA_CTL_STAT_RCR_SHA_PAR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) RX_DMA_CTL_STAT_RBR_PRE_PAR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) RX_DMA_CTL_STAT_CONFIG_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) RX_DMA_CTL_STAT_RCRINCON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) RX_DMA_CTL_STAT_RCRFULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) RX_DMA_CTL_STAT_RBRFULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) RX_DMA_CTL_STAT_RBRLOGPAGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) RX_DMA_CTL_STAT_CFIGLOGPAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define RX_DMA_CTL_STAT_PORT_FATAL (RX_DMA_CTL_STAT_DC_FIFO_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define RX_DMA_CTL_WRITE_CLEAR_ERRS (RX_DMA_CTL_STAT_RBR_EMPTY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) RX_DMA_CTL_STAT_RCRSHADOW_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) RX_DMA_CTL_STAT_RBR_PRE_EMTY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) RX_DMA_CTL_STAT_WRED_DROP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) RX_DMA_CTL_STAT_PORT_DROP_PKT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) RX_DMA_CTL_STAT_RCRTO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) RX_DMA_CTL_STAT_RCRTHRES | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) RX_DMA_CTL_STAT_DC_FIFO_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define RCR_FLSH_FLSH 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define RXMISC_OFLOW 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define RXMISC_COUNT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #define RX_DMA_CTL_STAT_DBG_RBR_TMOUT 0x0020000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR 0x0010000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS 0x0008000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR 0x0004000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR 0x0002000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR 0x0001000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define RX_DMA_CTL_STAT_DBG_MEX 0x0000800000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define RX_DMA_CTL_STAT_DBG_RCRTHRES 0x0000400000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define RX_DMA_CTL_STAT_DBG_RCRTO 0x0000200000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR 0x0000100000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR 0x0000080000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT 0x0000040000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define RX_DMA_CTL_STAT_DBG_WRED_DROP 0x0000020000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY 0x0000010000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #define RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL 0x0000008000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define RX_DMA_CTL_STAT_DBG_CONFIG_ERR 0x0000004000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define RX_DMA_CTL_STAT_DBG_RCRINCON 0x0000002000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define RX_DMA_CTL_STAT_DBG_RCRFULL 0x0000001000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define RX_DMA_CTL_STAT_DBG_RBR_EMPTY 0x0000000800000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define RX_DMA_CTL_STAT_DBG_RBRFULL 0x0000000400000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define RX_DMA_CTL_STAT_DBG_RBRLOGPAGE 0x0000000200000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE 0x0000000100000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define RX_DMA_CTL_STAT_DBG_PTRREAD 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define RX_DMA_CTL_STAT_DBG_PKTREAD 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define RX_DMA_ENT_MSK_RBR_TMOUT 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define RX_DMA_ENT_MSK_RSP_CNT_ERR 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define RX_DMA_ENT_MSK_BYTE_EN_BUS 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define RX_DMA_ENT_MSK_RSP_DAT_ERR 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define RX_DMA_ENT_MSK_RCR_ACK_ERR 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define RX_DMA_ENT_MSK_DC_FIFO_ERR 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #define RX_DMA_ENT_MSK_RCRTHRES 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define RX_DMA_ENT_MSK_RCRTO 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define RX_DMA_ENT_MSK_RCR_SHA_PAR 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define RX_DMA_ENT_MSK_RBR_PRE_PAR 0x0000000000000800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define RX_DMA_ENT_MSK_PORT_DROP_PKT 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define RX_DMA_ENT_MSK_WRED_DROP 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define RX_DMA_ENT_MSK_RBR_PRE_EMTY 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define RX_DMA_ENT_MSK_CONFIG_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define RX_DMA_ENT_MSK_RCRINCON 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define RX_DMA_ENT_MSK_RCRFULL 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define RX_DMA_ENT_MSK_RBR_EMPTY 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define RX_DMA_ENT_MSK_RBRFULL 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define RX_DMA_ENT_MSK_RBRLOGPAGE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define RX_DMA_ENT_MSK_CFIGLOGPAGE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define RX_DMA_ENT_MSK_ALL 0x00000000003f7fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define TX_RNG_CFIG_LEN 0x1fff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define TX_RNG_CFIG_LEN_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define TX_RNG_CFIG_STADDR_BASE 0x00000ffffff80000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define TX_RNG_CFIG_STADDR 0x000000000007ffc0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define TX_RING_HDL_WRAP 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define TX_RING_HDL_HEAD 0x000000000007fff8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define TX_RING_HDL_HEAD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define TX_RING_KICK_WRAP 0x0000000000080000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define TX_RING_KICK_TAIL 0x000000000007fff8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) #define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define TX_ENT_MSK_MK 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define TX_ENT_MSK_MBOX_ERR 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define TX_ENT_MSK_PKT_SIZE_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define TX_ENT_MSK_TX_RING_OFLOW 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define TX_ENT_MSK_PREF_BUF_ECC_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define TX_ENT_MSK_NACK_PREF 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define TX_ENT_MSK_NACK_PKT_RD 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define TX_ENT_MSK_CONF_PART_ERR 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define TX_ENT_MSK_PKT_PRT_ERR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) #define TX_CS_PKT_CNT 0x0fff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define TX_CS_PKT_CNT_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define TX_CS_LASTMARK 0x00000fff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define TX_CS_LASTMARK_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #define TX_CS_RST 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define TX_CS_RST_STATE 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define TX_CS_MB 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #define TX_CS_STOP_N_GO 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define TX_CS_SNG_STATE 0x0000000008000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define TX_CS_MK 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #define TX_CS_MMK 0x0000000000004000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #define TX_CS_MBOX_ERR 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define TX_CS_PKT_SIZE_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define TX_CS_TX_RING_OFLOW 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define TX_CS_PREF_BUF_PAR_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #define TX_CS_NACK_PREF 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define TX_CS_NACK_PKT_RD 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #define TX_CS_CONF_PART_ERR 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define TX_CS_PKT_PRT_ERR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define TXDMA_MBH_MBADDR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #define TXDMA_MBL_MBADDR 0x00000000ffffffc0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) #define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) #define TX_DMA_PRE_ST_SHADOW_HD 0x000000000007ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define TX_RNG_ERR_LOGH_ERR 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define TX_RNG_ERR_LOGH_MERR 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define TX_RNG_ERR_LOGH_ERRCODE 0x0000000038000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define TX_RNG_ERR_LOGH_ERRADDR 0x0000000000000fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define TX_RNG_ERR_LOGL_ERRADDR 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define TDMC_INTR_DBG_MK 0x0000000000008000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define TDMC_INTR_DBG_MBOX_ERR 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define TDMC_INTR_DBG_PKT_SIZE_ERR 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define TDMC_INTR_DBG_TX_RING_OFLOW 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define TDMC_INTR_DBG_PREF_BUF_PAR_ERR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define TDMC_INTR_DBG_NACK_PREF 0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define TDMC_INTR_DBG_NACK_PKT_RD 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define TDMC_INTR_DBG_CONF_PART_ERR 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define TDMC_INTR_DBG_PKT_PART_ERR 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define TX_CS_DBG_PKT_CNT 0x0fff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) #define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define TDMC_INJ_PAR_ERR_VAL 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define TDMC_DBG_SEL_DBG_SEL 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define TDMC_TRAINING_VECTOR_VEC 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #define TXC_DMA_MAX(CHAN) (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #define TXC_DMA_MAX_LEN(CHAN) (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #define TXC_CONTROL (FZC_TXC + 0x20000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define TXC_CONTROL_ENABLE 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define TXC_CONTROL_PORT_ENABLE(X) (1 << (X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #define TXC_TRAINING_VEC (FZC_TXC + 0x20008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #define TXC_TRAINING_VEC_MASK 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define TXC_DEBUG (FZC_TXC + 0x20010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) #define TXC_DEBUG_SELECT 0x000000000000003fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define TXC_MAX_REORDER (FZC_TXC + 0x20018UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #define TXC_MAX_REORDER_PORT3 0x000000000f000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #define TXC_MAX_REORDER_PORT2 0x00000000000f0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define TXC_MAX_REORDER_PORT1 0x0000000000000f00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define TXC_MAX_REORDER_PORT0 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define TXC_PORT_CTL(PORT) (FZC_TXC + 0x20020UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define TXC_PORT_CTL_CLR_ALL_STAT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define TXC_PKT_STUFFED(PORT) (FZC_TXC + 0x20030UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define TXC_PKT_STUFFED_PP_REORDER 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define TXC_PKT_STUFFED_PP_PACKETASSY 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define TXC_PKT_XMIT(PORT) (FZC_TXC + 0x20038UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define TXC_PKT_XMIT_BYTES 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define TXC_PKT_XMIT_PKTS 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define TXC_ROECC_CTL(PORT) (FZC_TXC + 0x20040UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define TXC_ROECC_CTL_DISABLE_UE 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define TXC_ROECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define TXC_ROECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define TXC_ROECC_CTL_ALL_PKTS 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define TXC_ROECC_CTL_ALT_PKTS 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define TXC_ROECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define TXC_ROECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define TXC_ROECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) #define TXC_ROECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #define TXC_ROECC_ST(PORT) (FZC_TXC + 0x20048UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define TXC_ROECC_CLR_ST 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #define TXC_ROECC_CE 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define TXC_ROECC_UE 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define TXC_ROECC_ST_ECC_ADDR 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define TXC_RO_DATA0(PORT) (FZC_TXC + 0x20050UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define TXC_RO_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) #define TXC_RO_DATA1(PORT) (FZC_TXC + 0x20058UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) #define TXC_RO_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) #define TXC_RO_DATA2(PORT) (FZC_TXC + 0x20060UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #define TXC_RO_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) #define TXC_RO_DATA3(PORT) (FZC_TXC + 0x20068UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #define TXC_RO_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) #define TXC_RO_DATA4(PORT) (FZC_TXC + 0x20070UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) #define TXC_RO_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) #define TXC_SFECC_CTL(PORT) (FZC_TXC + 0x20078UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #define TXC_SFECC_CTL_DISABLE_UE 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #define TXC_SFECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #define TXC_SFECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) #define TXC_SFECC_CTL_ALL_PKTS 0x0000000000000400ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) #define TXC_SFECC_CTL_ALT_PKTS 0x0000000000000200ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) #define TXC_SFECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #define TXC_SFECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define TXC_SFECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #define TXC_SFECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #define TXC_SFECC_ST(PORT) (FZC_TXC + 0x20080UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #define TXC_SFECC_ST_CLR_ST 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #define TXC_SFECC_ST_CE 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #define TXC_SFECC_ST_UE 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) #define TXC_SFECC_ST_ECC_ADDR 0x00000000000003ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define TXC_SF_DATA0(PORT) (FZC_TXC + 0x20088UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define TXC_SF_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) #define TXC_SF_DATA1(PORT) (FZC_TXC + 0x20090UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) #define TXC_SF_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #define TXC_SF_DATA2(PORT) (FZC_TXC + 0x20098UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #define TXC_SF_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define TXC_SF_DATA3(PORT) (FZC_TXC + 0x200a0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #define TXC_SF_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) #define TXC_SF_DATA4(PORT) (FZC_TXC + 0x200a8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) #define TXC_SF_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define TXC_RO_TIDS(PORT) (FZC_TXC + 0x200b0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define TXC_RO_TIDS_IN_USE 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define TXC_RO_STATE0(PORT) (FZC_TXC + 0x200b8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define TXC_RO_STATE0_DUPLICATE_TID 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define TXC_RO_STATE1(PORT) (FZC_TXC + 0x200c0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define TXC_RO_STATE1_UNUSED_TID 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define TXC_RO_STATE2(PORT) (FZC_TXC + 0x200c8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define TXC_RO_STATE2_TRANS_TIMEOUT 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #define TXC_RO_STATE3(PORT) (FZC_TXC + 0x200d0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) #define TXC_RO_STATE3_ENAB_SPC_WMARK 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #define TXC_RO_STATE3_RO_SPC_WMARK 0x000000007fe00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #define TXC_RO_STATE3_ROFIFO_SPC_AVAIL 0x00000000001ff800ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define TXC_RO_STATE3_ENAB_RO_WMARK 0x0000000000000100ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #define TXC_RO_STATE3_HIGH_RO_USED 0x00000000000000f0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) #define TXC_RO_STATE3_NUM_RO_USED 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #define TXC_RO_CTL(PORT) (FZC_TXC + 0x200d8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) #define TXC_RO_CTL_CLR_FAIL_STATE 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #define TXC_RO_CTL_RO_ADDR 0x000000000f000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #define TXC_RO_CTL_ADDR_FAILED 0x0000000000400000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define TXC_RO_CTL_DMA_FAILED 0x0000000000200000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define TXC_RO_CTL_LEN_FAILED 0x0000000000100000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define TXC_RO_CTL_CAPT_ADDR_FAILED 0x0000000000040000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #define TXC_RO_CTL_CAPT_DMA_FAILED 0x0000000000020000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #define TXC_RO_CTL_CAPT_LEN_FAILED 0x0000000000010000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define TXC_RO_CTL_RO_STATE_RD_DONE 0x0000000000000080ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #define TXC_RO_CTL_RO_STATE_WR_DONE 0x0000000000000040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #define TXC_RO_CTL_RO_STATE_RD 0x0000000000000020ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) #define TXC_RO_CTL_RO_STATE_WR 0x0000000000000010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #define TXC_RO_CTL_RO_STATE_ADDR 0x000000000000000fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) #define TXC_RO_ST_DATA0(PORT) (FZC_TXC + 0x200e0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) #define TXC_RO_ST_DATA0_DATA0 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) #define TXC_RO_ST_DATA1(PORT) (FZC_TXC + 0x200e8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) #define TXC_RO_ST_DATA1_DATA1 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) #define TXC_RO_ST_DATA2(PORT) (FZC_TXC + 0x200f0UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) #define TXC_RO_ST_DATA2_DATA2 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) #define TXC_RO_ST_DATA3(PORT) (FZC_TXC + 0x200f8UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) #define TXC_RO_ST_DATA3_DATA3 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) #define TXC_PORT_PACKET_REQ(PORT) (FZC_TXC + 0x20100UL + (PORT)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) #define TXC_PORT_PACKET_REQ_GATHER_REQ 0x00000000f0000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #define TXC_PORT_PACKET_REQ_PKT_REQ 0x000000000fff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) #define TXC_PORT_PACKET_REQ_PERR_ABRT 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /* bits are same as TXC_INT_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) #define TXC_INT_STAT_DBG (FZC_TXC + 0x20420UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) #define TXC_INT_STAT (FZC_TXC + 0x20428UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #define TXC_INT_STAT_VAL_SHIFT(PORT) ((PORT) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) #define TXC_INT_STAT_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) #define TXC_INT_STAT_SF_CE(PORT) (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #define TXC_INT_STAT_SF_UE(PORT) (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) #define TXC_INT_STAT_RO_CE(PORT) (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #define TXC_INT_STAT_RO_UE(PORT) (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #define TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) #define TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #define TXC_INT_MASK (FZC_TXC + 0x20430UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) #define TXC_INT_MASK_VAL_SHIFT(PORT) ((PORT) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #define TXC_INT_MASK_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) #define TXC_INT_MASK_SF_CE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) #define TXC_INT_MASK_SF_UE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) #define TXC_INT_MASK_RO_CE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #define TXC_INT_MASK_RO_UE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) #define TXC_INT_MASK_REORDER_ERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) #define TXC_INT_MASK_PKTASM_DEAD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #define TXC_INT_MASK_ALL 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) #define TXC_PORT_DMA(IDX) (FZC_TXC + 0x20028UL + (IDX)*0x100UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) #define ESPC_PIO_EN (FZC_PROM + 0x40000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #define ESPC_PIO_EN_ENABLE 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define ESPC_PIO_STAT (FZC_PROM + 0x40008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) #define ESPC_PIO_STAT_READ_START 0x0000000080000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #define ESPC_PIO_STAT_READ_END 0x0000000040000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) #define ESPC_PIO_STAT_WRITE_INIT 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) #define ESPC_PIO_STAT_WRITE_END 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define ESPC_PIO_STAT_ADDR 0x0000000003ffff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define ESPC_PIO_STAT_ADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define ESPC_PIO_STAT_DATA 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define ESPC_PIO_STAT_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #define ESPC_NCR(IDX) (FZC_PROM + 0x40020UL + (IDX)*0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #define ESPC_NCR_VAL 0x00000000ffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #define ESPC_MAC_ADDR0 ESPC_NCR(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) #define ESPC_MAC_ADDR1 ESPC_NCR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) #define ESPC_NUM_PORTS_MACS ESPC_NCR(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) #define ESPC_NUM_PORTS_MACS_VAL 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #define ESPC_MOD_STR_LEN ESPC_NCR(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) #define ESPC_MOD_STR_1 ESPC_NCR(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #define ESPC_MOD_STR_2 ESPC_NCR(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) #define ESPC_MOD_STR_3 ESPC_NCR(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) #define ESPC_MOD_STR_4 ESPC_NCR(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) #define ESPC_MOD_STR_5 ESPC_NCR(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) #define ESPC_MOD_STR_6 ESPC_NCR(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) #define ESPC_MOD_STR_7 ESPC_NCR(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) #define ESPC_MOD_STR_8 ESPC_NCR(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #define ESPC_BD_MOD_STR_LEN ESPC_NCR(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) #define ESPC_BD_MOD_STR_1 ESPC_NCR(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) #define ESPC_BD_MOD_STR_2 ESPC_NCR(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) #define ESPC_BD_MOD_STR_3 ESPC_NCR(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) #define ESPC_BD_MOD_STR_4 ESPC_NCR(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #define ESPC_PHY_TYPE ESPC_NCR(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) #define ESPC_PHY_TYPE_PORT0 0x00000000ff000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) #define ESPC_PHY_TYPE_PORT0_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #define ESPC_PHY_TYPE_PORT1 0x0000000000ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) #define ESPC_PHY_TYPE_PORT1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #define ESPC_PHY_TYPE_PORT2 0x000000000000ff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) #define ESPC_PHY_TYPE_PORT2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) #define ESPC_PHY_TYPE_PORT3 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #define ESPC_PHY_TYPE_PORT3_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #define ESPC_PHY_TYPE_1G_COPPER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #define ESPC_PHY_TYPE_1G_FIBER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define ESPC_PHY_TYPE_10G_COPPER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define ESPC_PHY_TYPE_10G_FIBER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define ESPC_MAX_FM_SZ ESPC_NCR(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define ESPC_INTR_NUM ESPC_NCR(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define ESPC_INTR_NUM_PORT0 0x00000000ff000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) #define ESPC_INTR_NUM_PORT1 0x0000000000ff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #define ESPC_INTR_NUM_PORT2 0x000000000000ff00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define ESPC_INTR_NUM_PORT3 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define ESPC_VER_IMGSZ ESPC_NCR(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #define ESPC_VER_IMGSZ_IMGSZ 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) #define ESPC_VER_IMGSZ_IMGSZ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define ESPC_VER_IMGSZ_VER 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define ESPC_VER_IMGSZ_VER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #define ESPC_CHKSUM ESPC_NCR(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #define ESPC_CHKSUM_SUM 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #define ESPC_EEPROM_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define CLASS_CODE_UNRECOG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define CLASS_CODE_DUMMY1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) #define CLASS_CODE_ETHERTYPE1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) #define CLASS_CODE_ETHERTYPE2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define CLASS_CODE_USER_PROG1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #define CLASS_CODE_USER_PROG2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define CLASS_CODE_USER_PROG3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define CLASS_CODE_USER_PROG4 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) #define CLASS_CODE_TCP_IPV4 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) #define CLASS_CODE_UDP_IPV4 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) #define CLASS_CODE_AH_ESP_IPV4 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #define CLASS_CODE_SCTP_IPV4 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) #define CLASS_CODE_TCP_IPV6 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) #define CLASS_CODE_UDP_IPV6 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) #define CLASS_CODE_AH_ESP_IPV6 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) #define CLASS_CODE_SCTP_IPV6 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) #define CLASS_CODE_ARP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) #define CLASS_CODE_RARP 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #define CLASS_CODE_DUMMY2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #define CLASS_CODE_DUMMY3 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) #define CLASS_CODE_DUMMY4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #define CLASS_CODE_DUMMY5 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #define CLASS_CODE_DUMMY6 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) #define CLASS_CODE_DUMMY7 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #define CLASS_CODE_DUMMY8 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) #define CLASS_CODE_DUMMY9 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #define CLASS_CODE_DUMMY10 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) #define CLASS_CODE_DUMMY11 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) #define CLASS_CODE_DUMMY12 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #define CLASS_CODE_DUMMY13 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #define CLASS_CODE_DUMMY14 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #define CLASS_CODE_DUMMY15 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) /* Logical devices and device groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) #define LDN_RXDMA(CHAN) (0 + (CHAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define LDN_RESV1(OFF) (16 + (OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #define LDN_TXDMA(CHAN) (32 + (CHAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #define LDN_RESV2(OFF) (56 + (OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) #define LDN_MIF 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) #define LDN_MAC(PORT) (64 + (PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) #define LDN_DEVICE_ERROR 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #define LDN_MAX LDN_DEVICE_ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) #define NIU_LDG_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) #define NIU_LDG_MAX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) #define NIU_NUM_LDG 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #define LDG_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* PHY stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define NIU_PMA_PMD_DEV_ADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define NIU_PCS_DEV_ADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define NIU_PHY_ID_MASK 0xfffff0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define NIU_PHY_ID_BCM8704 0x00206030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define NIU_PHY_ID_BCM8706 0x00206035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) #define NIU_PHY_ID_BCM5464R 0x002060b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) #define NIU_PHY_ID_MRVL88X2011 0x01410020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* MRVL88X2011 register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define MRVL88X2011_USER_DEV1_ADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) #define MRVL88X2011_USER_DEV2_ADDR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define MRVL88X2011_USER_DEV3_ADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #define MRVL88X2011_USER_DEV4_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define MRVL88X2011_PMA_PMD_CTL_1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) #define MRVL88X2011_PMA_PMD_STATUS_1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define MRVL88X2011_10G_PMD_STATUS_2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define MRVL88X2011_10G_PMD_TX_DIS 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define MRVL88X2011_10G_XGXS_LANE_STAT 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #define MRVL88X2011_GENERAL_CTL 0x8300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define MRVL88X2011_LED_BLINK_CTL 0x8303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define MRVL88X2011_LED_8_TO_11_CTL 0x8306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* MRVL88X2011 register control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define MRVL88X2011_ENA_XFPREFCLK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) #define MRVL88X2011_ENA_PMDTX 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define MRVL88X2011_LOOPBACK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #define MRVL88X2011_LED_ACT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) #define MRVL88X2011_LNK_STATUS_OK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) #define MRVL88X2011_LED_BLKRATE_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define MRVL88X2011_LED_BLKRATE_034MS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #define MRVL88X2011_LED_BLKRATE_067MS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #define MRVL88X2011_LED_BLKRATE_134MS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) #define MRVL88X2011_LED_BLKRATE_269MS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #define MRVL88X2011_LED_BLKRATE_538MS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define MRVL88X2011_LED_CTL_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define MRVL88X2011_LED_CTL_PCS_ACT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define MRVL88X2011_LED_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #define MRVL88X2011_LED(n,v) ((v)<<((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) #define MRVL88X2011_LED_STAT(n,v) ((v)>>((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #define BCM8704_PMA_PMD_DEV_ADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) #define BCM8704_PCS_DEV_ADDR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) #define BCM8704_USER_DEV3_ADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define BCM8704_PHYXS_DEV_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #define BCM8704_USER_DEV4_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #define BCM8704_PMD_RCV_SIGDET 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) #define PMD_RCV_SIGDET_LANE3 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #define PMD_RCV_SIGDET_LANE2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) #define PMD_RCV_SIGDET_LANE1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) #define PMD_RCV_SIGDET_LANE0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) #define PMD_RCV_SIGDET_GLOBAL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) #define BCM8704_PCS_10G_R_STATUS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #define PCS_10G_R_STATUS_LINKSTAT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define PCS_10G_R_STATUS_PRBS31_ABLE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) #define PCS_10G_R_STATUS_HI_BER 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) #define PCS_10G_R_STATUS_BLK_LOCK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define BCM8704_USER_CONTROL 0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define USER_CONTROL_OPTXENB_LVL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) #define USER_CONTROL_OPTXRST_LVL 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) #define USER_CONTROL_OPBIASFLT_LVL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) #define USER_CONTROL_OBTMPFLT_LVL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) #define USER_CONTROL_OPPRFLT_LVL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) #define USER_CONTROL_OPTXFLT_LVL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #define USER_CONTROL_OPRXLOS_LVL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) #define USER_CONTROL_OPRXFLT_LVL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) #define USER_CONTROL_OPTXON_LVL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define USER_CONTROL_RES1 0x007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define USER_CONTROL_RES1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define BCM8704_USER_ANALOG_CLK 0xc801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) #define BCM8704_USER_PMD_RX_CONTROL 0xc802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #define BCM8704_USER_PMD_TX_CONTROL 0xc803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) #define USER_PMD_TX_CTL_RES1 0xfe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #define USER_PMD_TX_CTL_XFP_CLKEN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) #define USER_PMD_TX_CTL_TX_DAC_TXD 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define USER_PMD_TX_CTL_TX_DAC_TXD_SH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define USER_PMD_TX_CTL_TX_DAC_TXCK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define USER_PMD_TX_CTL_TX_DAC_TXCK_SH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #define USER_PMD_TX_CTL_TSD_LPWREN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define USER_PMD_TX_CTL_TSCK_LPWREN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define USER_PMD_TX_CTL_CMU_LPWREN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #define USER_PMD_TX_CTL_SFIFORST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #define BCM8704_USER_ANALOG_STATUS0 0xc804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #define BCM8704_USER_OPT_DIGITAL_CTRL 0xc808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define BCM8704_USER_TX_ALARM_STATUS 0x9004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define USER_ODIG_CTRL_FMODE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #define USER_ODIG_CTRL_TX_PDOWN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) #define USER_ODIG_CTRL_RX_PDOWN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) #define USER_ODIG_CTRL_EFILT_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define USER_ODIG_CTRL_OPT_RST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) #define USER_ODIG_CTRL_PCS_TIB 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define USER_ODIG_CTRL_PCS_RI 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define USER_ODIG_CTRL_RESV1 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) #define USER_ODIG_CTRL_GPIOS 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) #define USER_ODIG_CTRL_GPIOS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #define USER_ODIG_CTRL_RESV2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define USER_ODIG_CTRL_LB_ERR_DIS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define USER_ODIG_CTRL_RESV3 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) #define USER_ODIG_CTRL_TXONOFF_PD_DIS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #define BCM8704_PHYXS_XGXS_LANE_STAT 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) #define PHYXS_XGXS_LANE_STAT_ALINGED 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #define PHYXS_XGXS_LANE_STAT_PATTEST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define PHYXS_XGXS_LANE_STAT_MAGIC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #define PHYXS_XGXS_LANE_STAT_LANE3 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define PHYXS_XGXS_LANE_STAT_LANE2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define PHYXS_XGXS_LANE_STAT_LANE1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define PHYXS_XGXS_LANE_STAT_LANE0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #define BCM5464R_AUX_CTL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #define BCM5464R_AUX_CTL_EXT_LB 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define BCM5464R_AUX_CTL_EXT_PLEN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define BCM5464R_AUX_CTL_ER1000 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) #define BCM5464R_AUX_CTL_ER1000_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) #define BCM5464R_AUX_CTL_RESV1 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #define BCM5464R_AUX_CTL_WRITE_1 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #define BCM5464R_AUX_CTL_RESV2 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #define BCM5464R_AUX_CTL_PRESP_DIS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) #define BCM5464R_AUX_CTL_RESV3 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #define BCM5464R_AUX_CTL_ER100 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define BCM5464R_AUX_CTL_ER100_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define BCM5464R_AUX_CTL_DIAG_MODE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define BCM5464R_AUX_CTL_SR_SEL 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define BCM5464R_AUX_CTL_SR_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) #define BCM5464R_CTRL1000_AS_MASTER 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) #define BCM5464R_CTRL1000_ENABLE_AS_MASTER 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) #define RCR_ENTRY_MULTI 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) #define RCR_ENTRY_PKT_TYPE 0x6000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) #define RCR_ENTRY_PKT_TYPE_SHIFT 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) #define RCR_ENTRY_ZERO_COPY 0x1000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) #define RCR_ENTRY_NOPORT 0x0800000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) #define RCR_ENTRY_PROMISC 0x0400000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) #define RCR_ENTRY_ERROR 0x0380000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) #define RCR_ENTRY_DCF_ERR 0x0040000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) #define RCR_ENTRY_L2_LEN 0x003fff0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) #define RCR_ENTRY_L2_LEN_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) #define RCR_ENTRY_PKTBUFSZ 0x000000c000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #define RCR_ENTRY_PKTBUFSZ_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #define RCR_ENTRY_PKT_BUF_ADDR 0x0000003fffffffffULL /* bits 43:6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define RCR_ENTRY_PKT_BUF_ADDR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) #define RCR_PKT_TYPE_OTHER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) #define RCR_PKT_TYPE_TCP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) #define RCR_PKT_TYPE_UDP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define RCR_PKT_TYPE_SCTP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #define NIU_RXPULL_MAX ETH_HLEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) struct rx_pkt_hdr0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #if defined(__LITTLE_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) u8 inputport:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) maccheck:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) class:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) u8 vlan:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) llcsnap:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) noport:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) badip:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) tcamhit:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) tres:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) tzfvld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) u8 class:5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) maccheck:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) inputport:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) u8 tzfvld:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) tres:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) tcamhit:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) badip:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) noport:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) llcsnap:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) vlan:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) struct rx_pkt_hdr1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) u8 hwrsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) u8 tcammatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) #if defined(__LITTLE_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) u8 hwrsvd2:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) hashit:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) exact:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) hzfvld:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) hashsidx:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) u8 hashsidx:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) hzfvld:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) exact:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) hashit:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) hwrsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) u8 zcrsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /* Bits 11:8 of zero copy flow ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) #if defined(__LITTLE_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) u8 hwrsvd3:4, zflowid0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) u8 zflowid0:4, hwrsvd3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* Bits 7:0 of zero copy flow ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) u8 zflowid1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /* Bits 15:8 of hash value, H2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) u8 hashval2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) /* Bits 7:0 of hash value, H2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) u8 hashval2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) /* Bits 19:16 of hash value, H1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #if defined(__LITTLE_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) u8 hwrsvd4:4, hashval1_0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) u8 hashval1_0:4, hwrsvd4:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /* Bits 15:8 of hash value, H1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) u8 hashval1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) /* Bits 7:0 of hash value, H1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) u8 hashval1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) u8 hwrsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) u8 hwrsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) u8 usrdata_0; /* Bits 39:32 of user data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) u8 usrdata_1; /* Bits 31:24 of user data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) u8 usrdata_2; /* Bits 23:16 of user data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) u8 usrdata_3; /* Bits 15:8 of user data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) u8 usrdata_4; /* Bits 7:0 of user data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) struct tx_dma_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) u64 tx_dma_pre_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) u64 tx_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) u64 tx_ring_kick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) u64 tx_ring_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) u64 resv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) u32 tx_rng_err_logl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) u32 tx_rng_err_logh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) u64 resv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) u64 resv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) struct tx_pkt_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) __le64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) #define TXHDR_PAD 0x0000000000000007ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) #define TXHDR_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #define TXHDR_LEN 0x000000003fff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #define TXHDR_LEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #define TXHDR_L4STUFF 0x0000003f00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) #define TXHDR_L4STUFF_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) #define TXHDR_L4START 0x00003f0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) #define TXHDR_L4START_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define TXHDR_L3START 0x000f000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define TXHDR_L3START_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) #define TXHDR_IHL 0x00f0000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #define TXHDR_IHL_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) #define TXHDR_VLAN 0x0100000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) #define TXHDR_LLC 0x0200000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define TXHDR_IP_VER 0x2000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define TXHDR_CSUM_NONE 0x0000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #define TXHDR_CSUM_TCP 0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) #define TXHDR_CSUM_UDP 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) #define TXHDR_CSUM_SCTP 0xc000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) __le64 resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #define TX_DESC_SOP 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #define TX_DESC_MARK 0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #define TX_DESC_NUM_PTR 0x3c00000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) #define TX_DESC_NUM_PTR_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) #define TX_DESC_TR_LEN 0x01fff00000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) #define TX_DESC_TR_LEN_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #define TX_DESC_SAD 0x00000fffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) #define TX_DESC_SAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) struct tx_buff_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) u64 mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) struct txdma_mailbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) __le64 tx_dma_pre_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) __le64 tx_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) __le64 tx_ring_kick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) __le64 tx_ring_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) __le64 resv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) __le32 tx_rng_err_logl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) __le32 tx_rng_err_logh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) __le64 resv2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) } __attribute__((aligned(64)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) #define MAX_TX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) #define MAX_TX_DESC_LEN 4076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) struct tx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) struct tx_buff_info tx_buffs[MAX_TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) struct niu *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) u64 tx_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) int prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) int cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) int wrap_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) u16 last_pkt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) u16 tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) u16 mark_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) u16 mark_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) u16 mark_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) u16 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) struct txdma_mailbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) __le64 *descr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) u64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) u64 tx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) u64 mbox_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) u64 descr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) int max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) #define NEXT_TX(tp, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) (((index) + 1) < (tp)->pending ? ((index) + 1) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) static inline u32 niu_tx_avail(struct tx_ring_info *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) return (tp->pending -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) struct rxdma_mailbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) __le64 rx_dma_ctl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) __le64 rbr_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) __le32 rbr_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) __le32 rbr_hdh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) __le64 resv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) __le32 rcrstat_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) __le32 rcrstat_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) __le64 rcrstat_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) __le64 resv2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) } __attribute__((aligned(64)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #define MAX_RBR_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define MAX_RCR_RING_SIZE (MAX_RBR_RING_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) #define RBR_REFILL_MIN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define RX_SKB_ALLOC_SIZE 128 + NET_IP_ALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) struct rx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) struct niu *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) int rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) u16 rbr_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) u16 rbr_blocks_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) u16 rbr_sizes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) unsigned int rcr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) unsigned int rcr_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) unsigned int rbr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) unsigned int rbr_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) unsigned int rbr_refill_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) unsigned int rbr_kick_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) unsigned int rbr_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) struct page **rxhash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) struct rxdma_mailbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) __le64 *rcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) __le32 *rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) #define RBR_DESCR_ADDR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) u64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) u64 rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) u64 rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) u64 rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) u64 mbox_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) u64 rcr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) u64 rbr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /* WRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) int nonsyn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) int nonsyn_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) int syn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) int syn_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /* interrupt mitigation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) int rcr_pkt_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) int rcr_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) #define NEXT_RCR(rp, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #define NEXT_RBR(rp, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) #define NIU_MAX_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) #define NIU_NUM_RXCHAN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define NIU_NUM_TXCHAN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) #define MAC_NUM_HASH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define NIU_MAX_MTU 9216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) /* VPD strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define NIU_QGC_LP_BM_STR "501-7606"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) #define NIU_2XGF_LP_BM_STR "501-7283"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) #define NIU_QGC_PEM_BM_STR "501-7765"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) #define NIU_2XGF_PEM_BM_STR "501-7626"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define NIU_ALONSO_BM_STR "373-0202"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) #define NIU_FOXXY_BM_STR "501-7961"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define NIU_2XGF_MRVL_BM_STR "SK-6E82"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) #define NIU_QGC_LP_MDL_STR "SUNW,pcie-qgc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #define NIU_2XGF_LP_MDL_STR "SUNW,pcie-2xgf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define NIU_QGC_PEM_MDL_STR "SUNW,pcie-qgc-pem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define NIU_2XGF_PEM_MDL_STR "SUNW,pcie-2xgf-pem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) #define NIU_ALONSO_MDL_STR "SUNW,CP3220"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) #define NIU_KIMI_MDL_STR "SUNW,CP3260"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) #define NIU_MARAMBA_MDL_STR "SUNW,pcie-neptune"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) #define NIU_FOXXY_MDL_STR "SUNW,pcie-rfem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define NIU_2XGF_MRVL_MDL_STR "SysKonnect,pcie-2xgf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define NIU_VPD_MIN_MAJOR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) #define NIU_VPD_MIN_MINOR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) #define NIU_VPD_MODEL_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) #define NIU_VPD_BD_MODEL_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #define NIU_VPD_VERSION_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #define NIU_VPD_PHY_TYPE_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) struct niu_vpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) char model[NIU_VPD_MODEL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) char board_model[NIU_VPD_BD_MODEL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) char version[NIU_VPD_VERSION_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) char phy_type[NIU_VPD_PHY_TYPE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) u8 mac_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) u8 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) u8 local_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) int fcode_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) int fcode_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) struct niu_altmac_rdc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) u8 alt_mac_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) u8 rdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) u8 mac_pref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) struct niu_vlan_rdc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) u8 rdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) u8 vlan_pref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) struct niu_classifier {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) struct niu_altmac_rdc alt_mac_mappings[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) struct niu_vlan_rdc vlan_mappings[ENET_VLAN_TBL_NUM_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) u16 tcam_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) u16 tcam_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) u16 tcam_valid_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) u16 num_alt_mac_mappings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) u32 h1_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) u16 h2_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) #define NIU_NUM_RDC_TABLES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) #define NIU_RDC_TABLE_SLOTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) struct rdc_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) u8 rxdma_channel[NIU_RDC_TABLE_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct niu_rdc_tables {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) struct rdc_table tables[NIU_NUM_RDC_TABLES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) int first_table_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) int num_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define PHY_TYPE_PMA_PMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) #define PHY_TYPE_PCS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) #define PHY_TYPE_MII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) #define PHY_TYPE_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) struct phy_probe_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) u32 phy_id[PHY_TYPE_MAX][NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) u8 phy_port[PHY_TYPE_MAX][NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) u8 cur[PHY_TYPE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) struct device_attribute phy_port_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) struct device_attribute phy_type_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) struct device_attribute phy_id_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) struct niu_tcam_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) u8 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) u64 key[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) u64 key_mask[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) u64 assoc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) union niu_parent_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) int domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) int device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) } pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) struct device_node *of;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) struct niu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) struct niu_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) struct platform_device *plat_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) union niu_parent_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) struct niu *ports[NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) atomic_t refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define PARENT_FLGS_CLS_HWINIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) u32 port_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) #define PORT_PHY_UNKNOWN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) #define PORT_PHY_INVALID 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define PORT_TYPE_10G 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #define PORT_TYPE_1G 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) #define PORT_TYPE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) u8 rxchan_per_port[NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) u8 txchan_per_port[NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) struct niu_rdc_tables rdc_group_cfg[NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) u8 rdc_default[NIU_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) u8 ldg_map[LDN_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) u8 plat_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #define PLAT_TYPE_INVALID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #define PLAT_TYPE_ATLAS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #define PLAT_TYPE_NIU 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) #define PLAT_TYPE_VF_P0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) #define PLAT_TYPE_VF_P1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) #define PLAT_TYPE_ATCA_CP3220 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) u8 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) u16 tcam_num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #define NIU_PCI_TCAM_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #define NIU_NONPCI_TCAM_ENTRIES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) #define NIU_TCAM_ENTRIES_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) int rxdma_clock_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) struct phy_probe_info phy_probe_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) struct niu_tcam_entry tcam[NIU_TCAM_ENTRIES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) #define NIU_L2_PROG_CLS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #define NIU_L3_PROG_CLS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) u64 l2_cls[NIU_L2_PROG_CLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) u64 l3_cls[NIU_L3_PROG_CLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) u64 tcam_key[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) u64 flow_key[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) u16 l3_cls_refcnt[NIU_L3_PROG_CLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) u8 l3_cls_pid[NIU_L3_PROG_CLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) struct niu_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) void *(*alloc_coherent)(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) u64 *handle, gfp_t flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) void (*free_coherent)(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) void *cpu_addr, u64 handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) u64 (*map_page)(struct device *dev, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) unsigned long offset, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) enum dma_data_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) void (*unmap_page)(struct device *dev, u64 dma_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) size_t size, enum dma_data_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) u64 (*map_single)(struct device *dev, void *cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) enum dma_data_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) void (*unmap_single)(struct device *dev, u64 dma_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) size_t size, enum dma_data_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) struct niu_link_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) u32 supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /* Describes what we're trying to get. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) u16 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) u8 duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) u8 autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) /* Describes what we actually have. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) u32 active_advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) u16 active_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) u8 active_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) u8 active_autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) #define SPEED_INVALID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) #define DUPLEX_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #define AUTONEG_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) u8 loopback_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) #define LOOPBACK_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) #define LOOPBACK_PHY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #define LOOPBACK_MAC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) struct niu_ldg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct niu *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) u8 ldg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) u8 timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) u64 v0, v1, v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) struct niu_xmac_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) u64 tx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) u64 tx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) u64 tx_overflow_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) u64 tx_max_pkt_size_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) u64 tx_underflow_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) u64 rx_local_faults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) u64 rx_remote_faults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) u64 rx_link_faults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) u64 rx_align_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) u64 rx_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) u64 rx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) u64 rx_bcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) u64 rx_hist_cnt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) u64 rx_hist_cnt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) u64 rx_hist_cnt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) u64 rx_hist_cnt4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) u64 rx_hist_cnt5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) u64 rx_hist_cnt6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) u64 rx_hist_cnt7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) u64 rx_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) u64 rx_code_violations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) u64 rx_len_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) u64 rx_crc_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) u64 rx_underflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) u64 rx_overflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) u64 pause_off_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) u64 pause_on_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) u64 pause_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) struct niu_bmac_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) u64 tx_underflow_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) u64 tx_max_pkt_size_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) u64 tx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) u64 rx_overflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) u64 rx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) u64 rx_align_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) u64 rx_crc_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) u64 rx_len_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) u64 pause_off_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) u64 pause_on_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) u64 pause_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) union niu_mac_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) struct niu_xmac_stats xmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) struct niu_bmac_stats bmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) struct niu_phy_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) int (*serdes_init)(struct niu *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) int (*xcvr_init)(struct niu *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) int (*link_status)(struct niu *np, int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) struct niu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) struct niu_parent *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) #define NIU_FLAGS_HOTPLUG_PHY_PRESENT 0x02000000 /* Removeable PHY detected*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) #define NIU_FLAGS_HOTPLUG_PHY 0x01000000 /* Removeable PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #define NIU_FLAGS_VPD_VALID 0x00800000 /* VPD has valid version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) #define NIU_FLAGS_MSIX 0x00400000 /* MSI-X in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) #define NIU_FLAGS_MCAST 0x00200000 /* multicast filter enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) #define NIU_FLAGS_PROMISC 0x00100000 /* PROMISC enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) #define NIU_FLAGS_XCVR_SERDES 0x00080000 /* 0=PHY 1=SERDES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) #define NIU_FLAGS_10G 0x00040000 /* 0=1G 1=10G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) #define NIU_FLAGS_FIBER 0x00020000 /* 0=COPPER 1=FIBER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) #define NIU_FLAGS_XMAC 0x00010000 /* 0=BMAC 1=XMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) char irq_name[NIU_NUM_RXCHAN+NIU_NUM_TXCHAN+3][IFNAMSIZ + 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /* Protects hw programming, and ring state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) const struct niu_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) union niu_mac_stats mac_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) struct rx_ring_info *rx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) struct tx_ring_info *tx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) int num_rx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) int num_tx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) struct niu_ldg ldg[NIU_NUM_LDG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) int num_ldg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) void __iomem *mac_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) unsigned long ipp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) unsigned long pcs_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) unsigned long xpcs_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) u64 orig_led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) const struct niu_phy_ops *phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) int phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) struct niu_link_config link_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) u8 mac_xcvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) #define MAC_XCVR_MII 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) #define MAC_XCVR_PCS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) #define MAC_XCVR_XPCS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) struct niu_classifier clas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) struct niu_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) u32 eeprom_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) void __iomem *vir_regs_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) void __iomem *vir_regs_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) #endif /* _NIU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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