^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Sun Microsystems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * vendor id: 0x108E (Sun Microsystems, Inc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * device id: 0xabba (Cassini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * revision ids: 0x01 = Cassini
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 0x02 = Cassini rev 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 0x10 = Cassini+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 0x11 = Cassini+ 0.2u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * vendor id: 0x100b (National Semiconductor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * device id: 0x0035 (DP83065/Saturn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * revision ids: 0x30 = Saturn B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * rings are all offset from 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * there are two clock domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * PCI: 33/66MHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * chip: 125MHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifndef _CASSINI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define _CASSINI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 32-bit words. there is no i/o port access. REG_ addresses are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * shared between cassini and cassini+. REG_PLUS_ addresses only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CAS_ID_REV2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAS_ID_REVPLUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAS_ID_REVPLUS02u 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAS_ID_REVSATURNB2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /** global resources **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* this register sets the weights for the weighted round robin arbiter. e.g.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * for its next turn to access the pci bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * DEFAULT: 0x0, SIZE: 5 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_CAWR 0x0004 /* core arbitration weight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CAWR_RX_DMA_WEIGHT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CAWR_TX_DMA_WEIGHT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CAWR_RR_DIS 0x10 /* [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * sizes determined by length of packet or descriptor transfer and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * max length allowed by the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * DEFAULT: 0x0, SIZE: 1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_INF_BURST 0x0008 /* infinite burst enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INF_BURST_EN 0x1 /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* top level interrupts [0-9] are auto-cleared to 0 when the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * register is read. second level interrupts [13 - 18] are cleared at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * the source. tx completion register 3 is replicated in [19 - 31]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * DEFAULT: 0x00000000, SIZE: 29 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_INTR_STATUS 0x000C /* interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) xferred from host queue to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TX FIFO. i.e.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TX Kick == TX complete. if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PACED_MODE set, then TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) also empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) corrupted. FATAL ERROR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) from RX FIFO to host mem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RX completion reg updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) may be delayed by recv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) intr blanking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RX Kick == RX complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) corrupted. FATAL ERROR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ring to post descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RX complete head incr to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) almost reach RX complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define INTR_RX_BUF_AE 0x00000100 /* less than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) programmable threshold #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) of free descr avail for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) hw use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTR_RX_COMP_AF 0x00000200 /* less than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) programmable threshold #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) of descr spaces for hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) use in completion descr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) len of non-reassembly pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) from fifo during DMA or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) header parser provides TCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) header and payload size >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MAC packet size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FATAL ERROR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bit will be set if an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) generated on the pci bus. useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) when driver is polling for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) least 1 unmasked interrupt set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) least 1 unmasked interrupt set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) at least 1 unmasked interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 1 unmasked interrupt set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) BIF has at least 1 unmasked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) interrupt set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 3 reg data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INTR_TX_COMP_3_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) INTR_MAC_CTRL_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* determines which status events will cause an interrupt. layout same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * as REG_INTR_STATUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_INTR_MASK 0x0010 /* Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * DEFAULT: 0x00000000, SIZE: 12 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (used w/ status alias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* same as REG_INTR_STATUS except that only bits cleared are those selected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * REG_ALIAS_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * DEFAULT: 0x00000000, SIZE: 29 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (selective clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* DEFAULT: 0x0, SIZE: 3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) set if no ACK64# during ABS64 cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) no read retry after 2^15 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCI_ERR_OTHER 0x04 /* other PCI errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unused in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unused in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DMA. unused in cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * causes an interrupt to be generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * DEFAULT: 0x7, SIZE: 3 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* used to configure PCI related parameters that are not in PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * DEFAULT: 0bxx000, SIZE: 5 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define REG_BIM_CFG 0x1008 /* BIM Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BIM_CFG_RESERVED0 0x001 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BIM_CFG_RESERVED1 0x002 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BIM_CFG_RESERVED2 0x100 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reset. reserved in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reserved in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reserved in Cassini. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* DEFAULT: 0x00000000, SIZE: 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) machine bits [21:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) machine bits [6:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * reset. poll until TX and RX read back as 0's for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define REG_SW_RESET 0x1010 /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cleared to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cleared to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) resets PHY and anything else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) connected to RSTOUT#. RSTOUT#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) is also activated by local PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reset when hot-swap is being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) this bit set, PCS and SLINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) modules won't be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) i.e., link won't drop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0b000: ARB_IDLE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0b001: ARB_IDLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0b010: ARB_WB_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0b011: ARB_WB_WAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0b100: ARB_RB_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0b101: ARB_RB_WAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0b110: ARB_RB_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0b111: ARB_WB_END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0b00: RD_PCI_WAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0b01: RD_PCI_RDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0b11: RD_PCI_ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0b00: AD_IDL_RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0b01: AD_ACK_RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0b10: AD_ACK_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0b11: AD_IDL_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0b00: WR_PCI_WAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0b01: WR_PCI_RDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0b11: WR_PCI_ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0b000: ARB_IDLE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0b001: ARB_IDLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0b010: ARB_TX_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0b011: ARB_TX_WAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0b100: ARB_RX_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0b110: ARB_RX_WAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Cassini only. 64-bit register used to check PCI datapath. when read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * value written has both lower and upper 32-bit halves rotated to the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) Cassini+: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* output enables are provided for each device's chip select and for the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * of the outputs from cassini to its local bus devices. two sw programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * bits are connected to general purpus control/status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * DEFAULT: 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) output EN. default: 0x7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) OE signal output enable on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) local bus interface. these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) are shared between both local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bus devices. tristate when 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) select output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * _DATA_HI should be the last access of the sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) purposes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) read buffer access = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* DEFAULT: undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) Cassini only. reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) Cassini+. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) buffer. Cassini only. reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) in Cassini+. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Cassini only. reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Cassini+. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) Cassini only. reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) Cassini+. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* ASUN: i'm not sure what this does as it's not in the spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * DEFAULT: 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * values for _SEL_HI_MASK and _SEL_LOW_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * wtc empty r, post pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * pci rpkt comp, txdma wr req, txdma wr ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * txdma wr rdy, txdma wr xfr done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * rd arb state, rd pci state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * wrpci state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * the following are not available in Cassini:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) driven on local bus P_A[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x03 = mac[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x0C = rx[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x30 = tx[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0xC0 = hp[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) on P_A[15:8]. see above for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) on P_A[7:0]. see above for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DEFAULT: 0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) register 2 for INTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * all of the alternate (2-4) INTR registers while _1 corresponds to only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * _MASK_1 and _STATUS_1 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define INTR_RX_DONE_ALT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define INTR_RX_COMP_FULL_ALT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define INTR_RX_COMP_AF_ALT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define INTR_RX_BUF_UNAVAIL_1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define INTR_RX_BUF_AE_1 0x10 /* almost empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define INTRN_MASK_RX_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) INTR_RX_COMP_FULL_ALT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) INTR_RX_COMP_AF_ALT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) INTR_RX_BUF_UNAVAIL_1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) INTR_RX_BUF_AE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) register 2 for INTB. default: 0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) flags are set. enables desc ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) register 2 for INTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) register alias 2 for INTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define REG_SATURN_PCFG 0x106c /* pin configuration register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) integrated macphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0 = normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SATURN_PCFG_MTP 0x00000080 /* test point select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GMII on SERDES pins for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) monitoring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pins configed as outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for power saving when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) internal phy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) polarity from strapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 1 = mac core led ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) polarity active low. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /** transmit dma registers **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MAX_TX_RINGS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* TX configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * DEFAULT: 0x3F000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define REG_TX_CFG 0x2004 /* TX config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) will stop after xfer of current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) buffer has been completed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) accessed w/ FIFO addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) and data registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) TX DMA should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ring 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TX_CFG_DESC_RING0_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) TX FIFO becomes empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if 0, TX_ALL set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if descr queue empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) the end of every packet kicked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) through Q1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) the end of every packet kicked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) through Q2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) the end of every packet kicked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) through Q3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) the end of every packet kicked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) through Q4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) writeback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) connection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0b00: tx mac req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tx mac retry req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tx ack and tx tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0b01: txdma rd req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) txdma rd ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) txdma rd rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) txdma rd type0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0b11: txdma wr req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) txdma wr ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) txdma wr rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) txdma wr xfr done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TX_CFG_CTX_SEL_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * used for diagnostics only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pointer. temp hold reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) diagnostics only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* current state of all state machines in TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) = 0x01 when TX disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * while the upper 23 bits are taken from the TX descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* 13 bit registers written by driver w/ descriptor value that follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * last valid xmit descriptor. kick # and complete # values are used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * the xmit dma engine to control tx descr fetching. if > 1 valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * tx descr is available within the cache line being read, cassini will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define REG_TX_KICK0 0x2038 /* TX kick reg #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* values of TX_COMPLETE_1-4 are written. each completion register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * NOTE: completion reg values are only written back prior to TX_INTME and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * TX_ALL interrupts. at all other times, the most up-to-date index values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * should be obtained from the REG_TX_COMPLETE_# registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * here's the layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * offset from base addr completion # byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * 0 TX_COMPLETE_1_MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * 1 TX_COMPLETE_1_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * 2 TX_COMPLETE_2_MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * 3 TX_COMPLETE_2_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * 4 TX_COMPLETE_3_MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * 5 TX_COMPLETE_3_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * 6 TX_COMPLETE_4_MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * 7 TX_COMPLETE_4_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define TX_COMPWB_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) base low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) base high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define TX_COMPWB_MSB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define TX_COMPWB_LSB_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define TX_COMPWB_NEXT(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * be 2KB-aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* 16-bit registers hold weights for the weighted round-robin of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * four CBQ TX descr rings. weights correspond to # bytes xferred from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * host to TXFIFO in a round of WRR arbitration. can be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * dynamically with new weights set upon completion of the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * packet transfer from host memory to TXFIFO. a dummy write to any of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * these registers causes a queue1 pre-emption with all historical bw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * deficit data reset to 0 (useful when congestion requires a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * pre-emption/re-allocation of network bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* diagnostics access to any TX FIFO location. every access is 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * TX FIFO data integrity is desired, TX DMA should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * disabled. _DATA_HI_Tx should be the last access of the sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * passed for the specified memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) controller state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clears on completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /** receive dma registers **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MAX_RX_DESC_RINGS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MAX_RX_COMP_RINGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* receive DMA channel configuration. default: 0x80910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * free ring size = (1 << n)*32 -> [32 - 8k]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * DEFAULT: 0x80910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define REG_RX_CFG 0x4000 /* RX config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) channel as soon as current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) frame xfer has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) driver should disable MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) for 200ms before disabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) free desc ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) def: 0x8 = 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define RX_CFG_DESC_RING_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ring. def: 0x8 = 32k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define RX_CFG_COMP_RING_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) batching. def: 0x0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) data byte of the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) w/in 8 byte boundares.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) this swivels the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DMA'ed to header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) buffers, jumbo buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) when header split is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) requested and MTU sized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buffers. def: 0x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define RX_CFG_SWIVEL_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* cassini+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RX free desc ring 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) def: 0x8 = 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define RX_CFG_DESC_RING1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* the page size register allows cassini chips to do the following with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * received data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * [--------------------------------------------------------------] page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * |--------------| = PAGE_SIZE_BUFFER_STRIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * page = PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * offset = PAGE_SIZE_MTU_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * for the above example, MTU_BUFFER_COUNT = 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * NOTE: as is apparent, you need to ensure that the following holds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * DEFAULT: 0x48002002 (8k pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) by receive descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if jumbo buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) supported the page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) should not be < 8k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0b00 = 2k, 0b01 = 4k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 0b10 = 8k, 0b11 = 16k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) DEFAULT: 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define RX_PAGE_SIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) packs into a page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) DEFAULT: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) each MTU buffer +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) offset from each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0b00 = 1k, 0b01 = 2k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0b10 = 4k, 0b11 = 8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) DEFAULT: 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) hw writes the MTU buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0b00 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0b01 = 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0b10 = 96, 0b11 = 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DEFAULT: 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* 11-bit counter points to next location in RX FIFO to be loaded/read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * shadow write pointers enable retries in case of early receive aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * DEFAULT: 0x0. generated on 64-bit boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pointer. (8-bit counter) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* current state of RX DMA state engines + other info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define REG_RX_DEBUG 0x401C /* RX debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0x0 = idle, 0x1 = load_bop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0x2 = load 1, 0x3 = load 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 0x4 = load 3, 0x5 = load 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0x6 = last detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0x7 = wait req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0x8 = wait req statuss 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0x9 = load st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 0xa = bubble mac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 0xb = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RX FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 0x0 = idle, 0x1 = hp xfr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0x2 = wait hp ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 0x3 = wait flow code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0x4 = fifo xfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0x5 = make status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 0x6 = csum ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 0x7 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) w/ MAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 0x0 = idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 0x1 = wait xoff ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 0x2 = wait xon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0x3 = wait xon ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 0x0 = idle data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 0x1 = header begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 0x2 = xfer header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 0x3 = xfer header ld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 0x4 = mtu begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 0x5 = xfer mtu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0x6 = xfer mtu ld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0x7 = jumbo begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 0x8 = xfer jumbo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 0x9 = xfer jumbo ld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 0xa = reas begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0xb = xfer reas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 0xc = flush tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 0xd = xfer reas ld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 0xe = error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 0xf = bubble idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 0x0 = idle desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 0x1 = wait ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 0x9 = wait ack 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 0x2 = fetch desc 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 0xa = fetch desc 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0x3 = load ptrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 0x4 = wait dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 0x5 = wait ack batch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0x6 = post batch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0x7 = xfr done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) interrupt queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) of the interrupt queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* flow control frames are emitted using two PAUSE thresholds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * value is is 0x6F.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * DEFAULT: 0x00078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define RX_PAUSE_THRESH_QUANTUM 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) RX FIFO occupancy >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) value*64B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define RX_PAUSE_THRESH_OFF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) emitting XOFF PAUSE when RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) FIFO occupancy falls below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) this value*64B. must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) < XOFF threshold. if =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RX_FIFO_SIZE< XON frames are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) never emitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define RX_PAUSE_THRESH_ON_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* 13-bit register used to control RX desc fetching and intr generation. if 4+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * valid RX descriptors are available, Cassini will read 4 at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * writing N means that all desc up to *but* excluding N are available. N must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * DEFAULT: 0 on reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define REG_RX_KICK 0x4024 /* RX kick reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * lower 13 bits of the low register are hard-wired to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) base low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define REG_RX_DB_HI 0x402C /* RX descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) base hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define REG_RX_CB_LOW 0x4030 /* RX completion ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) base low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define REG_RX_CB_HI 0x4034 /* RX completion ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) base hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* 13-bit register indicate desc used by cassini for receive frames. used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * for diagnostic purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * DEFAULT: 0 on reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define REG_RX_COMP 0x4038 /* (ro) RX completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* HEAD and TAIL are used to control RX desc posting and interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * generation. hw moves the head register to pass ownership to sw. sw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * moves the tail register to pass ownership back to hw. to give all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * more entries are available, DMA will pause and an interrupt will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * generated to indicate no more entries are available. sw can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * this interrupt to reduce the # of times it must update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * completion tail register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * DEFAULT: 0 on reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define REG_RX_COMP_HEAD 0x403C /* RX completion head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* values used for receive interrupt blanking. loaded each time the ISR is read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * DEFAULT: 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define REG_RX_BLANK 0x4044 /* RX blanking register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) for ISR read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) this many sets of completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) writebacks (up to 2 packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) occur since the last time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) the ISR was read. 0 = no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) packet blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define RX_BLANK_INTR_PKT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if that many clocks were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) counted since last time the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ISR was read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) each count is 512 core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clocks (125MHz). 0 = no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) time blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define RX_BLANK_INTR_TIME_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* values used for interrupt generation based on threshold values of how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * many free desc and completion entries are available for hw use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * DEFAULT: 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define REG_RX_AE_THRESH 0x4048 /* RX almost empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) generated if # desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) avail for hw use <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define RX_AE_THRESH_FREE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) generated if # of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) completion entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) avail for hw use <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define RX_AE_THRESH_COMP_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* probabilities for random early drop (RED) thresholds on a FIFO threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * basis. probability should increase when the FIFO level increases. control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * packets are never dropped and not counted in stats. probability programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * DEFAULT: 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define REG_RX_RED 0x404C /* RX random early detect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * RX control FIFO = # of packets in RX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * START/COMPLETE is writeable. START will clear when the BIST has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * checking all 17 RAMS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define REG_RX_BIST 0x4060 /* (ro) RX BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define RX_BIST_SUMMARY 0x00000002 /* when BIST complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) summary pass bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) contains AND of BIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) results of all 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RAMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define RX_BIST_START 0x00000001 /* write 1 to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) BIST. self clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) on completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * from to retrieve packet control info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * DEFAULT: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) write ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* receive interrupt blanking. loaded each time interrupt alias register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) alias read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) completion writebacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) > # since last ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) read. 0 = no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) blanking. up to 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) packets per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) completion wb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) clocks > # since last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ISR read. each count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) is 512 core clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (125MHz). 0 = no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) blanking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * to normal operation after diagnostics, write to address location 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * be the last write access of a write sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * should be last write access of the write sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) Batching FIFO addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) hi and flow id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) T0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) T1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* 64-bit pointer to receive data buffer in host memory used for headers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * small packets. MSB in high register. loaded by DMA state machine and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * increments as DMA writes receive data. only 50 LSB are incremented. top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * 13 bits taken from RX descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) data mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) data high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* cassini+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * 0. same semantics as primary desc/complete rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 2 base low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) 2 base high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) 2 base low. 4 total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) 2 base high. 4 total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) head reg. 4 total. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) tail reg. 4 total. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /** header parser registers **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* RX parser configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * DEFAULT: 0x1651004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define REG_HP_CFG 0x4140 /* header parser
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) configuration reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) 0 = 64. 0x3f = 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define HP_CFG_NUM_CPU_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) TCP seq # by one when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) stored in FDBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) needed to be considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) for reassembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define HP_CFG_TCP_THRESH_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* access to RX Instruction RAM. 5-bit register/counter holds addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * of sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) data mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define HP_INSTR_RAM_MID_OP_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) data high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define HP_INSTR_RAM_HI_VAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define HP_INSTR_RAM_HI_MASK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* PIO access into RX Header parser data RAM and flow database.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * flow database.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * should be the last write access of the write sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * DEFAULT: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RAM address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) locations in header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) parser data ram to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) in the flow database */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * FLOW_DB(10) = bit 0 has value for flow valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* diagnostics for RX Header Parser block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * ASUN: the header parser state machine register is used for diagnostics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * purposes. however, the spec doesn't have any details on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) start offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) reassembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) equal to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) chk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* BIST for header parser(HP) and flow database memories (FDBM). set _START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * to start BIST. controller clears _START on completion. _START can also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * be cleared to force termination of BIST. a bit set indicates that that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * memory passed its BIST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) bank 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /** MAC registers. **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* reset bits are set using a PIO write and self-cleared after the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * execution has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) command (default: 0x0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) command (default: 0x0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* execute a pause flow control frame transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) DEFAULT: 0x0XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) to be sent on network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) in units of slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) frame on network */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* bit set indicates that event occurred. auto-cleared when status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * is read and have corresponding mask bits in mask register. events will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * trigger an interrupt if the corresponding mask bit is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * status register default: 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * mask register default = 0xFFFFFFFF on reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) transmision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define MAC_TX_UNDERRUN 0x0002 /* terminated frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) transmission due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) data starvation in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) xmit data path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) length passed to TX MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) by the DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define MAC_TX_COLL_LATE 0x0020 /* rollover of the late
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) attempts counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) RX FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define MAC_RX_LEN_ERR 0x0020 /* rollover of length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) violation error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* DEFAULT: 0xXXXX0000 on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) reception of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) pause control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) transition from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "not paused" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "paused" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) transition from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) "paused" to "not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) paused" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) operand that was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) received in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) pause flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* layout identical to TX MAC[8:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* layout identical to RX MAC[6:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* layout identical to CTRL MAC[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * imposed before writes to other bits in the TX_MAC_CFG register or any of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * the MAC parameters is performed. delay dependent upon time required to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * the delay for a 1518-byte frame on a 100Mbps network is 125us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * alternatively, just poll TX_CFG_EN until it reads back as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * be 0x200 (slot time of 512 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) force TXMAC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) machine to remain in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) idle state or to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) transition to idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) on completion of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ongoing packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) process. set to 1 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) full duplex and 0 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) half duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) algorithm. set to 1 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) full duplex and 0 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) half duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) Rx-to-TX IPG. after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) receiving a frame, TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) MAC will reset its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) deferral process to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) carrier sense for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) amount of time = IPG0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) IPG1 and commit to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) transmission for time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) specified in IPG2. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) 0 or when xmitting frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) back-to-pack (Tx-to-Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) IPG), TX MAC ignores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) IPG0 and will only use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) IPG1 for deferral time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) IPG2 still used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) give up on frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) xmission. if backoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) algorithm reaches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ATTEMPT_LIMIT, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) clear attempts counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) and continue trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) send the frame as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) GIVE_UP_LIM. when 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) TX MAC will execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) standard CSMA/CD prot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) continue to try to xmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) until successful. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) 0, TX MAC will continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) to try xmitting until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) successful or backoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) algorithm reaches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ATTEMPT_LIMIT*16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) backoff algorithm. TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MAC will not back off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) after a xmission attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) that resulted in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) collision. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) deferral process is reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) in response to carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) sense during the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) duration of IPG. TX MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) will only commit to frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) xmission after frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) xmission has actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) begun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) CRC for all xmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) packets. when clear, CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) generation is dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) upon NO_CRC bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) xmit control word from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) TX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) carrier extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) feature. this allows for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) longer collision domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) by extending the carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) and collision window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) from the end of FCS until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) the end of the slot time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if necessary. Required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) for half-duplex at 1Gbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) clear otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* when CRC is not stripped, reassembly packets will not contain the CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * these will be stripped by HRP because it reassembles layer 4 data, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * CRC is layer 2. however, non-reassembly packets will still contain the CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * when passed to the host. to ensure proper operation, need to wait 3.2ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * after clearing RX_CFG_EN before writing to any other RX MAC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * restrictions as CFG_EN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) feature not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) last 4 bytes of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) received frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) multicast frames (group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) bit in DA field set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) multicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) address filtering regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) to filter both unicast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) and multicast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) RX DMA by setting BAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) bit but not Abort bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) in the status. CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) framing, and length errs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) will not increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) error counters. frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) which don't match dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) addr will be passed up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) w/ BAD bit set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) packet bursts generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) by carrier extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) with packet bursting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) senders. only applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) to half-duplex 1Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* DEFAULT: 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) sending pause flow ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pause flow ctrl frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) packets to RX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* to ensure proper operation, a global initialization sequence should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * performed when a loopback config is entered or exited. if programmed after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * a hw or global sw reset, RX/TX MAC software reset and initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * should be done to ensure stable clocking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define REG_MAC_XIF_CFG 0x603C /* XIF config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) on MII xmit bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) path to GMII recv data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) path. phy mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) clock selection must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) set to GMII mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) GMII_MODE should be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) to 1. in loopback mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) REFCLK will drive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) entire mac core. 0 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) normal operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) path during packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) xmission. clear to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) in any full duplex mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) in any loopback mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) or in half-duplex SERDES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) or SLINK modes. set when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) in half-duplex when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) using external phy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) clocks and datapath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) external tristate buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) on the MII receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) recommended: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) recommended: 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) recommended: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define REG_MAC_SLOT_TIME 0x604C /* slot time reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) recommended: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) recommended: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * recommended value: 0x2000.05EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) preamble bytes that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) TX MAC will xmit at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) beginning of each frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) value should be 2 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) greater. recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) value: 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) of jam in units of media
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) byte time. recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) value: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) of attempts TX MAC will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) make to xmit a frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) before it resets its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) attempts counter. after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) the limit has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) reached, TX MAC may or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) may not drop the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dependent upon value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) in TX_MAC_CFG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) type field of a MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ctrl frame. recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) value: 0x8808 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * register contains comparison
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * 0 16 MSB of primary MAC addr [47:32] of DA field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * 1 16 middle bits "" [31:16] of DA field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * 2 16 LSB "" [15:0] of DA field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * 4*x 16 middle bits "" [31:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * 5*x 16 LSB "" [15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * 42 16 MSB of MAC CTRL addr [47:32] of DA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * 43 16 middle bits "" [31:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * 44 16 LSB "" [15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * if there is a match, MAC will set the bit for alternative address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * filter pass [15]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * here is the map of registers given MAC address notation: a:b:c:d:e:f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * ab cd ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * primary addr reg 2 reg 1 reg 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * alt addr 1 reg 5 reg 4 reg 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * alt addr x reg 5*x reg 4*x reg 3*x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * ctrl addr reg 44 reg 43 reg 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) [47:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mask reg. 8-bit reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) contains nibble mask for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) reg 2 and 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * 16-bit registers contain bits of the hash table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * e.g., 15 -> [15:0], 0 -> [255:240]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* statistics registers. these registers generate an interrupt on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * overflow. recommended initialization: 0x0000. most are 16-bits except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * for PEAK_ATTEMPTS register which is 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define REG_MAC_COLL_FIRST 0x61A4 /* first attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) successful collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define REG_MAC_COLL_LATE 0x61AC /* late collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) is the media byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) clock/256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define REG_MAC_LEN_ERR 0x61BC /* length error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* misc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) 10-bit register used as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) seed for the random number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) generator for the CSMA/CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) backoff algorithm. only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) programmed after power-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) reset and should be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) random value which has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) high likelihood of being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unique for each MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) attached to a network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) segment (e.g., 10 LSB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) MAC address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* 27-bit register has the current state for key state machines in the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define MAC_SM_RLM_MASK 0x07800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define MAC_SM_RLM_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define MAC_SM_RX_FC_MASK 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define MAC_SM_RX_FC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define MAC_SM_TLM_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define MAC_SM_TLM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define MAC_SM_ENCAP_SM_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define MAC_SM_ENCAP_SM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define MAC_SM_TX_REQ_MASK 0x00000C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define MAC_SM_TX_REQ_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define MAC_SM_TX_FC_MASK 0x000003C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define MAC_SM_TX_FC_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /** MIF registers. the MIF can be programmed in either bit-bang or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * frame mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) 1 -> 0 will generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) rising edge. 0 -> 1 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) generate a falling edge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) register generates data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) enable. enable when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) xmitting data from MIF to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) transceiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* 32-bit register serves as an instruction register when the MIF is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * programmed in frame mode. load this register w/ a valid instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * (as per IEEE 802.3u MII spec). poll this register to check for instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * execution completion. during a read operation, this register will also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * contain the 16-bit data returned by the tranceiver. unless specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * otherwise, fields are considered "don't care" when polling for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define REG_MIF_FRAME 0x620C /* MIF frame/output reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) load w/ 01 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) issuing an instr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define MIF_FRAME_ST 0x40000000 /* STart of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) write. 10 for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) issuing an instr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) this field should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) loaded w/ the XCVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define MIF_FRAME_PHY_ADDR_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) when issuing an instr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) addr of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) to be read/written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define MIF_FRAME_REG_ADDR_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) when issuing an instr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) set this bit to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) when issuing an instr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) set this bit to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) when polling for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) completion, 1 means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) that instr execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) has been completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) load with 16-bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) to be written in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) transceiver reg for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) write. doesn't matter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) in a read. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) polling for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) completion, field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) "don't care" for write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) and 16-bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) returned by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) transceiver for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) read (if valid bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) is set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define REG_MIF_CFG 0x6210 /* MIF config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) 0 -> select MDIO_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define MIF_CFG_POLL_EN 0x0002 /* enable polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) mechanism. if set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) BB_MODE should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) 0 -> frame mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) used by polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) only meaningful if POLL_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) is set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define MIF_CFG_POLL_REG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) when MDIO_0 is idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) 1 -> tranceiver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) connected to MDIO_0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) when MIF is communicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) w/ MDIO_0 in bit-bang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) mode, this bit indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) the incoming bit stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) during a read op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) when MDIO_1 is idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) 1 -> transceiver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) connected to MDIO_1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) when MIF is communicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) w/ MDIO_1 in bit-bang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) mode, this bit indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) the incoming bit stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) during a read op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) be polled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define MIF_CFG_POLL_PHY_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* 16-bit register used to determine which bits in the POLL_STATUS portion of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * set. DEFAULT: 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define REG_MIF_MASK 0x6214 /* MIF mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* 32-bit register used when in poll mode. auto-cleared after being read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define REG_MIF_STATUS 0x6218 /* MIF status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) the "latest image"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) update of the XCVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) reg being read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define MIF_STATUS_POLL_DATA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) which bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) POLL_DATA field have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) changed since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) MIF_STATUS reg was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) last read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define MIF_STATUS_POLL_STATUS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* 7-bit register has current state for all state machines in the MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define MIF_SM_CONTROL_MASK 0x07 /* control state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /** PCS/Serialink. the following registers are equivalent to the standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * MII management registers except that they're directly mapped in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * Cassini's register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* the auto-negotiation enable bit should be programmed the same at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * the link partner as in the local device to enable auto-negotiation to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * complete. when that bit is reprogrammed, auto-neg/manual config is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * restarted automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * DEFAULT: 0x1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) to MAC interface is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) activated regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) of activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) behaviour same for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) half and full dplx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) restart auto-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) on writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) on writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) through automatic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) link config before it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) can be used. when 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) link can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) w/out any link config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) when done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* DEFAULT: 0x0108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) 0 -> link down. 0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) latched so that 0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) kept until read. read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) 2x to determine if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) link has gone up again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) auto-neg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) from received link code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) word. only valid after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) auto-neg completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) 0 -> auto-negotiation not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) indication that this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) a 1000 Base-X PHY. writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) to it are ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* used during auto-negotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * DEFAULT: 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) 1000 Base-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) 1000 Base-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) symmetric capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) asymmetric capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) to optionally indicate to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) link partner that chip is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) going off-line. bit12 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) get set when signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) detect == FAIL and will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) remain set until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) successful negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* contents updated as a result of autonegotiation. layout and definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * identical to PCS_MII_ADVERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define REG_PCS_MII_LPA 0x900C /* PCS MII link partner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ability reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* DEFAULT: 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define REG_PCS_CFG 0x9010 /* PCS config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define PCS_CFG_EN 0x01 /* enable PCS. must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) 0 when modifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) PCS_MII_ADVERT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) OK. bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) non-resettable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) of optical signal to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) signal detect okay when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) signal is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) measurements. a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) code group is xmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) regularly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) 0x0 = normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) 0x1 = high freq test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) pattern, D21.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) 0x2 = low freq test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pattern, K28.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) 0x3 = reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) negotiation timer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) a few cycles for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* used for diagnostic purposes. bits 20-22 autoclear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) and diagnostic reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) xmission of idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) otherwise, xmission of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) of idle. otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) reception of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) indicates reception of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) Config codes. cycling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) through 0-1 indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) reception of idles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define PCS_SM_LINK_STATE_MASK 0x0001E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define SM_LINK_STATE_UP 0x00016000 /* link state is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) recept of Config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) loss of sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) from OK to FAIL. bit29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) will also be set if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) this is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) receipt of breaklink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) C codes from partner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) C codes w/ 0 content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) received triggering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) start/restart of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) autonegotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) should be sent for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) no longer than 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) initialized. see serdes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) state reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) not received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) achieved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) w/ ack bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) to send C codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) instead of idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) symbols or pkt data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* this register indicates interrupt changes in specific PCS MII status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * PCS_INT may be masked at the ISR level. only a single bit is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * for link status change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) since last read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* control which network interface is used. no more than one bit should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * DEFAULT: none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) MII/GMII is selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) selection between MII and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) GMII is controlled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) XIF_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) 10-bit interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* input to serdes chip or serialink block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) serdes interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) detection. should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) 0x0 for normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) to REFCLK when set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) when clear, receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) clock locks to incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) serial data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * should be 0x0 for normal operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * 0b000 normal operation, PROM address[3:0] selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * 0b010 rxmac req, rx ack, rx tag, rx clk shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * 0b011 txmac req, tx ack, tx tag, tx retry req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * 0b101 R period RX, R period TX, R period HP, R period BIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define PCS_SOS_PROM_ADDR_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* used for diagnostics. this register indicates progress of the SERDES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) * boot up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * 0b00 undergoing reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * 0b01 waiting 500us while lockrefn is asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * 0b10 waiting for comma detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * 0b11 receive data is synchronized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define PCS_SERDES_STATE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* used for diagnostics. indicates number of packets transmitted or received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * counters rollover w/out generating an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * DEFAULT: 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) whether they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) encountered an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /** LocalBus Devices. the following provides run-time access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * Cassini's PROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define REG_SECOND_LOCALBUS_END 0x1FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* entropy device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define ENTROPY_STATUS_DRDY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define ENTROPY_STATUS_BUSY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define ENTROPY_STATUS_CIPHER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define ENTROPY_STATUS_BYPASS_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define ENTROPY_MODE_KEY_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define ENTROPY_MODE_ENCRYPT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define ENTROPY_RESET_DES_IO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define ENTROPY_RESET_STC_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define ENTROPY_RESET_KEY_CACHE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define ENTROPY_RESET_IV 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* phys of interest w/ their special mii registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define PHY_LUCENT_B0 0x00437421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define LUCENT_MII_REG 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define PHY_NS_DP83065 0x20005c78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define DP83065_MII_MEM 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define DP83065_MII_REGD 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define DP83065_MII_REGE 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define PHY_BROADCOM_5411 0x00206071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define PHY_BROADCOM_B0 0x00206050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define BROADCOM_MII_REG4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define BROADCOM_MII_REG5 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define BROADCOM_MII_REG7 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define BROADCOM_MII_REG8 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define CAS_MII_ANNPTR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define CAS_MII_ANNPRR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define CAS_MII_1000_CTRL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define CAS_MII_1000_STATUS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define CAS_MII_1000_EXTEND 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * if autoneg is disabled, here's the table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * BMCR_SPEED100 = 100Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * BMCR_SPEED1000 = 1000Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define CAS_ADVERTISE_1000HALF 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define CAS_ADVERTISE_1000FULL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define CAS_ADVERTISE_PAUSE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* regular lpa register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) /* 1000_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define CAS_LPA_1000HALF 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define CAS_LPA_1000FULL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define CAS_EXTEND_1000XFULL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define CAS_EXTEND_1000XHALF 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define CAS_EXTEND_1000TFULL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define CAS_EXTEND_1000THALF 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* cassini header parser firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) typedef struct cas_hp_inst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) const char *note;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) u16 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) u8 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) u8 soff, snext; /* if match succeeds, new offset and match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) u8 foff, fnext; /* if match fails, new offset and match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /* output info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) u8 outop; /* output opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) u16 outarg; /* output argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) u8 outenab; /* output enable: 0 = not, 1 = if match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) 2 = if !match, 3 = always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) u8 outshift; /* barrel shift right, 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) u16 outmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) } cas_hp_inst_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define OP_EQ 0 /* packet == value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define OP_LT 1 /* packet < value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define OP_GT 2 /* packet > value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define OP_NP 3 /* new packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* output opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define CL_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define LD_FID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define LD_SEQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define LD_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define LD_SAP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define LD_R1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define LD_L3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define LD_SUM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define LD_HDR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #define IM_FID 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define IM_SEQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define IM_SAP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define IM_R1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define IM_CTL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define LD_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define ST_FLG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) /* match setp #s for IP4TCP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define S1_PCKT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define S1_VLAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define S1_CFI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define S1_8023 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define S1_LLC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define S1_LLCc 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define S1_IPV4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #define S1_IPV4c 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define S1_IPV4F 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define S1_TCP44 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define S1_IPV6 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define S1_IPV6L 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define S1_IPV6c 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define S1_TCP64 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define S1_TCPSQ 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define S1_TCPFG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define S1_TCPHL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define S1_TCPHc 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define S1_CLNP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define S1_CLNP2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define S1_DROP 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define S2_HTTP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define S1_ESP4 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) #define S1_AH4 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define S1_ESP6 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define S1_AH6 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define CAS_PROG_IP46TCP4_PREAMBLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) CL_REG, 0x000, 0, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) CL_REG, 0x000, 0, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) CL_REG, 0x000, 0, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) CL_REG, 0x000, 0, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) LD_SAP, 0x100, 3, 0x0, 0xffff}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) LD_SUM, 0x015, 1, 0x0, 0x0000}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) IM_R1, 0x128, 1, 0x0, 0xffff}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) LD_LEN, 0x03f, 1, 0x0, 0xffff}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #ifdef USE_HP_IP46TCP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) CAS_PROG_IP46TCP4_PREAMBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) { "TCP seq", /* DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) IM_CTL, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) IM_CTL, 0x080, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #ifdef HP_IP46TCP4_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) * Alternate table load which excludes HTTP server traffic from reassembly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * It is substantially similar to the basic table, with one extra state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * and a few extra compares. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #ifdef USE_HP_IP46TCP4NOHTTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) CAS_PROG_IP46TCP4_PREAMBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) { "TCP seq", /* DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) LD_R1, 0x205, 3, 0xB, 0xf000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) LD_HDR, 0x0ff, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) CL_REG, 0x002, 3, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) IM_CTL, 0x080, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) IM_CTL, 0x044, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #ifdef HP_IP46TCP4NOHTTP_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* match step #s for IP4FRAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define S3_IPV6c 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define S3_TCP64 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define S3_TCPSQ 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define S3_TCPFG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define S3_TCPHL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define S3_TCPHc 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define S3_FRAG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define S3_FOFF 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define S3_CLNP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #ifdef USE_HP_IP4FRAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static cas_hp_inst_t cas_prog_ip4fragtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) CL_REG, 0x3ff, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) IM_CTL, 0x00a, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) LD_SAP, 0x100, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) LD_SUM, 0x00a, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) LD_LEN, 0x03e, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) LD_SUM, 0x015, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) LD_LEN, 0x03f, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) { "TCP seq", /* DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) LD_R1, 0x205, 3, 0xB, 0xf000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) LD_HDR, 0x0ff, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) LD_SEQ, 0x040, 1, 0xD, 0xfff8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #ifdef HP_IP4FRAG_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * Alternate table which does batching without reassembly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #ifdef USE_HP_IP46TCP4BATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) CAS_PROG_IP46TCP4_PREAMBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) { "TCP seq", /* DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #ifdef HP_IP46TCP4BATCH_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* Workaround for Cassini rev2 descriptor corruption problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * Does batching without reassembly, and sets the SAP to a known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * data pattern for all packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #ifdef USE_HP_WORKAROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) static cas_hp_inst_t cas_prog_workaroundtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) IM_CTL, 0x04a, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) IM_SAP, 0x6AE, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) LD_SUM, 0x00a, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) LD_LEN, 0x03e, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) LD_SUM, 0x015, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) IM_R1, 0x128, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) LD_LEN, 0x03f, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) { "TCP seq", /* DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) LD_R1, 0x205, 3, 0xB, 0xf000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #ifdef HP_WORKAROUND_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) #define CAS_HP_FIRMWARE cas_prog_workaroundtab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) #ifdef USE_HP_ENCRYPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static cas_hp_inst_t cas_prog_encryptiontab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) IM_CTL, 0x00a, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) 00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) CL_REG, 0x000, 0, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) LD_SAP, 0x100, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) LD_SUM, 0x00a, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) LD_LEN, 0x03e, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) LD_SUM, 0x015, 1, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) IM_R1, 0x128, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) { "TCP64?",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) 0x03f, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) { "TCP seq", /* 14:DADDR should point to dest port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) LD_R1, 0x205, 3, 0xB, 0xf000} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) IM_CTL, 0x001, 3, 0x0, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) CL_REG, 0x002, 3, 0x0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) IM_CTL, 0x080, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) IM_CTL, 0x044, 3, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) { "IPV4 ESP encrypted?", /* S1_ESP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) 0x021, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) { "IPV4 AH encrypted?", /* S1_AH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) 0x021, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) { "IPV6 ESP encrypted?", /* S1_ESP6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) 0x021, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) { "IPV6 AH encrypted?", /* S1_AH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) 0x021, 1, 0x0, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #ifdef HP_ENCRYPT_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) #define CAS_HP_FIRMWARE cas_prog_encryptiontab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static cas_hp_inst_t cas_prog_null[] = { {NULL} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #ifdef HP_NULL_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define CAS_HP_FIRMWARE cas_prog_null
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) /* phy types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define CAS_PHY_UNKNOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #define CAS_PHY_SERDES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define CAS_PHY_MII_MDIO0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define CAS_PHY_MII_MDIO1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) * is the actual size. the default index for the various rings is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) * 8. NOTE: there a bunch of alignment constraints for the rings. to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) * deal with that, i just allocate rings to create the desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) * alignment. here are the constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) * RX DESC and COMP rings must be 8KB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) * TX DESC must be 2KB aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) * if you change the numbers, be cognizant of how the alignment will change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) * in INIT_BLOCK as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) #define TX_DESC_RING_INDEX 4 /* 512 = 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #define RX_DESC_RING_INDEX 4 /* 512 = 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) #define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) #error TX_DESC_RING_INDEX must be between 0 and 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #error RX_DESC_RING_INDEX must be between 0 and 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #error RX_COMP_RING_INDEX must be between 0 and 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) #define N_TX_RINGS MAX_TX_RINGS /* for QoS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #define N_RX_DESC_RINGS MAX_RX_DESC_RINGS /* 1 for ipsec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) #define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* number of flows that can go through re-assembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) #define N_RX_FLOWS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /* convert values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) TX_CFG_DESC_RINGN_SHIFT(y)) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) TX_CFG_DESC_RINGN_MASK(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define CAS_MIN_PAGE_SHIFT 11 /* 2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define CAS_MAX_PAGE_SHIFT 14 /* 16384 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) bytes. 0 - 9256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #define TX_DESC_BUFLEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) #define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) of bytes to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) skipped before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) csum calc begins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) value must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) #define TX_DESC_CSUM_START_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) byte offset w/in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) the pkt for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) 1st csum byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) must be > 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define TX_DESC_CSUM_STUFF_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) #define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) #define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) CRC will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) inserted into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) outgoing frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) struct cas_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) __le64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) __le64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /* descriptor ring for free buffers contains page-sized buffers. the index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * value is not used by the hw in any way. it's just stored and returned in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) * the completion ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) struct cas_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) __le64 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) __le64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* received packets are put on the completion ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define RX_COMP1_DATA_SIZE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) #define RX_COMP1_DATA_OFF_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) #define RX_COMP1_DATA_INDEX_SHIFT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #define RX_COMP1_SKIP_SHIFT 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) #define RX_COMP1_TYPE_SHIFT 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #define RX_COMP2_NEXT_INDEX_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define RX_COMP2_HDR_SIZE_SHIFT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define RX_COMP2_HDR_OFF_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define RX_COMP2_HDR_INDEX_SHIFT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #define RX_COMP3_CSUM_START_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #define RX_COMP3_FLOWID_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) #define RX_COMP3_OPCODE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define RX_COMP3_LOAD_BAL_SHIFT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) #define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) #define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) #define RX_COMP3_SAP_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) /* word 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define RX_COMP4_TCP_CSUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define RX_COMP4_PKT_LEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define RX_COMP4_PERFECT_MATCH_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) #define RX_COMP4_ZERO 0x0000080000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #define RX_COMP4_HASH_VAL_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define RX_COMP4_BAD 0x4000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /* we encode the following: ring/index/release. only 14 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) * are usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) * MAX_RX_DESC_RINGS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define RX_INDEX_NUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define RX_INDEX_RING_MASK 0x0000000000001000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define RX_INDEX_RING_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define RX_INDEX_RELEASE 0x0000000000002000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) struct cas_rx_comp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) __le64 word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) __le64 word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) __le64 word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) __le64 word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) enum link_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) link_down = 0, /* No link, will retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) link_aneg, /* Autoneg in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) link_force_try, /* Try Forced link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) link_force_ret, /* Forced mode worked, retrying autoneg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) link_force_ok, /* Stay in forced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) link_up /* Link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) typedef struct cas_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct page *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) int used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) } cas_page_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* some alignment constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * TX COMPWB must be 8-byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) * to accomplish this, here's what we do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) * INIT_BLOCK_RX_COMP = 64k (already aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) * INIT_BLOCK_RX_DESC = 8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) * INIT_BLOCK_TX = 8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) * INIT_BLOCK_RX1_DESC = 8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) * TX COMPWB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) struct cas_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) __le64 tx_compwb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) /* tiny buffers to deal with target abort issue. we allocate a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) * over so that we don't have target abort issues with these buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) * as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) #define TX_TINY_BUF_LEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) struct cas_tiny_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) int nbufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) int used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct cas {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) spinlock_t lock; /* for most bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) spinlock_t rx_inuse_lock; /* rx inuse list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) spinlock_t rx_spare_lock; /* rx spare list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) int rx_old[N_RX_DESC_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) int rx_last[N_RX_DESC_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* Set when chip is actually in operational state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) * (ie. not power managed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) int hw_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) int opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) struct mutex pm_mutex; /* open/close/suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) struct cas_init_block *init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) struct cas_tx_desc *init_txds[MAX_TX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) /* we use sk_buffs for tx and pages for rx. the rx skbuffs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) * are there for flow re-assembly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) struct sk_buff_head rx_flows[N_RX_FLOWS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) struct list_head rx_spare_list, rx_inuse_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) int rx_spares_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /* for small packets when copying would be quicker than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) u8 *tx_tiny_bufs[N_TX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) struct net_device_stats net_stats[N_TX_RINGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) u32 pci_cfg[64 >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) u8 pci_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) int phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) int phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) #define CAS_FLAG_1000MB_CAP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) #define CAS_FLAG_REG_PLUS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) #define CAS_FLAG_TARGET_ABORT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #define CAS_FLAG_SATURN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #define CAS_FLAG_RXD_POST_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) #define CAS_FLAG_RXD_POST_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) CAS_FLAG_RXD_POST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #define CAS_FLAG_ENTROPY_DEV 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) #define CAS_FLAG_NO_HW_CSUM 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) u32 cas_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) int packet_min; /* minimum packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) int tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) int rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) int rx_pause_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) int rx_pause_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) int crc_size; /* 4 if half-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) int pci_irq_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) int min_frame_size; /* for tx fifo workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* page size allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) int page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) int mtu_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) u32 mac_rx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) /* Autoneg & PHY control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) int link_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) int link_fcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) enum link_state lstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) struct timer_list link_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) int timer_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) atomic_t reset_task_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) atomic_t reset_task_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) atomic_t reset_task_pending_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) atomic_t reset_task_pending_spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) atomic_t reset_task_pending_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) /* Link-down problem workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) #define LINK_TRANSITION_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) #define LINK_TRANSITION_ON_FAILURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) #define LINK_TRANSITION_STILL_FAILED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) #define LINK_TRANSITION_LINK_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) #define LINK_TRANSITION_LINK_CONFIG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) #define LINK_TRANSITION_LINK_DOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #define LINK_TRANSITION_REQUESTED_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) int link_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) int link_transition_jiffies_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) unsigned long link_transition_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) /* Tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) u8 orig_cacheline_size; /* value when loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) #define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /* Diagnostic counters and state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) int casreg_len; /* reg-space size for dumping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) u64 pause_entered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) u16 pause_last_time_recvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) /* Firmware Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) u16 fw_load_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) u32 fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) u8 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) #define CAS_ALIGN(addr, align) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) #define RX_FIFO_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #define EXPANSION_ROM_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #define CAS_MC_EXACT_MATCH_SIZE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) #define CAS_MC_HASH_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) CAS_MC_HASH_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) #define TX_TARGET_ABORT_LEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) #define RX_SWIVEL_OFF_VAL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) #define RX_BLANK_INTR_PKT_VAL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) #define RX_BLANK_INTR_TIME_VAL 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) #define HP_TCP_THRESH_VAL 1530 /* reduce to enable reassembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #endif /* _CASSINI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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