Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007,2008  SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  ***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _SMSC9420_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _SMSC9420_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TX_RING_SIZE			(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define RX_RING_SIZE			(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* interrupt deassertion in multiples of 10us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define INT_DEAS_TIME			(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NAPI_WEIGHT			(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SMSC_BAR			(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Register set is duplicated for BE at an offset of 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LAN9420_CPSR_ENDIAN_OFFSET	(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LAN9420_CPSR_ENDIAN_OFFSET	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_VENDOR_ID_9420		(0x1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCI_DEVICE_ID_9420		(0xE420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LAN_REGISTER_EXTENT		(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SMSC9420_EEPROM_SIZE		((u32)11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SMSC9420_EEPROM_MAGIC		(0x9420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PKT_BUF_SZ			(VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* DMA Controller Control and Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BUS_MODE			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BUS_MODE_SWR_			(BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BUS_MODE_DMA_BURST_LENGTH_1	(BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BUS_MODE_DMA_BURST_LENGTH_2	(BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BUS_MODE_DMA_BURST_LENGTH_4	(BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BUS_MODE_DMA_BURST_LENGTH_8	(BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BUS_MODE_DMA_BURST_LENGTH_16	(BIT(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BUS_MODE_DMA_BURST_LENGTH_32	(BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BUS_MODE_DBO_			(BIT(20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TX_POLL_DEMAND			(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RX_POLL_DEMAND			(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RX_BASE_ADDR			(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TX_BASE_ADDR			(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DMAC_STATUS			(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DMAC_STS_TS_			(7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DMAC_STS_RS_ 			(7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DMAC_STS_NIS_			(BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DMAC_STS_AIS_			(BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DMAC_STS_RWT_			(BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DMAC_STS_RXPS_			(BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DMAC_STS_RXBU_			(BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DMAC_STS_RX_			(BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DMAC_STS_TXUNF_			(BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DMAC_STS_TXBU_			(BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DMAC_STS_TXPS_			(BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DMAC_STS_TX_			(BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DMAC_CONTROL			(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DMAC_CONTROL_TTM_		(BIT(22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DMAC_CONTROL_SF_		(BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DMAC_CONTROL_ST_		(BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DMAC_CONTROL_OSF_		(BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DMAC_CONTROL_SR_		(BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DMAC_INTR_ENA			(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DMAC_INTR_ENA_NIS_		(BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DMAC_INTR_ENA_AIS_		(BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DMAC_INTR_ENA_RWT_		(BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DMAC_INTR_ENA_RXPS_		(BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DMAC_INTR_ENA_RXBU_		(BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DMAC_INTR_ENA_RX_		(BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DMAC_INTR_ENA_TXBU_		(BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DMAC_INTR_ENA_TXPS_		(BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DMAC_INTR_ENA_TX_		(BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MISS_FRAME_CNTR			(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TX_BUFF_ADDR			(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define RX_BUFF_ADDR			(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* Transmit Descriptor Bit Defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TDES0_OWN_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TDES0_ERROR_SUMMARY_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TDES0_LOSS_OF_CARRIER_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TDES0_NO_CARRIER_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TDES0_LATE_COLLISION_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TDES0_EXCESSIVE_COLLISIONS_	(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TDES0_HEARTBEAT_FAIL_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TDES0_COLLISION_COUNT_MASK_	(0x00000078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TDES0_COLLISION_COUNT_SHFT_	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TDES0_EXCESSIVE_DEFERRAL_	(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TDES0_DEFERRED_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TDES1_IC_			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TDES1_LS_			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TDES1_FS_			0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TDES1_TXCSEN_			0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TDES1_TER_			(BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TDES1_TCH_			0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Receive Descriptor 0 Bit Defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RDES0_OWN_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RDES0_FRAME_LENGTH_MASK_	(0x07FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RDES0_FRAME_LENGTH_SHFT_	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RDES0_ERROR_SUMMARY_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RDES0_DESCRIPTOR_ERROR_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RDES0_LENGTH_ERROR_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RDES0_RUNT_FRAME_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RDES0_MULTICAST_FRAME_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RDES0_FIRST_DESCRIPTOR_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RDES0_LAST_DESCRIPTOR_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RDES0_FRAME_TOO_LONG_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RDES0_COLLISION_SEEN_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RDES0_FRAME_TYPE_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RDES0_WATCHDOG_TIMEOUT_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RDES0_MII_ERROR_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RDES0_DRIBBLING_BIT_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RDES0_CRC_ERROR_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Receive Descriptor 1 Bit Defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RDES1_RER_			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*       MAC Control and Status Registers      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MAC_CR				(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MAC_CR_RXALL_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAC_CR_DIS_RXOWN_		(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MAC_CR_LOOPBK_			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MAC_CR_FDPX_			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MAC_CR_MCPAS_			(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MAC_CR_PRMS_			(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MAC_CR_INVFILT_			(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MAC_CR_PASSBAD_			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAC_CR_HFILT_			(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MAC_CR_HPFILT_			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MAC_CR_LCOLL_			(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAC_CR_DIS_BCAST_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MAC_CR_DIS_RTRY_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MAC_CR_PADSTR_			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MAC_CR_BOLMT_MSK		(0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MAC_CR_MFCHK_			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MAC_CR_TXEN_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MAC_CR_RXEN_			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ADDRH				(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ADDRL				(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HASHH				(0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HASHL				(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MII_ACCESS			(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MII_ACCESS_MII_BUSY_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MII_ACCESS_MII_WRITE_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MII_ACCESS_MII_READ_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MII_ACCESS_INDX_MSK_		(0x000007C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MII_ACCESS_PHYADDR_MSK_		(0x0000F8C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MII_ACCESS_INDX_SHFT_CNT	(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MII_ACCESS_PHYADDR_SHFT_CNT	(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MII_DATA			(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FLOW				(0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define VLAN1				(0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VLAN2				(0xA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WUFF				(0xA8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define WUCSR				(0xAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define COE_CR				(0xB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TX_COE_EN			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RX_COE_MODE			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RX_COE_EN			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*     System Control and Status Registers     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /***********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ID_REV				(0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define INT_CTL				(0xC4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define INT_CTL_SW_INT_EN_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define INT_CTL_SBERR_INT_EN_		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define INT_CTL_MBERR_INT_EN_		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define INT_CTL_GPT_INT_EN_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define INT_CTL_PHY_INT_EN_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define INT_CTL_WAKE_INT_EN_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define INT_STAT			(0xC8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define INT_STAT_SW_INT_		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define INT_STAT_MBERR_INT_		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define INT_STAT_SBERR_INT_		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define INT_STAT_GPT_INT_		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define INT_STAT_PHY_INT_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define INT_STAT_WAKE_INT_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define INT_STAT_DMAC_INT_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define INT_CFG				(0xCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define INT_CFG_IRQ_INT_		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define INT_CFG_IRQ_EN_			(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define INT_CFG_INT_DEAS_CLR_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define INT_CFG_INT_DEAS_MASK		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GPIO_CFG			(0xD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GPIO_CFG_LED_3_			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GPIO_CFG_LED_2_			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GPIO_CFG_LED_1_			(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GPIO_CFG_EEPR_EN_		(0x00700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GPT_CFG				(0xD4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GPT_CFG_TIMER_EN_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GPT_CNT				(0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define BUS_CFG				(0xDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define BUS_CFG_RXTXWEIGHT_1_1		(0 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BUS_CFG_RXTXWEIGHT_2_1		(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define BUS_CFG_RXTXWEIGHT_3_1		(2 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BUS_CFG_RXTXWEIGHT_4_1		(3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PMT_CTRL			(0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FREE_RUN			(0xF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define E2P_CMD				(0xF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define E2P_CMD_EPC_BUSY_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define E2P_CMD_EPC_CMD_		(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define E2P_CMD_EPC_CMD_READ_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define E2P_CMD_EPC_CMD_EWDS_		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define E2P_CMD_EPC_CMD_WRAL_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define E2P_CMD_EPC_CMD_ERASE_		(0x50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define E2P_CMD_EPC_CMD_ERAL_		(0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define E2P_CMD_EPC_CMD_RELOAD_		(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define E2P_CMD_EPC_TIMEOUT_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define E2P_CMD_MAC_ADDR_LOADED_	(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define E2P_CMD_EPC_ADDR_		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define E2P_DATA			(0xFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define E2P_DATA_EEPROM_DATA_		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif /* _SMSC9420_H */