^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007,2008 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "smsc9420.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "smsc9420"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_MDIONAME "smsc9420-mdio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_DESCRIPTION "SMSC LAN9420 driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_VERSION "1.01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct smsc9420_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 buffer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 buffer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct smsc9420_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct smsc9420_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct smsc9420_dma_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct smsc9420_dma_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct smsc9420_ring_info *tx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct smsc9420_ring_info *rx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dma_addr_t rx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_addr_t tx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int tx_ring_head, tx_ring_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int rx_ring_head, rx_ring_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spinlock_t int_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spinlock_t phy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bool software_irq_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool rx_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int last_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int last_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct pci_device_id smsc9420_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static uint smsc_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static uint debug = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param(debug, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(debug, "debug level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ioread32(pd->ioaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite32(value, pd->ioaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* to ensure PCI write completion, we must perform a PCI read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) smsc9420_reg_read(pd, ID_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int i, reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_lock_irqsave(&pd->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) netif_warn(pd, drv, pd->dev, "MII is busy???\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* set the address, index & direction (read from PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MII_ACCESS_MII_READ_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) smsc9420_reg_write(pd, MII_ACCESS, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* wait for read to complete with 50us timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!(smsc9420_reg_read(pd, MII_ACCESS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MII_ACCESS_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg = (u16)smsc9420_reg_read(pd, MII_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) spin_unlock_irqrestore(&pd->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int i, reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spin_lock_irqsave(&pd->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) netif_warn(pd, drv, pd->dev, "MII is busy???\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* put the data to write in the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) smsc9420_reg_write(pd, MII_DATA, (u32)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* set the address, index & direction (write to PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MII_ACCESS_MII_WRITE_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) smsc9420_reg_write(pd, MII_ACCESS, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* wait for write to complete with 50us timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!(smsc9420_reg_read(pd, MII_ACCESS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MII_ACCESS_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) spin_unlock_irqrestore(&pd->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Returns hash bit number for given MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * 01 00 5E 00 00 01 -> returns bit number 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u32 smsc9420_hash(u8 addr[ETH_ALEN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BUG_ON(!pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) smsc9420_reg_write(pd, E2P_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ethtool_drvinfo *drvinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct smsc9420_pdata *pd = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sizeof(drvinfo->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct smsc9420_pdata *pd = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return pd->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct smsc9420_pdata *pd = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pd->msg_enable = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int smsc9420_ethtool_getregslen(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* all smsc9420 registers plus all phy registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0x100 + (32 * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regs->version = smsc9420_reg_read(pd, ID_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < 0x100; i += (sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) data[j++] = smsc9420_reg_read(pd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) // cannot read phy registers if the net device is down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!phy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i <= 31; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) phy_dev->mdio.addr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) temp &= ~GPIO_CFG_EEPR_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) smsc9420_reg_write(pd, GPIO_CFG, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 e2cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) netif_warn(pd, hw, pd->dev, "Busy at start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) e2cmd = op | E2P_CMD_EPC_BUSY_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) smsc9420_reg_write(pd, E2P_CMD, e2cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) e2cmd = smsc9420_reg_read(pd, E2P_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) netif_info(pd, hw, pd->dev, "TIMED OUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) netif_info(pd, hw, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "Error occurred during eeprom operation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 address, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 op = E2P_CMD_EPC_CMD_READ_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = smsc9420_eeprom_send_cmd(pd, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) data[address] = smsc9420_reg_read(pd, E2P_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = smsc9420_eeprom_send_cmd(pd, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) op = E2P_CMD_EPC_CMD_WRITE_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) smsc9420_reg_write(pd, E2P_DATA, (u32)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = smsc9420_eeprom_send_cmd(pd, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return SMSC9420_EEPROM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 eeprom_data[SMSC9420_EEPROM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) smsc9420_eeprom_enable_access(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) eeprom->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memcpy(data, &eeprom_data[eeprom->offset], len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) eeprom->magic = SMSC9420_EEPROM_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) eeprom->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) smsc9420_eeprom_enable_access(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Single byte write, according to man page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) eeprom->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct ethtool_ops smsc9420_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .get_drvinfo = smsc9420_ethtool_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .get_msglevel = smsc9420_ethtool_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .set_msglevel = smsc9420_ethtool_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .nway_reset = phy_ethtool_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .get_eeprom = smsc9420_ethtool_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .set_eeprom = smsc9420_ethtool_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .get_regs_len = smsc9420_ethtool_getregslen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .get_regs = smsc9420_ethtool_getregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .get_ts_info = ethtool_op_get_ts_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .get_link_ksettings = phy_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .set_link_ksettings = phy_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Sets the device MAC address to dev_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void smsc9420_set_mac_address(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 *dev_addr = dev->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (dev_addr[1] << 8) | dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) smsc9420_reg_write(pd, ADDRH, mac_high16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) smsc9420_reg_write(pd, ADDRL, mac_low32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void smsc9420_check_mac_address(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Check if mac address has been specified when bringing interface up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) smsc9420_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) netif_dbg(pd, probe, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "MAC Address is specified by configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Try reading mac address from device. if EEPROM is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * it will already have been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev->dev_addr[0] = (u8)(mac_low32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev->dev_addr[1] = (u8)(mac_low32 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev->dev_addr[2] = (u8)(mac_low32 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev->dev_addr[3] = (u8)(mac_low32 >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev->dev_addr[4] = (u8)(mac_high16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev->dev_addr[5] = (u8)(mac_high16 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* eeprom values are valid so use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) netif_dbg(pd, probe, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "Mac Address is read from EEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* eeprom values are invalid, generate random MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) smsc9420_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) netif_dbg(pd, probe, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "MAC Address is set to random\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 dmac_control, mac_cr, dma_intr_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* disable TX DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dmac_control &= (~DMAC_CONTROL_ST_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Wait max 10ms for transmit process to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* ACK Tx DMAC stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* mask TX DMAC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* stop MAC TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) smsc9420_reg_write(pd, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) BUG_ON(!pd->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!pd->tx_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct sk_buff *skb = pd->tx_buffers[i].skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BUG_ON(!pd->tx_buffers[i].mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dma_unmap_single(&pd->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pd->tx_buffers[i].mapping, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pd->tx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pd->tx_ring[i].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pd->tx_ring[i].buffer1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pd->tx_ring[i].buffer2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) kfree(pd->tx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pd->tx_buffers = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pd->tx_ring_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pd->tx_ring_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) BUG_ON(!pd->rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!pd->rx_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (pd->rx_buffers[i].skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_kfree_skb_any(pd->rx_buffers[i].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (pd->rx_buffers[i].mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dma_unmap_single(&pd->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pd->rx_buffers[i].mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pd->rx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pd->rx_ring[i].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pd->rx_ring[i].buffer1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pd->rx_ring[i].buffer2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) kfree(pd->rx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pd->rx_buffers = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pd->rx_ring_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pd->rx_ring_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 mac_cr, dmac_control, dma_intr_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* mask RX DMAC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* stop RX MAC prior to stoping DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) smsc9420_reg_write(pd, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* stop RX DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dmac_control &= (~DMAC_CONTROL_SR_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* wait up to 10ms for receive to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) netif_warn(pd, ifdown, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "RX DMAC did not stop! timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* ACK the Rx DMAC stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static irqreturn_t smsc9420_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct smsc9420_pdata *pd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 int_cfg, int_sts, int_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ulong flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) BUG_ON(!pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) BUG_ON(!pd->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int_cfg = smsc9420_reg_read(pd, INT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* check if it's our interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int_sts = smsc9420_reg_read(pd, INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 ints_to_clear = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (status & DMAC_STS_TX_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) netif_wake_queue(pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (status & DMAC_STS_RX_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* mask RX DMAC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) napi_schedule(&pd->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ints_to_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* mask software interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int_ctl = smsc9420_reg_read(pd, INT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int_ctl &= (~INT_CTL_SW_INT_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) smsc9420_reg_write(pd, INT_CTL, int_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pd->software_irq_signal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* to ensure PCI write completion, we must perform a PCI read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static void smsc9420_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) const int irq = pd->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) smsc9420_isr(0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #endif /* CONFIG_NET_POLL_CONTROLLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) smsc9420_reg_read(pd, BUS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int smsc9420_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 int_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ulong flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) BUG_ON(!pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) BUG_ON(!dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* disable master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) netif_tx_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) napi_disable(&pd->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) smsc9420_stop_tx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) smsc9420_free_tx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) smsc9420_stop_rx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) smsc9420_free_rx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) free_irq(pd->pdev->irq, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) smsc9420_dmac_soft_reset(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) phy_stop(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) phy_disconnect(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mdiobus_unregister(pd->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mdiobus_free(pd->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (desc_status & RDES0_DESCRIPTOR_ERROR_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else if (desc_status & RDES0_CRC_ERROR_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (desc_status & RDES0_FIRST_DESCRIPTOR_))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (desc_status & RDES0_MULTICAST_FRAME_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev->stats.multicast++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) const u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct net_device *dev = pd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) >> RDES0_FRAME_LENGTH_SHFT_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* remove crc from packet lendth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) packet_length -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (pd->rx_csum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) packet_length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->stats.rx_bytes += packet_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pd->rx_buffers[index].mapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) skb = pd->rx_buffers[index].skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pd->rx_buffers[index].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (pd->rx_csum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) NET_IP_ALIGN + packet_length + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) put_unaligned_le16(hw_csum, &skb->csum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) skb_reserve(skb, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) skb_put(skb, packet_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BUG_ON(pd->rx_buffers[index].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) BUG_ON(pd->rx_buffers[index].mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (dma_mapping_error(&pd->pdev->dev, mapping)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pd->rx_buffers[index].skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pd->rx_buffers[index].mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pd->rx_ring[index].status = RDES0_OWN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) while (pd->rx_ring_tail != pd->rx_ring_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct smsc9420_pdata *pd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) container_of(napi, struct smsc9420_pdata, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct net_device *dev = pd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 drop_frame_cnt, dma_intr_ena, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (work_done = 0; work_done < budget; work_done++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) status = pd->rx_ring[pd->rx_ring_head].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* stop if DMAC owns this dma descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (status & RDES0_OWN_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) smsc9420_rx_count_stats(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) smsc9420_alloc_new_rx_buffers(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev->stats.rx_dropped +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Kick RXDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) napi_complete_done(&pd->napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* re-enable RX DMA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) TDES0_EXCESSIVE_COLLISIONS_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev->stats.tx_bytes += (length & 0x7FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev->stats.collisions += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev->stats.collisions +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (status & TDES0_COLLISION_COUNT_MASK_) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TDES0_COLLISION_COUNT_SHFT_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev->stats.tx_heartbeat_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Check for completed dma transfers, update stats and free skbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void smsc9420_complete_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) while (pd->tx_ring_tail != pd->tx_ring_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int index = pd->tx_ring_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 status, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) status = pd->tx_ring[index].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) length = pd->tx_ring[index].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Check if DMA still owns this descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (unlikely(TDES0_OWN_ & status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) smsc9420_tx_update_stats(dev, status, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) BUG_ON(!pd->tx_buffers[index].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) BUG_ON(!pd->tx_buffers[index].mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma_unmap_single(&pd->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pd->tx_buffers[index].mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) pd->tx_buffers[index].skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pd->tx_buffers[index].mapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dev_kfree_skb_any(pd->tx_buffers[index].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pd->tx_buffers[index].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pd->tx_ring[index].buffer1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int index = pd->tx_ring_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u32 tmp_desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) bool about_to_take_last_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) smsc9420_complete_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) BUG_ON(pd->tx_buffers[index].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) BUG_ON(pd->tx_buffers[index].mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (dma_mapping_error(&pd->pdev->dev, mapping)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) netif_warn(pd, tx_err, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "pci_map_single failed, dropping packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pd->tx_buffers[index].skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pd->tx_buffers[index].mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (unlikely(about_to_take_last_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) tmp_desc1 |= TDES1_IC_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) netif_stop_queue(pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* check if we are at the last descriptor and need to set EOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (unlikely(index == (TX_RING_SIZE - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) tmp_desc1 |= TDES1_TER_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) pd->tx_ring[index].buffer1 = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) pd->tx_ring[index].length = tmp_desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* increment head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* assign ownership to DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pd->tx_ring[index].status = TDES0_OWN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* kick the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev->stats.rx_dropped +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static void smsc9420_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mac_cr |= MAC_CR_PRMS_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) mac_cr &= (~MAC_CR_MCPAS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mac_cr &= (~MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) } else if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) mac_cr &= (~MAC_CR_PRMS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mac_cr |= MAC_CR_MCPAS_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) mac_cr &= (~MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) } else if (!netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) u32 hash_lo = 0, hash_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 bit_num = smsc9420_hash(ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 mask = 1 << (bit_num & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (bit_num & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) hash_hi |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) hash_lo |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) smsc9420_reg_write(pd, HASHH, hash_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) smsc9420_reg_write(pd, HASHL, hash_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mac_cr &= (~MAC_CR_PRMS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mac_cr &= (~MAC_CR_MCPAS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mac_cr |= MAC_CR_HPFILT_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) smsc9420_reg_write(pd, HASHH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) smsc9420_reg_write(pd, HASHL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) mac_cr &= (~MAC_CR_PRMS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mac_cr &= (~MAC_CR_MCPAS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mac_cr &= (~MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) smsc9420_reg_write(pd, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct net_device *dev = pd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u32 flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (phy_dev->duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u16 rmtadv = phy_read(phy_dev, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (cap & FLOW_CTRL_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) flow = 0xFFFF0002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cap & FLOW_CTRL_RX ? "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cap & FLOW_CTRL_TX ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) netif_info(pd, link, pd->dev, "half duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) smsc9420_reg_write(pd, FLOW, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Update link mode if anything has changed. Called periodically when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * PHY is in polling mode, even if nothing has changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void smsc9420_phy_adjust_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (phy_dev->duplex != pd->last_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (phy_dev->duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) netif_dbg(pd, link, pd->dev, "full duplex mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mac_cr |= MAC_CR_FDPX_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) netif_dbg(pd, link, pd->dev, "half duplex mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mac_cr &= ~MAC_CR_FDPX_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) smsc9420_reg_write(pd, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) smsc9420_phy_update_flowcontrol(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pd->last_duplex = phy_dev->duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) carrier = netif_carrier_ok(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (carrier != pd->last_carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) netif_dbg(pd, link, pd->dev, "carrier OK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) netif_dbg(pd, link, pd->dev, "no carrier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pd->last_carrier = carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int smsc9420_mii_probe(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct phy_device *phydev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) BUG_ON(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Device only supports internal PHY at address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) phydev = mdiobus_get_phy(pd->mii_bus, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (!phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) netdev_err(dev, "no PHY found at address 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) phydev = phy_connect(dev, phydev_name(phydev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (IS_ERR(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) netdev_err(dev, "Could not attach to PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return PTR_ERR(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) phy_set_max_speed(phydev, SPEED_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* mask with MAC supported features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) phy_support_asym_pause(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) phy_attached_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) pd->last_duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pd->last_carrier = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int smsc9420_mii_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) pd->mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (!pd->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) goto err_out_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pd->mii_bus->name = DRV_MDIONAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) (pd->pdev->bus->number << 8) | pd->pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pd->mii_bus->priv = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pd->mii_bus->read = smsc9420_mii_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pd->mii_bus->write = smsc9420_mii_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Mask all PHYs except ID 1 (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pd->mii_bus->phy_mask = ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (mdiobus_register(pd->mii_bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) goto err_out_free_bus_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (smsc9420_mii_probe(dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) goto err_out_unregister_bus_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) err_out_unregister_bus_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) mdiobus_unregister(pd->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) err_out_free_bus_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mdiobus_free(pd->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) err_out_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) BUG_ON(!pd->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) sizeof(struct smsc9420_ring_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (!pd->tx_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Initialize the TX Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pd->tx_buffers[i].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pd->tx_buffers[i].mapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) pd->tx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pd->tx_ring[i].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pd->tx_ring[i].buffer1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pd->tx_ring[i].buffer2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pd->tx_ring_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pd->tx_ring_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) BUG_ON(!pd->rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sizeof(struct smsc9420_ring_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (pd->rx_buffers == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* initialize the rx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) pd->rx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) pd->rx_ring[i].length = PKT_BUF_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pd->rx_ring[i].buffer2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pd->rx_buffers[i].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pd->rx_buffers[i].mapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* now allocate the entire ring of skbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (smsc9420_alloc_rx_buffer(pd, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) netif_warn(pd, ifup, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "failed to allocate rx skb %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto out_free_rx_skbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pd->rx_ring_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pd->rx_ring_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) smsc9420_reg_read(pd, VLAN1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (pd->rx_csum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Enable RX COE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) smsc9420_reg_write(pd, COE_CR, coe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) out_free_rx_skbs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) smsc9420_free_rx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int smsc9420_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) const int irq = pd->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int result = 0, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (!is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) netif_warn(pd, ifup, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "dev_addr is not a valid MAC address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) result = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* disable, mask and acknowledge all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) smsc9420_reg_write(pd, INT_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) smsc9420_dmac_soft_reset(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* make sure MAC_CR is sane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) smsc9420_reg_write(pd, MAC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) smsc9420_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* Configure GPIO pins to drive LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) smsc9420_reg_write(pd, GPIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) bus_mode |= BUS_MODE_DBO_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) smsc9420_reg_write(pd, BUS_MODE, bus_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* set bus master bridge arbitration priority for Rx and TX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) smsc9420_reg_write(pd, DMAC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* test the IRQ connection to the ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pd->software_irq_signal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* configure interrupt deassertion timer and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* unmask software interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) smsc9420_reg_write(pd, INT_CTL, int_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (pd->software_irq_signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!pd->software_irq_signal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) goto out_free_irq_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) result = smsc9420_alloc_tx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) netif_warn(pd, ifup, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "Failed to Initialize tx dma ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) goto out_free_irq_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) result = smsc9420_alloc_rx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) netif_warn(pd, ifup, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) "Failed to Initialize rx dma ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto out_free_tx_ring_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) result = smsc9420_mii_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) goto out_free_rx_ring_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Bring the PHY up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) phy_start(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) napi_enable(&pd->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* start tx and rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) smsc9420_reg_write(pd, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dma_intr_ena |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) smsc9420_pci_flush_write(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) out_free_rx_ring_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) smsc9420_free_rx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) out_free_tx_ring_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) smsc9420_free_tx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) out_free_irq_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) free_irq(irq, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) out_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int __maybe_unused smsc9420_suspend(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct smsc9420_pdata *pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u32 int_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ulong flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) spin_lock_irqsave(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) smsc9420_reg_write(pd, INT_CFG, int_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) spin_unlock_irqrestore(&pd->int_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) netif_tx_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) smsc9420_stop_tx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) smsc9420_free_tx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) napi_disable(&pd->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) smsc9420_stop_rx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) smsc9420_free_rx_ring(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) free_irq(pd->pdev->irq, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) device_wakeup_disable(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static int __maybe_unused smsc9420_resume(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) pci_set_master(to_pci_dev(dev_d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) device_wakeup_disable(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* FIXME: gross. It looks like ancient PM relic.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) err = smsc9420_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const struct net_device_ops smsc9420_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .ndo_open = smsc9420_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ndo_stop = smsc9420_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .ndo_start_xmit = smsc9420_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .ndo_get_stats = smsc9420_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .ndo_set_rx_mode = smsc9420_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .ndo_do_ioctl = phy_do_ioctl_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .ndo_poll_controller = smsc9420_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #endif /* CONFIG_NET_POLL_CONTROLLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct smsc9420_pdata *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) void __iomem *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u32 id_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* First do the PCI initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) result = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (unlikely(result)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) pr_err("Cannot enable smsc9420\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) dev = alloc_etherdev(sizeof(*pd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) goto out_disable_pci_device_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) netdev_err(dev, "Cannot find PCI device base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) goto out_free_netdev_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if ((pci_request_regions(pdev, DRV_NAME))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) goto out_free_netdev_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) netdev_err(dev, "No usable DMA configuration, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto out_free_regions_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pci_resource_len(pdev, SMSC_BAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (!virt_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) netdev_err(dev, "Cannot map device registers, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) goto out_free_regions_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* registers are double mapped with 0 offset for LE and 0x200 for BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* pci descriptors are created in the PCI consistent area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pd->rx_ring = dma_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) &pd->rx_dma_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!pd->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) goto out_free_io_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* descriptors are aligned due to the nature of pci_alloc_consistent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) pd->tx_dma_addr = pd->rx_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) pd->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) pd->ioaddr = virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) pd->msg_enable = smsc_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) pd->rx_csum = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) id_rev = smsc9420_reg_read(pd, ID_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) switch (id_rev & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case 0x94200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) netif_info(pd, probe, pd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) goto out_free_dmadesc_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) smsc9420_dmac_soft_reset(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) smsc9420_eeprom_reload(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) smsc9420_check_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev->netdev_ops = &smsc9420_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dev->ethtool_ops = &smsc9420_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) result = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) netif_warn(pd, probe, pd->dev, "error %i registering device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) goto out_free_dmadesc_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) spin_lock_init(&pd->int_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) spin_lock_init(&pd->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) out_free_dmadesc_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) pd->rx_ring, pd->rx_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) out_free_io_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) out_free_regions_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) out_free_netdev_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) out_disable_pci_device_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) out_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static void smsc9420_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct smsc9420_pdata *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pd = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* tx_buffers and rx_buffers are freed in stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) BUG_ON(pd->tx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) BUG_ON(pd->rx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) BUG_ON(!pd->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) BUG_ON(!pd->rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) pd->rx_ring, pd->rx_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static SIMPLE_DEV_PM_OPS(smsc9420_pm_ops, smsc9420_suspend, smsc9420_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct pci_driver smsc9420_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .id_table = smsc9420_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .probe = smsc9420_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .remove = smsc9420_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .driver.pm = &smsc9420_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static int __init smsc9420_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return pci_register_driver(&smsc9420_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static void __exit smsc9420_exit_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pci_unregister_driver(&smsc9420_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) module_init(smsc9420_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) module_exit(smsc9420_exit_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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