Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2004-2008 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005-2008 ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __SMSC911X_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __SMSC911X_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*Chip ID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define LAN9115	0x01150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define LAN9116	0x01160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define LAN9117	0x01170000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define LAN9118	0x01180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define LAN9215	0x115A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define LAN9216	0x116A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define LAN9217	0x117A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LAN9218	0x118A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LAN9210	0x92100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LAN9211	0x92110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LAN9220	0x92200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LAN9221	0x92210000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LAN9250	0x92500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LAN89218	0x218A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TX_FIFO_LOW_THRESHOLD	((u32)1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SMSC911X_EEPROM_SIZE	((u32)128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define USE_DEBUG		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* This is the maximum number of packets to be received every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * NAPI poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SMSC_NAPI_WEIGHT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* implements a PHY loopback test at initialisation time, to ensure a packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * can be successfully looped back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define USE_PHY_WORK_AROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #if USE_DEBUG >= 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SMSC_WARN(pdata, nlevel, fmt, args...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	netif_warn(pdata, nlevel, (pdata)->dev,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		   "%s: " fmt "\n", __func__, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SMSC_WARN(pdata, nlevel, fmt, args...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	no_printk(fmt "\n", ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #if USE_DEBUG >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SMSC_TRACE(pdata, nlevel, fmt, args...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SMSC_TRACE(pdata, nlevel, fmt, args...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	no_printk(fmt "\n", ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #ifdef CONFIG_DEBUG_SPINLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SMSC_ASSERT_MAC_LOCK(pdata) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		lockdep_assert_held(&pdata->mac_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #endif				/* CONFIG_DEBUG_SPINLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* SMSC911x registers and bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RX_DATA_FIFO			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TX_DATA_FIFO			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TX_CMD_A_ON_COMP_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TX_CMD_A_BUF_END_ALGN_		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TX_CMD_A_4_BYTE_ALGN_		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TX_CMD_A_16_BYTE_ALGN_		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TX_CMD_A_32_BYTE_ALGN_		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TX_CMD_A_DATA_OFFSET_		0x001F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TX_CMD_A_FIRST_SEG_		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TX_CMD_A_LAST_SEG_		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TX_CMD_A_BUF_SIZE_		0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TX_CMD_B_PKT_TAG_		0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TX_CMD_B_ADD_CRC_DISABLE_	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TX_CMD_B_DISABLE_PADDING_	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TX_CMD_B_PKT_BYTE_LENGTH_	0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RX_STATUS_FIFO			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define RX_STS_ES_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RX_STS_LENGTH_ERR_		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define RX_STS_MCAST_			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define RX_STS_FRAME_TYPE_		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RX_STS_CRC_ERR_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define RX_STATUS_FIFO_PEEK		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TX_STATUS_FIFO			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TX_STS_ES_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TX_STS_LOST_CARRIER_		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TX_STS_NO_CARRIER_		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TX_STS_LATE_COL_		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TX_STS_EXCESS_COL_		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TX_STATUS_FIFO_PEEK		0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ID_REV				0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ID_REV_CHIP_ID_			0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ID_REV_REV_ID_			0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INT_CFG				0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define INT_CFG_INT_DEAS_		0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INT_CFG_INT_DEAS_CLR_		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INT_CFG_INT_DEAS_STS_		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define INT_CFG_IRQ_INT_		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define INT_CFG_IRQ_EN_			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INT_CFG_IRQ_POL_		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_CFG_IRQ_TYPE_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INT_STS				0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define INT_STS_SW_INT_			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define INT_STS_TXSTOP_INT_		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define INT_STS_RXSTOP_INT_		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INT_STS_RXDFH_INT_		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INT_STS_RXDF_INT_		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INT_STS_TX_IOC_			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INT_STS_RXD_INT_		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INT_STS_GPT_INT_		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INT_STS_PHY_INT_		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INT_STS_PME_INT_		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INT_STS_TXSO_			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INT_STS_RWT_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INT_STS_RXE_			0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INT_STS_TXE_			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INT_STS_TDFU_			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INT_STS_TDFO_			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define INT_STS_TDFA_			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_STS_TSFF_			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INT_STS_TSFL_			0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INT_STS_RXDF_			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define INT_STS_RDFL_			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INT_STS_RSFF_			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INT_STS_RSFL_			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define INT_STS_GPIO2_INT_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define INT_STS_GPIO1_INT_		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define INT_STS_GPIO0_INT_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define INT_EN				0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INT_EN_SW_INT_EN_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define INT_EN_TXSTOP_INT_EN_		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define INT_EN_RXSTOP_INT_EN_		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define INT_EN_RXDFH_INT_EN_		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define INT_EN_TIOC_INT_EN_		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define INT_EN_RXD_INT_EN_		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define INT_EN_GPT_INT_EN_		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define INT_EN_PHY_INT_EN_		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define INT_EN_PME_INT_EN_		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define INT_EN_TXSO_EN_			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define INT_EN_RWT_EN_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define INT_EN_RXE_EN_			0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define INT_EN_TXE_EN_			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define INT_EN_TDFU_EN_			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define INT_EN_TDFO_EN_			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define INT_EN_TDFA_EN_			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define INT_EN_TSFF_EN_			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define INT_EN_TSFL_EN_			0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define INT_EN_RXDF_EN_			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define INT_EN_RDFL_EN_			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define INT_EN_RSFF_EN_			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define INT_EN_RSFL_EN_			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define INT_EN_GPIO2_INT_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define INT_EN_GPIO1_INT_		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define INT_EN_GPIO0_INT_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BYTE_TEST			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FIFO_INT			0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FIFO_INT_TX_AVAIL_LEVEL_	0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FIFO_INT_TX_STS_LEVEL_		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FIFO_INT_RX_AVAIL_LEVEL_	0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FIFO_INT_RX_STS_LEVEL_		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RX_CFG				0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RX_CFG_RX_END_ALGN_		0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RX_CFG_RX_END_ALGN4_		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RX_CFG_RX_END_ALGN16_		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RX_CFG_RX_END_ALGN32_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RX_CFG_RX_DMA_CNT_		0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RX_CFG_RX_DUMP_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RX_CFG_RXDOFF_			0x00001F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TX_CFG				0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TX_CFG_TXS_DUMP_		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TX_CFG_TXD_DUMP_		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TX_CFG_TXSAO_			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TX_CFG_TX_ON_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TX_CFG_STOP_TX_			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HW_CFG				0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HW_CFG_TTM_			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HW_CFG_SF_			0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HW_CFG_TX_FIF_SZ_		0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HW_CFG_TR_			0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HW_CFG_SRST_			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* only available on 115/117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HW_CFG_PHY_CLK_SEL_		0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HW_CFG_PHY_CLK_SEL_INT_PHY_	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HW_CFG_PHY_CLK_SEL_EXT_PHY_	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HW_CFG_PHY_CLK_SEL_CLK_DIS_	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HW_CFG_SMI_SEL_		 	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HW_CFG_EXT_PHY_DET_		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HW_CFG_EXT_PHY_EN_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HW_CFG_SRST_TO_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* only available  on 116/118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HW_CFG_32_16_BIT_MODE_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RX_DP_CTRL			0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RX_DP_CTRL_RX_FFWD_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RX_FIFO_INF			0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RX_FIFO_INF_RXSUSED_		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RX_FIFO_INF_RXDUSED_		0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TX_FIFO_INF			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TX_FIFO_INF_TSUSED_		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TX_FIFO_INF_TDFREE_		0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PMT_CTRL			0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PMT_CTRL_PM_MODE_		0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PMT_CTRL_PM_MODE_D0_		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PMT_CTRL_PM_MODE_D1_		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PMT_CTRL_PM_MODE_D2_		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PMT_CTRL_PM_MODE_D3_		0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PMT_CTRL_PHY_RST_		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PMT_CTRL_WOL_EN_		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PMT_CTRL_ED_EN_			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PMT_CTRL_PME_TYPE_		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PMT_CTRL_WUPS_			0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PMT_CTRL_WUPS_NOWAKE_		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PMT_CTRL_WUPS_ED_		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PMT_CTRL_WUPS_WOL_		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PMT_CTRL_WUPS_MULTI_		0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PMT_CTRL_PME_IND_		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PMT_CTRL_PME_POL_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PMT_CTRL_PME_EN_		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PMT_CTRL_READY_			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GPIO_CFG			0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GPIO_CFG_LED3_EN_		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GPIO_CFG_LED2_EN_		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GPIO_CFG_LED1_EN_		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GPIO_CFG_GPIO2_INT_POL_		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GPIO_CFG_GPIO1_INT_POL_		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GPIO_CFG_GPIO0_INT_POL_		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GPIO_CFG_EEPR_EN_		0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GPIO_CFG_GPIOBUF2_		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GPIO_CFG_GPIOBUF1_		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GPIO_CFG_GPIOBUF0_		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GPIO_CFG_GPIODIR2_		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GPIO_CFG_GPIODIR1_		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GPIO_CFG_GPIODIR0_		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GPIO_CFG_GPIOD4_		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GPIO_CFG_GPIOD3_		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GPIO_CFG_GPIOD2_		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GPIO_CFG_GPIOD1_		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GPIO_CFG_GPIOD0_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GPT_CFG				0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GPT_CFG_TIMER_EN_		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GPT_CFG_GPT_LOAD_		0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GPT_CNT				0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GPT_CNT_GPT_CNT_		0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define WORD_SWAP			0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define FREE_RUN			0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RX_DROP				0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MAC_CSR_CMD			0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MAC_CSR_CMD_CSR_BUSY_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MAC_CSR_CMD_R_NOT_W_		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MAC_CSR_CMD_CSR_ADDR_		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MAC_CSR_DATA			0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AFC_CFG				0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AFC_CFG_AFC_HI_			0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AFC_CFG_AFC_LO_			0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AFC_CFG_BACK_DUR_		0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AFC_CFG_FCMULT_			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AFC_CFG_FCBRD_			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AFC_CFG_FCADD_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AFC_CFG_FCANY_			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define E2P_CMD				0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define E2P_CMD_EPC_BUSY_		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define E2P_CMD_EPC_CMD_		0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define E2P_CMD_EPC_CMD_READ_		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define E2P_CMD_EPC_CMD_EWDS_		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define E2P_CMD_EPC_CMD_EWEN_		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define E2P_CMD_EPC_CMD_WRITE_		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define E2P_CMD_EPC_CMD_WRAL_		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define E2P_CMD_EPC_CMD_ERASE_		0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define E2P_CMD_EPC_CMD_ERAL_		0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define E2P_CMD_EPC_CMD_RELOAD_		0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define E2P_CMD_EPC_TIMEOUT_		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define E2P_CMD_MAC_ADDR_LOADED_	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define E2P_CMD_EPC_ADDR_		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define E2P_DATA			0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define E2P_DATA_EEPROM_DATA_		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define LAN_REGISTER_EXTENT		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RESET_CTL			0x1F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RESET_CTL_DIGITAL_RST_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * MAC Control and Status Register (Indirect Address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  * Offset (through the MAC_CSR CMD and DATA port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MAC_CR				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MAC_CR_RXALL_			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MAC_CR_HBDIS_			0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MAC_CR_RCVOWN_			0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MAC_CR_LOOPBK_			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MAC_CR_FDPX_			0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MAC_CR_MCPAS_			0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MAC_CR_PRMS_			0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MAC_CR_INVFILT_			0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MAC_CR_PASSBAD_			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MAC_CR_HFILT_			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MAC_CR_HPFILT_			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MAC_CR_LCOLL_			0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MAC_CR_BCAST_			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MAC_CR_DISRTY_			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MAC_CR_PADSTR_			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MAC_CR_BOLMT_MASK_		0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MAC_CR_DFCHK_			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MAC_CR_TXEN_			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MAC_CR_RXEN_			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ADDRH				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ADDRL				0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HASHH				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HASHL				0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MII_ACC				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MII_ACC_PHY_ADDR_		0x0000F800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MII_ACC_MIIRINDA_		0x000007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MII_ACC_MII_WRITE_		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MII_ACC_MII_BUSY_		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MII_DATA			0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define FLOW				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FLOW_FCPT_			0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FLOW_FCPASS_			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define FLOW_FCEN_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define FLOW_FCBSY_			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define VLAN1				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define VLAN2				0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define WUFF				0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define WUCSR				0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define WUCSR_GUE_			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define WUCSR_WUFR_			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define WUCSR_MPR_			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define WUCSR_WAKE_EN_			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define WUCSR_MPEN_			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * Phy definitions (vendor-specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define LAN9118_PHY_ID			0x00C0001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MII_INTSTS			0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MII_INTMSK			0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PHY_INTMSK_AN_RCV_		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PHY_INTMSK_PDFAULT_		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PHY_INTMSK_AN_ACK_		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PHY_INTMSK_LNKDOWN_		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PHY_INTMSK_RFAULT_		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PHY_INTMSK_AN_COMP_		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PHY_INTMSK_ENERGYON_		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PHY_INTMSK_DEFAULT_		(PHY_INTMSK_ENERGYON_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 					 PHY_INTMSK_AN_COMP_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 					 PHY_INTMSK_RFAULT_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 					 PHY_INTMSK_LNKDOWN_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ADVERTISE_PAUSE_ALL		(ADVERTISE_PAUSE_CAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 					 ADVERTISE_PAUSE_ASYM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define LPA_PAUSE_ALL			(LPA_PAUSE_CAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 					 LPA_PAUSE_ASYM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * Provide hooks to let the arch add to the initialisation procedure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  * and to override the source of the MAC address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SMSC_INITIALIZE()		do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define smsc_get_mac(dev)		smsc911x_read_mac_address((dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #ifdef CONFIG_SMSC911X_ARCH_HOOKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #include <asm/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #include <linux/smscphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif				/* __SMSC911X_H__ */