^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004-2008 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2008 ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rewritten, heavily based on smsc911x simple driver by SMSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Partly uses io macros from smc91x.c by Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Supported devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * LAN9115, LAN9116, LAN9117, LAN9118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * LAN9215, LAN9216, LAN9217, LAN9218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * LAN9210, LAN9211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * LAN9220, LAN9221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * LAN89218,LAN9250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/swab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "smsc911x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SMSC_CHIPNAME "smsc911x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SMSC_MDIONAME "smsc911x-mdio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SMSC_DRV_VERSION "2008-10-21"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_VERSION(SMSC_DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_ALIAS("platform:smsc911x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if USE_DEBUG > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int debug = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int debug = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct smsc911x_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct smsc911x_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*rx_readfifo)(struct smsc911x_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int *buf, unsigned int wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void (*tx_writefifo)(struct smsc911x_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int *buf, unsigned int wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SMSC911X_NUM_SUPPLIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct smsc911x_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int idrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* used to decide which workarounds apply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* device configuration (copied from platform_data during probe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct smsc911x_platform_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* This needs to be acquired before calling any of below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * smsc911x_mac_read(), smsc911x_mac_write()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spinlock_t mac_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* spinlock to ensure register accesses are serialised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spinlock_t dev_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int using_extphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int last_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int last_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int gpio_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int gpio_orig_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int software_irq_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifdef USE_PHY_WORK_AROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MIN_PACKET_SIZE (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) char loopback_tx_pkt[MIN_PACKET_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) char loopback_rx_pkt[MIN_PACKET_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int resetcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Members for Multicast filter workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int multicast_update_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int set_bits_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int clear_bits_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int hashhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int hashlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct smsc911x_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Reset GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct gpio_desc *reset_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Easy access to information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (pdata->config.flags & SMSC911X_USE_32BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return readl(pdata->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (pdata->config.flags & SMSC911X_USE_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (pdata->config.flags & SMSC911X_USE_32BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (pdata->config.flags & SMSC911X_USE_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return (readw(pdata->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __smsc_shift(pdata, reg)) & 0xFFFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ((readw(pdata->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) data = pdata->ops->reg_read(pdata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(val, pdata->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writew(val & 0xFFFF, pdata->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writew(val & 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pdata->ioaddr + __smsc_shift(pdata, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writew((val >> 16) & 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pdata->ioaddr + __smsc_shift(pdata, reg + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pdata->ops->reg_write(pdata, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Writes a packet to the TX_DATA_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int wordcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __smsc911x_reg_write(pdata, TX_DATA_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) swab32(*buf++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Writes a packet to the TX_DATA_FIFO - shifted version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int wordcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) swab32(*buf++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) TX_DATA_FIFO), buf, wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __smsc911x_reg_write_shift(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) TX_DATA_FIFO, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Reads a packet out of the RX_DATA_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int wordcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *buf++ = swab32(__smsc911x_reg_read(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RX_DATA_FIFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Reads a packet out of the RX_DATA_FIFO - shifted version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int wordcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) spin_lock_irqsave(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RX_DATA_FIFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (pdata->config.flags & SMSC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RX_DATA_FIFO), buf, wordcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (pdata->config.flags & SMSC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) while (wordcount--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *buf++ = __smsc911x_reg_read_shift(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RX_DATA_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_unlock_irqrestore(&pdata->dev_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * enable regulator and clock resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int smsc911x_enable_resources(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) netdev_err(ndev, "failed to enable regulators %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) netdev_err(ndev, "failed to enable clock %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * disable resources, currently just regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int smsc911x_disable_resources(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!IS_ERR(pdata->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Request resources, currently just regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * these are not always-on we need to request regulators to be turned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * before we can try to access the device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int smsc911x_request_resources(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Request regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pdata->supplies[0].supply = "vdd33a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pdata->supplies[1].supply = "vddvario";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = regulator_bulk_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ARRAY_SIZE(pdata->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Retry on deferrals, else just report the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * and try to continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) netdev_err(ndev, "couldn't get regulators %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Request optional RESET GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pdata->reset_gpiod = devm_gpiod_get_optional(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Request clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pdata->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (IS_ERR(pdata->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_dbg(&pdev->dev, "couldn't get clock %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PTR_ERR(pdata->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Free resources, currently just regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void smsc911x_free_resources(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Free regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Free clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clk_put(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pdata->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * and smsc911x_mac_write, so assumes mac_lock is held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int smsc911x_mac_complete(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SMSC_ASSERT_MAC_LOCK(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (i = 0; i < 40; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!(val & MAC_CSR_CMD_CSR_BUSY_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "MAC_CSR_CMD: 0x%08X", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Fetches a MAC register value. Assumes mac_lock is acquired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SMSC_ASSERT_MAC_LOCK(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SMSC_WARN(pdata, hw, "MAC busy at entry");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Send the MAC cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Workaround for hardware read-after-write restriction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) temp = smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Wait for the read to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (likely(smsc911x_mac_complete(pdata) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return smsc911x_reg_read(pdata, MAC_CSR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SMSC_WARN(pdata, hw, "MAC busy after read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Set a mac register, mac_lock must be acquired before calling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void smsc911x_mac_write(struct smsc911x_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SMSC_ASSERT_MAC_LOCK(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SMSC_WARN(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "smsc911x_mac_write failed, MAC busy at entry");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Send data to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Write the actual data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MAC_CSR_CMD_CSR_BUSY_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Workaround for hardware read-after-write restriction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) temp = smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Wait for the write to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (likely(smsc911x_mac_complete(pdata) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Get a phy register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Set the address, index & direction (read from PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) smsc911x_mac_write(pdata, MII_ACC, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Wait for read to complete w/ timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) for (i = 0; i < 100; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) reg = smsc911x_mac_read(pdata, MII_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Set a phy register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Put the data to write in the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) smsc911x_mac_write(pdata, MII_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Set the address, index & direction (write to PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MII_ACC_MII_WRITE_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) smsc911x_mac_write(pdata, MII_ACC, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Wait for write to complete w/ timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (i = 0; i < 100; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reg = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Switch to external phy. Assumes tx and rx are stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Disable phy clocks to the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) smsc911x_reg_write(pdata, HW_CFG, hwcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) udelay(10); /* Enough time for clocks to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Switch to external phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) hwcfg |= HW_CFG_EXT_PHY_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) smsc911x_reg_write(pdata, HW_CFG, hwcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Enable phy clocks to the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) smsc911x_reg_write(pdata, HW_CFG, hwcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) udelay(10); /* Enough time for clocks to restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) hwcfg |= HW_CFG_SMI_SEL_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) smsc911x_reg_write(pdata, HW_CFG, hwcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Autodetects and enables external phy if present on supported chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SMSC_TRACE(pdata, hw, "Forcing internal PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pdata->using_extphy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SMSC_TRACE(pdata, hw, "Forcing external PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) smsc911x_phy_enable_external(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pdata->using_extphy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) SMSC_TRACE(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "HW_CFG EXT_PHY_DET set, using external PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) smsc911x_phy_enable_external(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pdata->using_extphy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SMSC_TRACE(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "HW_CFG EXT_PHY_DET clear, using internal PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pdata->using_extphy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Fetches a tx status out of the status fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Fetches the next rx status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned int result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #ifdef USE_PHY_WORK_AROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 wrsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 rdsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ulong bufp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) for (tries = 0; tries < 10; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int txcmd_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned int txcmd_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int pktlength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Zero-out rx packet memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Write tx packet to 118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) txcmd_a |= MIN_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) wrsz = MIN_PACKET_SIZE + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) wrsz >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Wait till transmit is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) i = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) status = smsc911x_tx_get_txstatus(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } while ((i--) && (!status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SMSC_WARN(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "Failed to transmit during loopback test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (status & TX_STS_ES_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SMSC_WARN(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "Transmit encountered errors during loopback test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Wait till receive is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) i = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) status = smsc911x_rx_get_rxstatus(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } while ((i--) && (!status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SMSC_WARN(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "Failed to receive during loopback test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (status & RX_STS_ES_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) SMSC_WARN(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "Receive encountered errors during loopback test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pktlength = ((status & 0x3FFF0000UL) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) bufp = (ulong)pdata->loopback_rx_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rdsz = pktlength + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rdsz >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (pktlength != (MIN_PACKET_SIZE + 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SMSC_WARN(pdata, hw, "Unexpected packet size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "during loop back test, size=%d, will retry",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pktlength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int mismatch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (j = 0; j < MIN_PACKET_SIZE; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (pdata->loopback_tx_pkt[j]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) != pdata->loopback_rx_pkt[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mismatch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!mismatch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) SMSC_TRACE(pdata, hw, "Successfully verified "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "loopback packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) SMSC_WARN(pdata, hw, "Data mismatch "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "during loop back test, will retry");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int smsc911x_phy_reset(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int i = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) temp = smsc911x_reg_read(pdata, PMT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) temp = smsc911x_reg_read(pdata, PMT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } while ((i--) && (temp & PMT_CTRL_PHY_RST_));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (unlikely(temp & PMT_CTRL_PHY_RST_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SMSC_WARN(pdata, hw, "PHY reset failed to complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Extra delay required because the phy may not be completed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * its reset when BMCR_RESET is cleared. Specs say 256 uS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * enough delay but using 1ms here to be safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int smsc911x_phy_loopbacktest(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned int i, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Initialise tx packet using broadcast destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) eth_broadcast_addr(pdata->loopback_tx_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Use incrementing source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 6; i < 12; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pdata->loopback_tx_pkt[i] = (char)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Set length type field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pdata->loopback_tx_pkt[12] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pdata->loopback_tx_pkt[13] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) for (i = 14; i < MIN_PACKET_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pdata->loopback_tx_pkt[i] = (char)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) val = smsc911x_reg_read(pdata, HW_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val &= HW_CFG_TX_FIF_SZ_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) val |= HW_CFG_SF_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) smsc911x_reg_write(pdata, HW_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) smsc911x_reg_write(pdata, RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Set PHY to 10/FD, no ANEG, and loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Enable MAC tx/rx, FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) | MAC_CR_TXEN_ | MAC_CR_RXEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pdata->resetcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Disable MAC rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) smsc911x_mac_write(pdata, MAC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) smsc911x_phy_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Disable MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) smsc911x_mac_write(pdata, MAC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Cancel PHY loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, MII_BMCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) smsc911x_reg_write(pdata, TX_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) smsc911x_reg_write(pdata, RX_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif /* USE_PHY_WORK_AROUND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct net_device *ndev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct phy_device *phy_dev = ndev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (phy_dev->duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u16 rmtadv = phy_read(phy_dev, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (cap & FLOW_CTRL_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) flow = 0xFFFF0002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (cap & FLOW_CTRL_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) afc |= 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) afc &= ~0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SMSC_TRACE(pdata, hw, "half duplex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) afc |= 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) smsc911x_mac_write(pdata, FLOW, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) smsc911x_reg_write(pdata, AFC_CFG, afc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Update link mode if anything has changed. Called periodically when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * PHY is in polling mode, even if nothing has changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void smsc911x_phy_adjust_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (phy_dev->duplex != pdata->last_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unsigned int mac_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SMSC_TRACE(pdata, hw, "duplex state has changed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mac_cr = smsc911x_mac_read(pdata, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (phy_dev->duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) SMSC_TRACE(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "configuring for full duplex mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mac_cr |= MAC_CR_FDPX_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) SMSC_TRACE(pdata, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "configuring for half duplex mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mac_cr &= ~MAC_CR_FDPX_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) smsc911x_mac_write(pdata, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) smsc911x_phy_update_flowcontrol(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pdata->last_duplex = phy_dev->duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) carrier = netif_carrier_ok(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (carrier != pdata->last_carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) SMSC_TRACE(pdata, hw, "carrier state has changed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) SMSC_TRACE(pdata, hw, "configuring for carrier OK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) (!pdata->using_extphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Restore original GPIO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pdata->gpio_setting = pdata->gpio_orig_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) smsc911x_reg_write(pdata, GPIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pdata->gpio_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SMSC_TRACE(pdata, hw, "configuring for no carrier");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Check global setting that LED1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * usage is 10/100 indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pdata->gpio_setting = smsc911x_reg_read(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GPIO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) (!pdata->using_extphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Force 10/100 LED off, after saving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * original GPIO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pdata->gpio_orig_setting = pdata->gpio_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) | GPIO_CFG_GPIODIR0_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) | GPIO_CFG_GPIOD0_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) smsc911x_reg_write(pdata, GPIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pdata->gpio_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pdata->last_carrier = carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int smsc911x_mii_probe(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct phy_device *phydev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* find the first phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) phydev = phy_find_first(pdata->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) netdev_err(dev, "no PHY found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) phydev->mdio.addr, phydev->phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pdata->config.phy_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) netdev_err(dev, "Could not attach to PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) phy_attached_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) phy_set_max_speed(phydev, SPEED_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* mask with MAC supported features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) phy_support_asym_pause(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pdata->last_duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) pdata->last_carrier = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #ifdef USE_PHY_WORK_AROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (smsc911x_phy_loopbacktest(dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SMSC_WARN(pdata, hw, "Failed Loop Back Test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) phy_disconnect(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #endif /* USE_PHY_WORK_AROUND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) SMSC_TRACE(pdata, hw, "phy initialised successfully");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int smsc911x_mii_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pdata->mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (!pdata->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto err_out_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pdata->mii_bus->name = SMSC_MDIONAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pdata->mii_bus->priv = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pdata->mii_bus->read = smsc911x_mii_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pdata->mii_bus->write = smsc911x_mii_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pdata->mii_bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) switch (pdata->idrev & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case 0x01170000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case 0x01150000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case 0x117A0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case 0x115A0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* External PHY supported, try to autodetect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) smsc911x_phy_initialise_external(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) SMSC_TRACE(pdata, hw, "External PHY is not supported, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "using internal PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pdata->using_extphy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!pdata->using_extphy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Mask all PHYs except ID 1 (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pdata->mii_bus->phy_mask = ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (mdiobus_register(pdata->mii_bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) SMSC_WARN(pdata, probe, "Error registering mii bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto err_out_free_bus_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) err_out_free_bus_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) mdiobus_free(pdata->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) err_out_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Gets the number of tx statuses in the fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return (smsc911x_reg_read(pdata, TX_FIFO_INF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) & TX_FIFO_INF_TSUSED_) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Reads tx statuses and increments counters where necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static void smsc911x_tx_update_txcounters(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) unsigned int tx_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (unlikely(tx_stat & 0x80000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* In this driver the packet tag is used as the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * length. Since a packet length can never reach the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * size of 0x8000, this bit is reserved. It is worth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * noting that the "reserved bit" in the warning above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * does not reference a hardware defined reserved bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * but rather a driver defined one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (unlikely(tx_stat & TX_STS_ES_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dev->stats.tx_bytes += (tx_stat >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev->stats.collisions += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev->stats.tx_aborted_errors += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev->stats.collisions +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ((tx_stat >> 3) & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev->stats.tx_carrier_errors += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Increments the Rx error counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int crc_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (unlikely(rxstat & RX_STS_ES_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) crc_err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (likely(!crc_err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) (rxstat & RX_STS_LENGTH_ERR_)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (rxstat & RX_STS_MCAST_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev->stats.multicast++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Quickly dumps bad packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (likely(pktwords >= 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned int timeout = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) val = smsc911x_reg_read(pdata, RX_DP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (unlikely(timeout == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SMSC_WARN(pdata, hw, "Timed out waiting for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) while (pktwords--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) smsc911x_reg_read(pdata, RX_DATA_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* NAPI poll function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int smsc911x_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct smsc911x_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) container_of(napi, struct smsc911x_data, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct net_device *dev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int npackets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) while (npackets < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) unsigned int pktlength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) unsigned int pktwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!rxstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* We processed all packets available. Tell NAPI it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * stop polling then re-enable rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) napi_complete(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) temp = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) temp |= INT_EN_RSFL_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) smsc911x_reg_write(pdata, INT_EN, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Count packet for NAPI scheduling, even if it has an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Error packets still require cycles to discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) npackets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pktlength = ((rxstat & 0x3FFF0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) smsc911x_rx_counterrors(dev, rxstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (unlikely(rxstat & RX_STS_ES_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SMSC_WARN(pdata, rx_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) "Discarding packet with error bit set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Packet has an error, discard it and continue with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * the next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) smsc911x_rx_fastforward(pdata, pktwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) skb = netdev_alloc_skb(dev, pktwords << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) SMSC_WARN(pdata, rx_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "Unable to allocate skb for rx packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Drop the packet and stop this polling iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) smsc911x_rx_fastforward(pdata, pktwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) pdata->ops->rx_readfifo(pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) (unsigned int *)skb->data, pktwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Align IP on 16B boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) skb_reserve(skb, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) skb_put(skb, pktlength - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* Update counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dev->stats.rx_bytes += (pktlength - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Return total received packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return npackets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* Returns hash bit number for given MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * 01 00 5E 00 00 01 -> returns bit number 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static unsigned int smsc911x_hash(char addr[ETH_ALEN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Performs the multicast & mac_cr update. This is called when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * safe on the current hardware, and with the mac_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) unsigned int mac_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) SMSC_ASSERT_MAC_LOCK(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mac_cr = smsc911x_mac_read(pdata, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mac_cr |= pdata->set_bits_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) mac_cr &= ~(pdata->clear_bits_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) smsc911x_mac_write(pdata, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mac_cr, pdata->hashhi, pdata->hashlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int mac_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* This function is only called for older LAN911x devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * (revA or revB), where MAC_CR, HASHH and HASHL should not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * be modified during Rx - newer devices immediately update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * This is called from interrupt context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) spin_lock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* Check Rx has stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) SMSC_WARN(pdata, drv, "Rx not stopped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Perform the update - safe to do now Rx has stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) smsc911x_rx_multicast_update(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Re-enable Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) mac_cr = smsc911x_mac_read(pdata, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mac_cr |= MAC_CR_RXEN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) smsc911x_mac_write(pdata, MAC_CR, mac_cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pdata->multicast_update_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_unlock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct net_device *ndev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct phy_device *phy_dev = ndev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!phy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* If the internal PHY is in General Power-Down mode, all, except the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * management interface, is powered-down and stays in that condition as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * long as Phy register bit 0.11 is HIGH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * In that case, clear the bit 0.11, so the PHY powers up and we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * access to the phy registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) rc = phy_read(phy_dev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* If the PHY general power-down bit is not set is not necessary to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * disable the general power down-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (rc & BMCR_PDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) rc = phy_write(phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct net_device *ndev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct phy_device *phy_dev = ndev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!phy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Only disable if energy detect mode is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (rc & MII_LAN83C185_EDPWRDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Disable energy detect mode for this SMSC Transceivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) rc & (~MII_LAN83C185_EDPWRDOWN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Allow PHY to wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct net_device *ndev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct phy_device *phy_dev = ndev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (!phy_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* Only enable if energy detect mode is already disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* Enable energy detect mode for this SMSC Transceivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) rc | MII_LAN83C185_EDPWRDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int smsc911x_soft_reset(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) unsigned int reset_offset = HW_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) unsigned int reset_mask = HW_CFG_SRST_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * Make sure to power-up the PHY chip before doing a reset, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * the reset fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = smsc911x_phy_general_power_up(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * are initialized in a Energy Detect Power-Down mode that prevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * the MAC chip to be software reseted. So we have to wakeup the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (pdata->generation == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ret = smsc911x_phy_disable_energy_detect(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if ((pdata->idrev & 0xFFFF0000) == LAN9250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* special reset for LAN9250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) reset_offset = RESET_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) reset_mask = RESET_CTL_DIGITAL_RST_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Reset the LAN911x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) smsc911x_reg_write(pdata, reset_offset, reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* verify reset bit is cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) temp = smsc911x_reg_read(pdata, reset_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) } while ((--timeout) && (temp & reset_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (unlikely(temp & reset_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SMSC_WARN(pdata, drv, "Failed to complete reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (pdata->generation == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ret = smsc911x_phy_enable_energy_detect(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* Sets the device MAC address to dev_addr, called with mac_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) (dev_addr[1] << 8) | dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) SMSC_ASSERT_MAC_LOCK(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) smsc911x_mac_write(pdata, ADDRH, mac_high16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) smsc911x_mac_write(pdata, ADDRL, mac_low32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static void smsc911x_disable_irq_chip(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) smsc911x_reg_write(pdata, INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) u32 intsts = smsc911x_reg_read(pdata, INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) u32 inten = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int serviced = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) temp = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) temp &= (~INT_EN_SW_INT_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) smsc911x_reg_write(pdata, INT_EN, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pdata->software_irq_signal = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) serviced = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* Called when there is a multicast update scheduled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * it is now safe to complete the update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SMSC_TRACE(pdata, intr, "RX Stop interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (pdata->multicast_update_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) smsc911x_rx_multicast_update_workaround(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) serviced = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (intsts & inten & INT_STS_TDFA_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) temp = smsc911x_reg_read(pdata, FIFO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) temp |= FIFO_INT_TX_AVAIL_LEVEL_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) smsc911x_reg_write(pdata, FIFO_INT, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) serviced = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (unlikely(intsts & inten & INT_STS_RXE_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SMSC_TRACE(pdata, intr, "RX Error interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) serviced = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (likely(intsts & inten & INT_STS_RSFL_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (likely(napi_schedule_prep(&pdata->napi))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Disable Rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) temp = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) temp &= (~INT_EN_RSFL_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) smsc911x_reg_write(pdata, INT_EN, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* Schedule a NAPI poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) __napi_schedule(&pdata->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) serviced = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return serviced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static int smsc911x_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) unsigned int intcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* find and start the given phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (!dev->phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) retval = smsc911x_mii_probe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SMSC_WARN(pdata, probe, "Error starting phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* Reset the LAN911x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) retval = smsc911x_soft_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) SMSC_WARN(pdata, hw, "soft reset failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) goto mii_free_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* Make sure EEPROM has finished loading before setting GPIO_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) --timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (unlikely(timeout == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) SMSC_WARN(pdata, ifup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) "Timed out waiting for EEPROM busy bit to clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* The soft reset above cleared the device's MAC address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * restore it from local copy (set in probe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* Initialise irqs, but leave all sources disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) smsc911x_disable_irq_chip(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* Set interrupt deassertion to 100uS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (pdata->config.irq_polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SMSC_TRACE(pdata, ifup, "irq polarity: active high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) intcfg |= INT_CFG_IRQ_POL_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SMSC_TRACE(pdata, ifup, "irq polarity: active low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (pdata->config.irq_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) SMSC_TRACE(pdata, ifup, "irq type: push-pull");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) intcfg |= INT_CFG_IRQ_TYPE_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) SMSC_TRACE(pdata, ifup, "irq type: open drain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) smsc911x_reg_write(pdata, INT_CFG, intcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pdata->software_irq_signal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) irq_flags = irq_get_trigger_type(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) retval = request_irq(dev->irq, smsc911x_irqhandler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) irq_flags | IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) SMSC_WARN(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) "Unable to claim requested irq: %d", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) goto mii_free_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) temp = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) temp |= INT_EN_SW_INT_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) smsc911x_reg_write(pdata, INT_EN, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (pdata->software_irq_signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (!pdata->software_irq_signal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) goto irq_stop_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) (unsigned long)pdata->ioaddr, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Reset the last known duplex and carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) pdata->last_duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pdata->last_carrier = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* Bring the PHY up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) phy_start(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) temp = smsc911x_reg_read(pdata, HW_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* Preserve TX FIFO size and external PHY configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) temp |= HW_CFG_SF_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) smsc911x_reg_write(pdata, HW_CFG, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) temp = smsc911x_reg_read(pdata, FIFO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) temp |= FIFO_INT_TX_AVAIL_LEVEL_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) temp &= ~(FIFO_INT_RX_STS_LEVEL_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) smsc911x_reg_write(pdata, FIFO_INT, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* set RX Data offset to 2 bytes for alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* enable NAPI polling before enabling RX interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) napi_enable(&pdata->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) temp = smsc911x_reg_read(pdata, INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) smsc911x_reg_write(pdata, INT_EN, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) temp = smsc911x_mac_read(pdata, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) smsc911x_mac_write(pdata, MAC_CR, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) irq_stop_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) mii_free_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) phy_disconnect(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) dev->phydev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Entry point for stopping the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static int smsc911x_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* Disable all device interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) temp = smsc911x_reg_read(pdata, INT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) temp &= ~INT_CFG_IRQ_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) smsc911x_reg_write(pdata, INT_CFG, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* Stop Tx and Rx polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) napi_disable(&pdata->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* At this point all Rx and Tx activity is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) smsc911x_tx_update_txcounters(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* Bring the PHY down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (dev->phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) phy_stop(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) phy_disconnect(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) dev->phydev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) SMSC_TRACE(pdata, ifdown, "Interface stopped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* Entry point for transmitting a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) unsigned int freespace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) unsigned int tx_cmd_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) unsigned int tx_cmd_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u32 wrsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ulong bufp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SMSC_WARN(pdata, tx_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) "Tx data fifo low, space available: %d", freespace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* Word alignment adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) tx_cmd_a |= (unsigned int)skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) tx_cmd_b = ((unsigned int)skb->len) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) tx_cmd_b |= (unsigned int)skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) bufp = (ulong)skb->data & (~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) wrsz = (u32)skb->len + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) wrsz += (u32)((ulong)skb->data & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) wrsz >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) freespace -= (skb->len + 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) smsc911x_tx_update_txcounters(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (freespace < TX_FIFO_LOW_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) temp = smsc911x_reg_read(pdata, FIFO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) temp &= 0x00FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) temp |= 0x32000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) smsc911x_reg_write(pdata, FIFO_INT, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* Entry point for getting status counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) smsc911x_tx_update_txcounters(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* Entry point for setting addressing modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static void smsc911x_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* Enabling promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) pdata->set_bits_mask = MAC_CR_PRMS_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) pdata->hashhi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) pdata->hashlo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) } else if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* Enabling all multicast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) pdata->set_bits_mask = MAC_CR_MCPAS_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) pdata->hashhi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pdata->hashlo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) } else if (!netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Enabling specific multicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned int hash_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) unsigned int hash_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pdata->set_bits_mask = MAC_CR_HPFILT_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) unsigned int bitnum = smsc911x_hash(ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) unsigned int mask = 0x01 << (bitnum & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (bitnum & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) hash_high |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) hash_low |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) pdata->hashhi = hash_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) pdata->hashlo = hash_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Enabling local MAC address only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) pdata->set_bits_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) pdata->clear_bits_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) pdata->hashhi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pdata->hashlo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (pdata->generation <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* Older hardware revision - cannot change these flags while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * receiving data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (!pdata->multicast_update_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) SMSC_TRACE(pdata, hw, "scheduling mcast update");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) pdata->multicast_update_pending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* Request the hardware to stop, then perform the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * update when we get an RX_STOP interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) temp = smsc911x_mac_read(pdata, MAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) temp &= ~(MAC_CR_RXEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) smsc911x_mac_write(pdata, MAC_CR, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* There is another update pending, this should now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * use the newer values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* Newer hardware revision - can write immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) smsc911x_rx_multicast_update(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static void smsc911x_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) smsc911x_irqhandler(0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #endif /* CONFIG_NET_POLL_CONTROLLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static int smsc911x_set_mac_address(struct net_device *dev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* On older hardware revisions we cannot change the mac address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * registers while receiving data. Newer devices can safely change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * this at any time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (pdata->generation <= 1 && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (!is_valid_ether_addr(addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) strlcpy(info->bus_info, dev_name(dev->dev.parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return pdata->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) pdata->msg_enable = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static int smsc911x_ethtool_getregslen(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct phy_device *phy_dev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) unsigned int j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) u32 *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) regs->version = pdata->idrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) data[j++] = smsc911x_reg_read(pdata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) for (i = MAC_CR; i <= WUCSR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) spin_lock_irqsave(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) data[j++] = smsc911x_mac_read(pdata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) spin_unlock_irqrestore(&pdata->mac_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) for (i = 0; i <= 31; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) data[j++] = smsc911x_mii_read(phy_dev->mdio.bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) phy_dev->mdio.addr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) temp &= ~GPIO_CFG_EEPR_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) smsc911x_reg_write(pdata, GPIO_CFG, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) u32 e2cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) SMSC_TRACE(pdata, drv, "op 0x%08x", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) SMSC_WARN(pdata, drv, "Busy at start");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) e2cmd = op | E2P_CMD_EPC_BUSY_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) SMSC_TRACE(pdata, drv, "TIMED OUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) u8 address, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) u32 op = E2P_CMD_EPC_CMD_READ_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) SMSC_TRACE(pdata, drv, "address 0x%x", address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ret = smsc911x_eeprom_send_cmd(pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) data[address] = smsc911x_reg_read(pdata, E2P_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) u8 address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ret = smsc911x_eeprom_send_cmd(pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) op = E2P_CMD_EPC_CMD_WRITE_ | address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* Workaround for hardware read-after-write restriction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ret = smsc911x_eeprom_send_cmd(pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return SMSC911X_EEPROM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) u8 eeprom_data[SMSC911X_EEPROM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) smsc911x_eeprom_enable_access(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) eeprom->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) memcpy(data, &eeprom_data[eeprom->offset], len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) eeprom->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) smsc911x_eeprom_enable_access(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /* Single byte write, according to man page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) eeprom->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const struct ethtool_ops smsc911x_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .get_drvinfo = smsc911x_ethtool_getdrvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .nway_reset = phy_ethtool_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .get_msglevel = smsc911x_ethtool_getmsglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .set_msglevel = smsc911x_ethtool_setmsglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .get_regs_len = smsc911x_ethtool_getregslen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .get_regs = smsc911x_ethtool_getregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .get_eeprom = smsc911x_ethtool_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .set_eeprom = smsc911x_ethtool_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .get_ts_info = ethtool_op_get_ts_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .get_link_ksettings = phy_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .set_link_ksettings = phy_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static const struct net_device_ops smsc911x_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .ndo_open = smsc911x_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .ndo_stop = smsc911x_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .ndo_start_xmit = smsc911x_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .ndo_get_stats = smsc911x_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ndo_set_rx_mode = smsc911x_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .ndo_do_ioctl = phy_do_ioctl_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .ndo_set_mac_address = smsc911x_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .ndo_poll_controller = smsc911x_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* copies the current mac address from hardware to dev->dev_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static void smsc911x_read_mac_address(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) dev->dev_addr[0] = (u8)(mac_low32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) dev->dev_addr[1] = (u8)(mac_low32 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) dev->dev_addr[2] = (u8)(mac_low32 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) dev->dev_addr[3] = (u8)(mac_low32 >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) dev->dev_addr[4] = (u8)(mac_high16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dev->dev_addr[5] = (u8)(mac_high16 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /* Initializing private device structures, only called from probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static int smsc911x_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) struct smsc911x_data *pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) unsigned int byte_test, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) unsigned int to = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) SMSC_TRACE(pdata, probe, "Driver Parameters:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) (unsigned long)pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) spin_lock_init(&pdata->dev_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) spin_lock_init(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (pdata->ioaddr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) * poll the READY bit in PMT_CTRL. Any other access to the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) * forbidden while this bit isn't set. Try for 100ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * Note that this test is done before the WORD_SWAP register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * programmed. So in some configurations the READY bit is at 16 before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * WORD_SWAP is written to. This issue is worked around by waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * until either bit 0 or bit 16 gets set in PMT_CTRL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) * SMSC has confirmed that checking bit 16 (marked as reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) * the datasheet) is fine since these bits "will either never be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * or can only go high after READY does (so also indicate the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * is ready)".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (to == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) netdev_err(dev, "Device not READY in 100ms aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* Check byte ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (byte_test == 0x43218765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) "applying WORD_SWAP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /* 1 dummy read of BYTE_TEST is needed after a write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) * WORD_SWAP before its contents are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (byte_test != 0x87654321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) SMSC_WARN(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) "top 16 bits equal to bottom 16 bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) "This may mean the chip is set "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) "for 32 bit while the bus is reading 16 bit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Default generation to zero (all workarounds apply) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pdata->generation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) switch (pdata->idrev & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) case LAN9118:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) case LAN9117:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) case LAN9116:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) case LAN9115:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) case LAN89218:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /* LAN911[5678] family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) pdata->generation = pdata->idrev & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) case LAN9218:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) case LAN9217:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) case LAN9216:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) case LAN9215:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* LAN921[5678] family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) pdata->generation = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) case LAN9210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) case LAN9211:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) case LAN9220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) case LAN9221:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) case LAN9250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* LAN9210/LAN9211/LAN9220/LAN9221/LAN9250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) pdata->generation = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) pdata->idrev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) "LAN911x identified, idrev: 0x%08X, generation: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pdata->idrev, pdata->generation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (pdata->generation == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) SMSC_WARN(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) "This driver is not intended for this chip revision");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* workaround for platforms without an eeprom, where the mac address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) * is stored elsewhere and set by the bootloader. This saves the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) * mac address before resetting the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) smsc911x_read_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /* Reset the LAN911x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) dev->flags |= IFF_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) dev->netdev_ops = &smsc911x_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) dev->ethtool_ops = &smsc911x_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static int smsc911x_drv_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct smsc911x_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) BUG_ON(!pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) BUG_ON(!pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) SMSC_TRACE(pdata, ifdown, "Stopping driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) mdiobus_unregister(pdata->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) mdiobus_free(pdata->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) "smsc911x-memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) iounmap(pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) (void)smsc911x_disable_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) smsc911x_free_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* standard register acces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static const struct smsc911x_ops standard_smsc911x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .reg_read = __smsc911x_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .reg_write = __smsc911x_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .rx_readfifo = smsc911x_rx_readfifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .tx_writefifo = smsc911x_tx_writefifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) /* shifted register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static const struct smsc911x_ops shifted_smsc911x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .reg_read = __smsc911x_reg_read_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .reg_write = __smsc911x_reg_write_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .rx_readfifo = smsc911x_rx_readfifo_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .tx_writefifo = smsc911x_tx_writefifo_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static int smsc911x_probe_config(struct smsc911x_platform_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) int phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) u32 width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) phy_interface = device_get_phy_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (phy_interface < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) phy_interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) config->phy_interface = phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) device_get_mac_address(dev, config->mac, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) err = device_property_read_u32(dev, "reg-io-width", &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (err == -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) if (!err && width == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) config->flags |= SMSC911X_USE_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) config->flags |= SMSC911X_USE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) device_property_read_u32(dev, "reg-shift", &config->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (device_property_present(dev, "smsc,irq-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (device_property_present(dev, "smsc,irq-push-pull"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (device_property_present(dev, "smsc,force-internal-phy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (device_property_present(dev, "smsc,force-external-phy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (device_property_present(dev, "smsc,save-mac-address"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static int smsc911x_drv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) struct smsc911x_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) int res_size, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) "smsc911x-memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) pr_warn("Could not allocate resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) res_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (irq == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) retval = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) } else if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) pr_warn("Could not allocate irq resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) goto out_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) dev = alloc_etherdev(sizeof(struct smsc911x_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) goto out_release_io_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) pdata = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) pdata->ioaddr = ioremap(res->start, res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (!pdata->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) goto out_ioremap_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) pdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) pdata->msg_enable = ((1 << debug) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) retval = smsc911x_request_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) goto out_request_resources_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) retval = smsc911x_enable_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) goto out_enable_resources_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (pdata->ioaddr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) goto out_disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) retval = smsc911x_probe_config(&pdata->config, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (retval && config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* copy config parameters across to pdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) memcpy(&pdata->config, config, sizeof(pdata->config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) SMSC_WARN(pdata, probe, "Error smsc911x config not found");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) goto out_disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* assume standard, non-shifted, access to HW registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) pdata->ops = &standard_smsc911x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) /* apply the right access if shifting is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) if (pdata->config.shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) pdata->ops = &shifted_smsc911x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) retval = smsc911x_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) goto out_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) retval = smsc911x_mii_init(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) goto out_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) retval = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) SMSC_WARN(pdata, probe, "Error %i registering device", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) goto out_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) "Network interface: \"%s\"", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) spin_lock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* Check if mac address has been specified when bringing interface up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) "MAC Address is specified by configuration");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) } else if (is_valid_ether_addr(pdata->config.mac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) "MAC Address specified by platform data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /* Try reading mac address from device. if EEPROM is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) * it will already have been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) smsc_get_mac(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* eeprom values are valid so use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) "Mac Address is read from LAN911x EEPROM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* eeprom values are invalid, generate random MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) SMSC_TRACE(pdata, probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) "MAC Address is set to eth_random_addr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) spin_unlock_irq(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) out_init_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) out_disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) (void)smsc911x_disable_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) out_enable_resources_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) smsc911x_free_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) out_request_resources_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) iounmap(pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) out_ioremap_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) out_release_io_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) out_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) /* This implementation assumes the devices remains powered on its VDDVARIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) * pins during suspend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /* TODO: implement freeze/thaw callbacks for hibernation.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static int smsc911x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) netif_device_detach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* enable wake on LAN, energy detection and the external PME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) * signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) smsc911x_reg_write(pdata, PMT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) pm_runtime_set_suspended(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static int smsc911x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) struct smsc911x_data *pdata = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) unsigned int to = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) pm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* Note 3.11 from the datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) * "When the LAN9220 is in a power saving state, a write of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) * data to the BYTE_TEST register will wake-up the device."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) smsc911x_reg_write(pdata, BYTE_TEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* poll the READY bit in PMT_CTRL. Any other access to the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) * forbidden while this bit isn't set. Try for 100ms and return -EIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * if it failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if (to == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) netif_device_attach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) static const struct dev_pm_ops smsc911x_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .suspend = smsc911x_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .resume = smsc911x_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define SMSC911X_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static const struct of_device_id smsc911x_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) { .compatible = "smsc,lan9115", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const struct acpi_device_id smsc911x_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) { "ARMH9118", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static struct platform_driver smsc911x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .probe = smsc911x_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .remove = smsc911x_drv_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .name = SMSC_CHIPNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .pm = SMSC911X_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .of_match_table = of_match_ptr(smsc911x_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .acpi_match_table = ACPI_PTR(smsc911x_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) /* Entry point for loading the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static int __init smsc911x_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) SMSC_INITIALIZE();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return platform_driver_register(&smsc911x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /* entry point for unloading the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static void __exit smsc911x_cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) platform_driver_unregister(&smsc911x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) module_init(smsc911x_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) module_exit(smsc911x_cleanup_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags