^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * smc91x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 by Erik Stahlman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 Standard Microsystems Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Developed by Simple Network Magic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2003 Monta Vista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Unified SMC91x driver by Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * io = for the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * irq = for the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * nowait = 0 for normal wait states, 1 eliminates additional wait states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Erik Stahlman <erik@vt.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * hardware multicast code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Peter Cammaert <pc@denkart.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Daris A Nevil <dnevil@snmc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Nicolas Pitre <nico@fluxnic.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Russell King <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * more bus abstraction, big cleanup, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 29/09/03 Russell King - add driver model support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - ethtool support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - convert to use generic MII interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - add link up/down notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - don't try to handle full negotiation in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * smc_phy_configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * - clean up (and fix stack overrun) in PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * MII read/write functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 22/09/04 Nicolas Pitre big update (see commit log for details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Debugging level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifndef SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SMC_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include "smc91x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #if defined(CONFIG_ASSABET_NEPONSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <mach/assabet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <mach/neponset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifndef SMC_NOWAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define SMC_NOWAIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int nowait = SMC_NOWAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param(nowait, int, 0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Transmit timeout, default 5 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int watchdog = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) module_param(watchdog, int, 0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_ALIAS("platform:smc91x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * The internal workings of the driver. If you are changing anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * here with the SMC stuff, you should have the datasheet and know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * what you are doing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CARDNAME "smc91x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Use power-down feature of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define POWER_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Wait time for memory to be free. This probably shouldn't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * tuned that much, as waiting for this means nothing else happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * in the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MEMORY_WAIT_TIME 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * The maximum number of processing loops allowed for each call to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAX_IRQ_LOOPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This selects whether TX packets are sent one by one to the SMC91x internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * memory and throttled until transmission completes. This may prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * RX overruns a litle by keeping much of the memory free for RX packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * but to the expense of reduced TX throughput and increased IRQ overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Note this is not a cure for a too slow data bus or too high IRQ latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define THROTTLE_TX_PKTS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The MII clock high/low times. 2x this number gives the MII clock period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MII_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DBG(n, dev, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (SMC_DEBUG >= (n)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) netdev_dbg(dev, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PRINTK(dev, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (SMC_DEBUG > 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) netdev_info(dev, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) netdev_dbg(dev, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #if SMC_DEBUG > 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void PRINT_PKT(u_char *buf, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) lines = length / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) remainder = length % 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < lines ; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) printk(KERN_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (cur = 0; cur < 8; cur++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u_char a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) a = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) b = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_cont("%02x%02x ", a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) printk(KERN_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < remainder/2 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u_char a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) a = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) b = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pr_cont("%02x%02x ", a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void PRINT_PKT(u_char *buf, int length) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* this enables an interrupt in the interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SMC_ENABLE_INT(lp, x) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned char mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long smc_enable_flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spin_lock_irqsave(&lp->lock, smc_enable_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask = SMC_GET_INT_MASK(lp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mask |= (x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SMC_SET_INT_MASK(lp, mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* this disables an interrupt from the interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SMC_DISABLE_INT(lp, x) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long smc_disable_flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock_irqsave(&lp->lock, smc_disable_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mask = SMC_GET_INT_MASK(lp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mask &= ~(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SMC_SET_INT_MASK(lp, mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Wait while MMU is busy. This is usually in the order of a few nanosecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * if at all, but let's avoid deadlocking the system if the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * decides to go south.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SMC_WAIT_MMU_BUSY(lp) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long timeout = jiffies + 2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (time_after(jiffies, timeout)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) netdev_dbg(dev, "timeout %s line %d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __FILE__, __LINE__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cpu_relax(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * this does a soft reset on the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void smc_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int ctl, cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct sk_buff *pending_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Disable all interrupts, block TX tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SMC_SET_INT_MASK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pending_skb = lp->pending_tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) lp->pending_tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* free any pending tx skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pending_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_kfree_skb(pending_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * This resets the registers mostly to defaults, but doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * affect EEPROM. That seems unnecessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SMC_SET_RCR(lp, RCR_SOFTRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Setup the Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This is necessary because the CONFIG_REG is not affected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * by a soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cfg = CONFIG_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Setup for fast accesses if requested. If the card/system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * can't handle it then there will be no recovery except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * a hard reset or power cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (lp->cfg.flags & SMC91X_NOWAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cfg |= CONFIG_NO_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Release from possible power-down state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Configuration register is not affected by Soft Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cfg |= CONFIG_EPH_POWER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SMC_SET_CONFIG(lp, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* this should pause enough for the chip to be happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * elaborate? What does the chip _need_? --jgarzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * This seems to be undocumented, but something the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * driver(s) have always done. Suspect undocumented timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * info/determined empirically. --rmk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Disable transmit and receive functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SMC_SET_RCR(lp, RCR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SMC_SET_TCR(lp, TCR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Set the control register to automatically release successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * transmitted packets, to make the best use out of our limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if(!THROTTLE_TX_PKTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctl |= CTL_AUTO_RELEASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctl &= ~CTL_AUTO_RELEASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SMC_SET_CTL(lp, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Reset the MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SMC_SET_MMU_CMD(lp, MC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Enable Interrupts, Receive, and Transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void smc_enable(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* see the header file for options in TCR/RCR DEFAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SMC_SET_TCR(lp, lp->tcr_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SMC_SET_RCR(lp, lp->rcr_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SMC_SET_MAC_ADDR(lp, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* now, enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (lp->version >= (CHIP_91100 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mask |= IM_MDINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SMC_SET_INT_MASK(lp, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * From this point the register bank must _NOT_ be switched away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * to something else than bank 2 without proper locking against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * races with any tasklet or interrupt handlers until smc_shutdown()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * or smc_reset() is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * this puts the device in an inactive state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void smc_shutdown(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct sk_buff *pending_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* no more interrupts for me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SMC_SET_INT_MASK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pending_skb = lp->pending_tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) lp->pending_tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_kfree_skb(pending_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* and tell the card to stay away from that nasty outside world */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SMC_SET_RCR(lp, RCR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SMC_SET_TCR(lp, TCR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef POWER_DOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* finally, shut the chip down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * This is the procedure to handle the receipt of a packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static inline void smc_rcv(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int packet_number, status, packet_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) packet_number = SMC_GET_RXFIFO(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (unlikely(packet_number & RXFIFO_REMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PRINTK(dev, "smc_rcv with nothing on FIFO.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* read from start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* First two words are status and packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SMC_GET_PKT_HDR(lp, status, packet_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) packet_len &= 0x07ff; /* mask off top bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) packet_number, status, packet_len, packet_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) back:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* accept VLAN packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) status &= ~RS_TOOLONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (packet_len < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* bloody hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) netdev_err(dev, "fubar (rxlen %u status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) packet_len, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) status |= RS_TOOSHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SMC_SET_MMU_CMD(lp, MC_RELEASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (status & RS_ALGNERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (status & (RS_TOOSHORT | RS_TOOLONG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (status & RS_BADCRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* set multicast stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (status & RS_MULTICAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev->stats.multicast++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Actual payload is packet_len - 6 (or 5 if odd byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * We want skb_reserve(2) and the final ctrl word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * (2 bytes, possibly containing the payload odd byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Furthermore, we add 2 bytes to allow rounding up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * multiple of 4 bytes on 32 bit buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Hence packet_len - 6 + 2 + 2 + 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) skb = netdev_alloc_skb(dev, packet_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (unlikely(skb == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SMC_SET_MMU_CMD(lp, MC_RELEASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Align IP header to 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) skb_reserve(skb, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (lp->version == 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) status |= RS_ODDFRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * If odd length: packet_len - 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * otherwise packet_len - 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * With the trailing ctrl byte it's packet_len - 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) data = skb_put(skb, data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SMC_PULL_DATA(lp, data, packet_len - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SMC_SET_MMU_CMD(lp, MC_RELEASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PRINT_PKT(data, packet_len - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev->stats.rx_bytes += data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * On SMP we have the following problem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * A = smc_hardware_send_pkt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * B = smc_hard_start_xmit()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * C = smc_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * A and B can never be executed simultaneously. However, at least on UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * it is possible (and even desirable) for C to interrupt execution of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * A or B in order to have better RX reliability and avoid overruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * C, just like A and B, must have exclusive access to the chip and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * each of them must lock against any other concurrent access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Unfortunately this is not possible to have C suspend execution of A or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * B taking place on another CPU. On UP this is no an issue since A and B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * are run from softirq context and C from hard IRQ context, and there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * no other CPU where concurrent access can happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * If ever there is a way to force at least B and C to always be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * on the same CPU then we could use read/write locks to protect against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * any other concurrent access and C would always interrupt B. But life
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * isn't that easy in a SMP world...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define smc_special_trylock(lock, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) local_irq_save(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __ret = spin_trylock(lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!__ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) local_irq_restore(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define smc_special_trylock(lock, flags) ((void)flags, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define smc_special_lock(lock, flags) do { flags = 0; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define smc_special_unlock(lock, flags) do { flags = 0; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * This is called to actually send a packet to the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void smc_hardware_send_pkt(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct smc_local *lp = from_tasklet(lp, t, tx_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int packet_no, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!smc_special_trylock(&lp->lock, flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tasklet_schedule(&lp->tx_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) skb = lp->pending_tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) smc_special_unlock(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) lp->pending_tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) packet_no = SMC_GET_AR(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (unlikely(packet_no & AR_FAILED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) netdev_err(dev, "Memory allocation failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) smc_special_unlock(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* point to the beginning of the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SMC_SET_PN(lp, packet_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SMC_SET_PTR(lp, PTR_AUTOINC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) buf = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) packet_no, len, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PRINT_PKT(buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Send the packet length (+6 for status words, length, and ctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * The card will pad to 64 bytes with zeroes if packet is too small.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SMC_PUT_PKT_HDR(lp, 0, len + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* send the actual data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SMC_PUSH_DATA(lp, buf, len & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Send final ctl word with the last byte if there is one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DATA_REG(lp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * have the effect of having at most one packet queued for TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * in the chip's memory at all time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * If THROTTLE_TX_PKTS is not set then the queue is stopped only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * when memory allocation (MC_ALLOC) does not succeed right away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (THROTTLE_TX_PKTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* queue the packet for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) smc_special_unlock(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev->stats.tx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) done: if (!THROTTLE_TX_PKTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Since I am not sure if I will have enough room in the chip's ram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * to store the packet, I call this routine which either sends it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * now, or set the card to generates an interrupt when ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * for the packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int numPages, poll_count, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) BUG_ON(lp->pending_tx_skb != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * The MMU wants the number of pages to be the number of 256 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * 'pages', minus 1 (since a packet can't ever have 0 pages :))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * The 91C111 ignores the size bits, but earlier models don't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Pkt size for allocating is data length +6 (for additional status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * words, length and ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * If odd size then last byte is included in ctl word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (unlikely(numPages > 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) netdev_warn(dev, "Far too big packet error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) smc_special_lock(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* now, try to allocate the memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Poll the chip for a short amount of time in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * allocation succeeds quickly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) poll_count = MEMORY_WAIT_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) status = SMC_GET_INT(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (status & IM_ALLOC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SMC_ACK_INT(lp, IM_ALLOC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } while (--poll_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) smc_special_unlock(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) lp->pending_tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!poll_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* oh well, wait until the chip finds memory later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DBG(2, dev, "TX memory allocation deferred.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SMC_ENABLE_INT(lp, IM_ALLOC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Allocation succeeded: push packet to the chip's own memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) smc_hardware_send_pkt(&lp->tx_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * This handles a TX interrupt, which is only called when:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * - a TX error occurred, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void smc_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int saved_packet, packet_no, tx_status, pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* If the TX FIFO is empty then nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) packet_no = SMC_GET_TXFIFO(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (unlikely(packet_no & TXFIFO_TEMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PRINTK(dev, "smc_tx with nothing on FIFO.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* select packet to read from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) saved_packet = SMC_GET_PN(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SMC_SET_PN(lp, packet_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* read the first word (status word) from this packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tx_status, packet_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!(tx_status & ES_TX_SUC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (tx_status & ES_LOSTCARR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (tx_status & (ES_LATCOL | ES_16COL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PRINTK(dev, "%s occurred on last xmit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (tx_status & ES_LATCOL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "late collision" : "too many collisions");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* kill the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SMC_SET_MMU_CMD(lp, MC_FREEPKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Don't restore Packet Number Reg until busy bit is cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) SMC_WAIT_MMU_BUSY(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SMC_SET_PN(lp, saved_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* re-enable transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) SMC_SET_TCR(lp, lp->tcr_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned int mii_reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mii_reg |= MII_MDOE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) for (mask = 1 << (bits - 1); mask; mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mii_reg |= MII_MDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mii_reg &= ~MII_MDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SMC_SET_MII(lp, mii_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) udelay(MII_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SMC_SET_MII(lp, mii_reg | MII_MCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) udelay(MII_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static unsigned int smc_mii_in(struct net_device *dev, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int mii_reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SMC_SET_MII(lp, mii_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (SMC_GET_MII(lp) & MII_MDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) SMC_SET_MII(lp, mii_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) udelay(MII_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SMC_SET_MII(lp, mii_reg | MII_MCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) udelay(MII_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Reads a register from the MII Management serial interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned int phydata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SMC_SELECT_BANK(lp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Idle - 32 ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) smc_mii_out(dev, 0xffffffff, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Start code (01) + read (10) + phyaddr + phyreg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Turnaround (2bits) + phydata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) phydata = smc_mii_in(dev, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Return to idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __func__, phyaddr, phyreg, phydata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return phydata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * Writes a register to the MII Management serial interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int phydata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SMC_SELECT_BANK(lp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Idle - 32 ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) smc_mii_out(dev, 0xffffffff, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Return to idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __func__, phyaddr, phyreg, phydata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Finds and reports the PHY address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void smc_phy_detect(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) lp->phy_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Scan all 32 PHY addresses if necessary, starting at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * PHY#1 to PHY#31, and then PHY#0 last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int id1, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Read the PHY identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) id1, id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Make sure it is a valid identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Save the PHY's address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) lp->mii.phy_id = phyaddr & 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) lp->phy_type = id1 << 16 | id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Sets the PHY to a configuration as determined by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int smc_phy_fixed(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int phyaddr = lp->mii.phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int bmcr, cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Enter Link Disable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) cfg1 |= PHY_CFG1_LNKDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * Set our fixed capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * Disable auto-negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (lp->ctl_rfduplx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (lp->ctl_rspeed == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) bmcr |= BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Write our capabilities to the phy control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Re-Configure the Receive/Phy Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SMC_SET_RPC(lp, lp->rpc_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * smc_phy_reset - reset the phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * @phy: phy address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Issue a software reset for the specified PHY and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * wait up to 100ms for the reset to complete. We should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * not access the PHY for 50ms after issuing the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * The time to wait appears to be dependent on the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * Must be called with lp->lock locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int smc_phy_reset(struct net_device *dev, int phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned int bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) for (timeout = 2; timeout; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bmcr = smc_phy_read(dev, phy, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!(bmcr & BMCR_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return bmcr & BMCR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * smc_phy_powerdown - powerdown phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Power down the specified PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void smc_phy_powerdown(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) unsigned int bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int phy = lp->mii.phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (lp->phy_type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* We need to ensure that no calls to smc_phy_configure are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) cancel_work_sync(&lp->phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) bmcr = smc_phy_read(dev, phy, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * smc_phy_check_media - check the media status and adjust TCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * @init: set true for initialisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Select duplex mode depending on negotiation state. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * also updates our carrier state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static void smc_phy_check_media(struct net_device *dev, int init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* duplex state has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (lp->mii.full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) lp->tcr_cur_mode |= TCR_SWFDUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) lp->tcr_cur_mode &= ~TCR_SWFDUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SMC_SET_TCR(lp, lp->tcr_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Configures the specified PHY through the MII management interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * using Autonegotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Calls smc_phy_fixed() if the user has requested a certain config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * If RPC ANEG bit is set, the media selection is dependent purely on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * the selection by the MII (either in the MII BMCR reg or the result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * is controlled by the RPC SPEED and RPC DPLX bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void smc_phy_configure(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct smc_local *lp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) container_of(work, struct smc_local, phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int phyaddr = lp->mii.phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int my_phy_caps; /* My PHY capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int my_ad_caps; /* My Advertised capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) DBG(3, dev, "smc_program_phy()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * We should not be called if phy_type is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (lp->phy_type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto smc_phy_configure_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (smc_phy_reset(dev, phyaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) netdev_info(dev, "PHY reset timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) goto smc_phy_configure_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * Enable PHY Interrupts (for register 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * Interrupts listed here are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) smc_phy_write(dev, phyaddr, PHY_MASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PHY_INT_SPDDET | PHY_INT_DPLXDET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Configure the Receive/Phy Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SMC_SET_RPC(lp, lp->rpc_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* If the user requested no auto neg, then go set his request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (lp->mii.force_media) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) smc_phy_fixed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto smc_phy_configure_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) netdev_info(dev, "Auto negotiation NOT supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) smc_phy_fixed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) goto smc_phy_configure_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (my_phy_caps & BMSR_100BASE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) my_ad_caps |= ADVERTISE_100BASE4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (my_phy_caps & BMSR_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) my_ad_caps |= ADVERTISE_100FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (my_phy_caps & BMSR_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) my_ad_caps |= ADVERTISE_100HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (my_phy_caps & BMSR_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) my_ad_caps |= ADVERTISE_10FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (my_phy_caps & BMSR_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) my_ad_caps |= ADVERTISE_10HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Disable capabilities not selected by our user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (lp->ctl_rspeed != 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!lp->ctl_rfduplx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Update our Auto-Neg Advertisement Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) lp->mii.advertising = my_ad_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * Read the register back. Without this, it appears that when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * auto-negotiation is restarted, sometimes it isn't ready and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * the link does not come up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) smc_phy_read(dev, phyaddr, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) DBG(2, dev, "phy caps=%x\n", my_phy_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Restart auto-negotiation process in order to advertise my caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) smc_phy_check_media(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) smc_phy_configure_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * smc_phy_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * Purpose: Handle interrupts relating to PHY register 18. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * called from the "hard" interrupt handler under our private spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static void smc_phy_interrupt(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int phyaddr = lp->mii.phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int phy18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (lp->phy_type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) smc_phy_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Read PHY Register 18, Status Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if ((phy18 & PHY_INT_INT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void smc_10bt_check_media(struct net_device *dev, int init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) unsigned int old_carrier, new_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) old_carrier = netif_carrier_ok(dev) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (init || (old_carrier != new_carrier)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (!new_carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (netif_msg_link(lp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) netdev_info(dev, "link %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) new_carrier ? "up" : "down");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void smc_eph_interrupt(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) smc_10bt_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ctl = SMC_GET_CTL(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SMC_SET_CTL(lp, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * This is the main routine of the driver, to handle the device when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * it needs some attention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static irqreturn_t smc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int status, mask, timeout, card_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int saved_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) DBG(3, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) spin_lock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* A preamble may be used when there is a potential race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * between the interruptible transmit functions and this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * ISR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SMC_INTERRUPT_PREAMBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) saved_pointer = SMC_GET_PTR(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) mask = SMC_GET_INT_MASK(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) SMC_SET_INT_MASK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* set a timeout value, so I don't stay here forever */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) timeout = MAX_IRQ_LOOPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) status = SMC_GET_INT(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) status, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ({ int meminfo; SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) meminfo = SMC_GET_MIR(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SMC_SELECT_BANK(lp, 2); meminfo; }),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SMC_GET_FIFO(lp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) status &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (status & IM_TX_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* do this before RX as it will free memory quickly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) DBG(3, dev, "TX int\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) smc_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SMC_ACK_INT(lp, IM_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (THROTTLE_TX_PKTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) } else if (status & IM_RCV_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DBG(3, dev, "RX irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) smc_rcv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) } else if (status & IM_ALLOC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DBG(3, dev, "Allocation irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) tasklet_hi_schedule(&lp->tx_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mask &= ~IM_ALLOC_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) } else if (status & IM_TX_EMPTY_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) DBG(3, dev, "TX empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mask &= ~IM_TX_EMPTY_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* update stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) card_stats = SMC_GET_COUNTER(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* single collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev->stats.collisions += card_stats & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) card_stats >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* multiple collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dev->stats.collisions += card_stats & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) } else if (status & IM_RX_OVRN_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ({ int eph_st; SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) eph_st = SMC_GET_EPH_STATUS(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SMC_SELECT_BANK(lp, 2); eph_st; }));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SMC_ACK_INT(lp, IM_RX_OVRN_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else if (status & IM_EPH_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) smc_eph_interrupt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) } else if (status & IM_MDINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SMC_ACK_INT(lp, IM_MDINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) smc_phy_interrupt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) } else if (status & IM_ERCV_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) SMC_ACK_INT(lp, IM_ERCV_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* restore register states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SMC_SET_PTR(lp, saved_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) SMC_SET_INT_MASK(lp, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) spin_unlock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #ifndef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (timeout == MAX_IRQ_LOOPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) DBG(3, dev, "Interrupt done (%d loops)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MAX_IRQ_LOOPS - timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * We return IRQ_HANDLED unconditionally here even if there was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * nothing to do. There is a possibility that a packet might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * get enqueued into the chip right after TX_EMPTY_INT is raised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * but just before the CPU acknowledges the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * Better take an unneeded IRQ in some occasions than complexifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * the code for all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * Polling receive - used by netconsole and other diagnostic tools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * to allow network i/o with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static void smc_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) smc_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Our watchdog timed out. Called by the networking layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static void smc_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int status, mask, eph_st, meminfo, fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) status = SMC_GET_INT(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) mask = SMC_GET_INT_MASK(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) fifo = SMC_GET_FIFO(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) eph_st = SMC_GET_EPH_STATUS(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) meminfo = SMC_GET_MIR(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) status, mask, meminfo, fifo, eph_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) smc_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) smc_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * Reconfiguring the PHY doesn't seem like a bad idea here, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * smc_phy_configure() calls msleep() which calls schedule_timeout()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * which calls schedule(). Hence we use a work queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (lp->phy_type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) schedule_work(&lp->phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* We can accept TX packets again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * This routine will, depending on the values passed to it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * either make it accept multicast packets, go into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * promiscuous mode (for TCPDUMP and cousins) or accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * a select set of multicast packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static void smc_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) unsigned char multicast_table[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) int update_multicast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) DBG(2, dev, "RCR_PRMS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) lp->rcr_cur_mode |= RCR_PRMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* BUG? I never disable promiscuous mode if multicasting was turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) Now, I turn off promiscuous mode, but I don't do anything to multicasting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) when promiscuous mode is turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * Here, I am setting this to accept all multicast packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * I don't need to zero the multicast table, because the flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * checked before the table is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) DBG(2, dev, "RCR_ALMUL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) lp->rcr_cur_mode |= RCR_ALMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * This sets the internal hardware table to filter out unwanted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * multicast packets before they take up memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * The SMC chip uses a hash table where the high 6 bits of the CRC of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * address are the offset into the table. If that bit is 1, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * multicast packet is accepted. Otherwise, it's dropped silently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * To use the 6 bits as an offset into the table, the high 3 bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * the number of the 8 bit register, while the low 3 bits are the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * within that register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) else if (!netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* table for flipping the order of 3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* start with a table of all zeros: reject all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) memset(multicast_table, 0, sizeof(multicast_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) int position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* only use the low order bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) position = crc32_le(~0, ha->addr, 6) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* do some messy swapping to put the bit in the right spot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) multicast_table[invert3[position&7]] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) (1<<invert3[(position>>3)&7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* be sure I get rid of flags I might have set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* now, the table can be loaded into the chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) update_multicast = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * since I'm disabling all multicast entirely, I need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * clear the multicast list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) memset(multicast_table, 0, sizeof(multicast_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) update_multicast = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SMC_SET_RCR(lp, lp->rcr_cur_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (update_multicast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) SMC_SELECT_BANK(lp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SMC_SET_MCAST(lp, multicast_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * Open and Initialize the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * Set up everything, reset the card, etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) smc_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Setup the default Register Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) lp->tcr_cur_mode = TCR_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) lp->rcr_cur_mode = RCR_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) lp->rpc_cur_mode = RPC_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) lp->cfg.leda << RPC_LSXA_SHFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) lp->cfg.ledb << RPC_LSXB_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * If we are not using a MII interface, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * monitor our own carrier signal to detect faults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (lp->phy_type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) lp->tcr_cur_mode |= TCR_MON_CSN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* reset the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) smc_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) smc_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Configure the PHY, initialize the link state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (lp->phy_type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) smc_phy_configure(&lp->phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) smc_10bt_check_media(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * smc_close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * this makes the board clean up everything that it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * and not talk to the outside world. Caused by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * an 'ifconfig ethX down'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int smc_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) DBG(2, dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* clear everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) smc_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) tasklet_kill(&lp->tx_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) smc_phy_powerdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * Ethtool support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) smc_ethtool_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (lp->phy_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) mii_ethtool_get_link_ksettings(&lp->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u32 supported = SUPPORTED_10baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) SUPPORTED_10baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) SUPPORTED_TP | SUPPORTED_AUI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (lp->ctl_rspeed == 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) cmd->base.speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) else if (lp->ctl_rspeed == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) cmd->base.speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) cmd->base.autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) cmd->base.port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ethtool_convert_legacy_u32_to_link_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) cmd->link_modes.supported, supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) smc_ethtool_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (lp->phy_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (cmd->base.autoneg != AUTONEG_DISABLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) cmd->base.speed != SPEED_10 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) (cmd->base.duplex != DUPLEX_HALF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) cmd->base.duplex != DUPLEX_FULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) // lp->port = cmd->base.port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) // if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) // smc_set_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) strlcpy(info->driver, CARDNAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) strlcpy(info->version, version, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) strlcpy(info->bus_info, dev_name(dev->dev.parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int smc_ethtool_nwayreset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (lp->phy_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ret = mii_nway_restart(&lp->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static u32 smc_ethtool_getmsglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return lp->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) lp->msg_enable = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* load word into GP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) SMC_SET_GP(lp, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* set the address to put the data in EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) SMC_SET_PTR(lp, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* tell it to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ctl = SMC_GET_CTL(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* wait for it to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) } while (SMC_GET_CTL(lp) & CTL_STORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* clean up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) SMC_SET_CTL(lp, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* set the EEPROM address to get the data from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) SMC_SET_PTR(lp, addr | PTR_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* tell it to load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) SMC_SET_GP(lp, 0xffff); /* init to known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ctl = SMC_GET_CTL(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* wait for it to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) } while (SMC_GET_CTL(lp) & CTL_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* read word from GP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) *word = SMC_GET_GP(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* clean up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) SMC_SET_CTL(lp, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static int smc_ethtool_geteeprom_len(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0x23 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int smc_ethtool_geteeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int imax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) DBG(1, dev, "Reading %d bytes at %d(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) eeprom->len, eeprom->offset, eeprom->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) imax = smc_ethtool_geteeprom_len(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) for (i = 0; i < eeprom->len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u16 wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int offset = i + eeprom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (offset > imax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) data[i] = (wbuf >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) data[i+1] = wbuf & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int smc_ethtool_seteeprom(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct ethtool_eeprom *eeprom, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) int imax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) DBG(1, dev, "Writing %d bytes to %d(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) eeprom->len, eeprom->offset, eeprom->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) imax = smc_ethtool_geteeprom_len(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) for (i = 0; i < eeprom->len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u16 wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) int offset = i + eeprom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (offset > imax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) wbuf = (data[i] << 8) | data[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const struct ethtool_ops smc_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .get_drvinfo = smc_ethtool_getdrvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .get_msglevel = smc_ethtool_getmsglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .set_msglevel = smc_ethtool_setmsglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .nway_reset = smc_ethtool_nwayreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .get_eeprom_len = smc_ethtool_geteeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .get_eeprom = smc_ethtool_geteeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .set_eeprom = smc_ethtool_seteeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .get_link_ksettings = smc_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .set_link_ksettings = smc_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const struct net_device_ops smc_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .ndo_open = smc_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .ndo_stop = smc_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ndo_start_xmit = smc_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .ndo_tx_timeout = smc_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .ndo_set_rx_mode = smc_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .ndo_poll_controller = smc_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * smc_findirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * This routine has a simple purpose -- make the SMC chip generate an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * interrupt, so an auto-detect routine can detect it, and find the IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * does this still work?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * I just deleted auto_irq.c, since it was never built...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * --jgarzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static int smc_findirq(struct smc_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) void __iomem *ioaddr = lp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) int timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) unsigned long cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) cookie = probe_irq_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * What I try to do here is trigger an ALLOC_INT. This is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * by allocating a small chunk of memory, which will give an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * when done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* enable ALLOCation interrupts ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SMC_SELECT_BANK(lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * Allocate 512 bytes of memory. Note that the chip was just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * reset so all the memory is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * Wait until positive that the interrupt has been generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) int int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) int_status = SMC_GET_INT(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (int_status & IM_ALLOC_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) break; /* got the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * there is really nothing that I can do here if timeout fails,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * as autoirq_report will return a 0 anyway, which is what I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * want in this case. Plus, the clean up is needed in both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* and disable all interrupts again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SMC_SET_INT_MASK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /* and return what I found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return probe_irq_off(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * Function: smc_probe(unsigned long ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * Purpose:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * Tests to see if a given ioaddr points to an SMC91x chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * Returns a 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * Algorithm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * (1) see if the high byte of BANK_SELECT is 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * (2) compare the ioaddr with the base register's address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * (3) see if I recognize the chip ID in the appropriate register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * Here I do typical initialization tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * o Initialize the structure if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * o print out my vanity message if not done so already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * o print out what type of hardware is detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * o print out the ethernet address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * o find the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * o set up my private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * o configure the dev structure with my subroutines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * o actually GRAB the irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * o GRAB the region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static int smc_probe(struct net_device *dev, void __iomem *ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) unsigned long irq_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) struct smc_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) unsigned int val, revision_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) const char *version_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* First, see if the high byte is 0x33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) val = SMC_CURRENT_BANK(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) DBG(2, dev, "%s: bank signature probe returned 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) CARDNAME, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if ((val & 0xFF00) != 0x3300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if ((val & 0xFF) == 0x33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) netdev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "%s: Detected possible byte-swapped interface at IOADDR %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) CARDNAME, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * The above MIGHT indicate a device, but I need to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * further test this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) SMC_SELECT_BANK(lp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) val = SMC_CURRENT_BANK(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if ((val & 0xFF00) != 0x3300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * well, we've already written once, so hopefully another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * time won't hurt. This time, I need to switch the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * register to bank 1, so I can access the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) val = SMC_GET_BASE(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) CARDNAME, ioaddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * check if the revision register is something that I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * recognize. These might need to be added to later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * as future revisions could be added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) SMC_SELECT_BANK(lp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) revision_register = SMC_GET_REV(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) version_string = chip_ids[ (revision_register >> 4) & 0xF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (!version_string || (revision_register & 0xff00) != 0x3300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /* I don't recognize this chip, so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) CARDNAME, ioaddr, revision_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* At this point I'll assume that the chip is an SMC91x. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) pr_info_once("%s\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* fill in some of the fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev->base_addr = (unsigned long)ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) lp->base = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) lp->version = revision_register & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) spin_lock_init(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Get the MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) SMC_SELECT_BANK(lp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) SMC_GET_MAC_ADDR(lp, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* now, reset the chip, and put it into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) smc_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * If dev->irq is 0, then the device has to be banged on to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * what the IRQ is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * This banging doesn't always detect the IRQ, for unknown reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * a workaround is to reset the chip and try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) * be what is requested on the command line. I don't do that, mostly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * because the card that I have uses a non-standard method of accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * the IRQs, and because this _should_ work in most configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * Specifying an IRQ is done with the assumption that the user knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * what (s)he is doing. No checking is done!!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (dev->irq < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int trials;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) trials = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) while (trials--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) dev->irq = smc_findirq(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* kick the card and try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) smc_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (dev->irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dev->irq = irq_canonicalize(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dev->watchdog_timeo = msecs_to_jiffies(watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dev->netdev_ops = &smc_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev->ethtool_ops = &smc_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) tasklet_setup(&lp->tx_task, smc_hardware_send_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) INIT_WORK(&lp->phy_configure, smc_phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) lp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) lp->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) lp->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) lp->mii.force_media = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) lp->mii.full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) lp->mii.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) lp->mii.mdio_read = smc_phy_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) lp->mii.mdio_write = smc_phy_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * Locate the phy, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (lp->version >= (CHIP_91100 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) smc_phy_detect(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* then shut everything down to save power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) smc_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) smc_phy_powerdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* Set default parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) lp->msg_enable = NETIF_MSG_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) lp->ctl_rfduplx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) lp->ctl_rspeed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (lp->version >= (CHIP_91100 << 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) lp->ctl_rfduplx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) lp->ctl_rspeed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Grab the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #ifdef CONFIG_ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) # ifdef SMC_USE_PXA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) lp->cfg.flags |= SMC91X_USE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (lp->cfg.flags & SMC91X_USE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) lp->dma_chan = dma_request_channel(mask, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) retval = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* now, print out the card info, in a short format.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) netdev_info(dev, "%s (rev %d) at %p IRQ %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) version_string, revision_register & 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) lp->base, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (lp->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) pr_cont(" DMA %p", lp->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) pr_cont("%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (!is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /* Print the Ethernet address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) netdev_info(dev, "Ethernet addr: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (lp->phy_type == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) PRINTK(dev, "No PHY found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) PRINTK(dev, "PHY LAN83C180\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #ifdef CONFIG_ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (retval && lp->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dma_release_channel(lp->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static int smc_enable_device(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) unsigned char ecor, ecsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct resource * res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * Map the attribute space. This is overkill, but clean.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) addr = ioremap(res->start, ATTRIB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * Reset the device. We must disable IRQs around this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * since a reset causes the IRQ line become active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) readb(addr + (ECOR << SMC_IO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * Wait 100us for the chip to reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * The device will ignore all writes to the enable bit while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * reset is asserted, even if the reset bit is cleared in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * same write. Must clear reset first, then enable the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * Set the appropriate byte/word mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (!SMC_16BIT(lp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ecsr |= ECSR_IOIS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * Wait for the chip to wake up. We could poll the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * register in the main register space, but that isn't mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * yet. We know this is going to take 750us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static int smc_request_attrib(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct smc_local *lp __maybe_unused = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) static void smc_release_attrib(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct smc_local *lp __maybe_unused = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) release_mem_region(res->start, ATTRIB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (SMC_CAN_USE_DATACS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) netdev_info(ndev, "%s: failed to request datacs memory region.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) CARDNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (SMC_CAN_USE_DATACS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (lp->datacs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) iounmap(lp->datacs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) lp->datacs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) release_mem_region(res->start, SMC_DATA_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static const struct acpi_device_id smc91x_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) { "LNRO0003", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #if IS_BUILTIN(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static const struct of_device_id smc91x_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) { .compatible = "smsc,lan91c94", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) { .compatible = "smsc,lan91c111", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) MODULE_DEVICE_TABLE(of, smc91x_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * of_try_set_control_gpio - configure a gpio if it exists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static int try_toggle_control_gpio(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct gpio_desc **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) const char *name, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) int value, unsigned int nsdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) struct gpio_desc *gpio = *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) gpio = devm_gpiod_get_index_optional(dev, name, index, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (nsdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) usleep_range(nsdelay, 2 * nsdelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) gpiod_set_value_cansleep(gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) *desc = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * smc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) * Input parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) * dev->base_addr == 0, try to find all possible locations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) * dev->base_addr > 0x1ff, this is the address to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) * dev->base_addr == <anything else>, return failure code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * 0 --> there is a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * anything else, error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static int smc_drv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) const struct of_device_id *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct smc_local *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) unsigned int __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) unsigned long irq_flags = SMC_IRQ_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) unsigned long irq_resflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ndev = alloc_etherdev(sizeof(struct smc_local));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (!ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /* get configuration from platform data, only allow use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) lp->cfg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) memcpy(&lp->cfg, pd, sizeof(lp->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) "at least one of 8-bit or 16-bit access support is required.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) goto out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) #if IS_BUILTIN(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) /* Optional pwrdwn GPIO configured? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) "power", 0, 0, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) goto out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * Optional reset GPIO configured? Minimum 100 ns reset needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * according to LAN91C96 datasheet page 14.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) "reset", 0, 0, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) goto out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * Need to wait for optional EEPROM to load, max 750 us according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) * to LAN91C96 datasheet page 55.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (lp->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) usleep_range(750, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* Combination of IO widths supported, default to 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (!device_property_read_u32(&pdev->dev, "reg-io-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (val & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) lp->cfg.flags |= SMC91X_USE_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if ((val == 0) || (val & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) lp->cfg.flags |= SMC91X_USE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (val & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) lp->cfg.flags |= SMC91X_USE_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) lp->cfg.flags |= SMC91X_USE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (!device_property_read_u32(&pdev->dev, "reg-shift",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) lp->io_shift = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) lp->cfg.pxa_u16_align4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) device_property_read_bool(&pdev->dev, "pxa-u16-align4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (!pd && !match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) if (!lp->cfg.leda && !lp->cfg.ledb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) lp->cfg.leda = RPC_LSA_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) lp->cfg.ledb = RPC_LSB_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ndev->dma = (unsigned char)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) goto out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) goto out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ndev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if (ndev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ret = ndev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) goto out_release_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * If this platform does not specify any special irqflags, or if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) * the resource supplies a trigger, override the irqflags with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) * the trigger flags from the resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) irq_flags = irq_resflags & IRQF_TRIGGER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ret = smc_request_attrib(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) goto out_release_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #if defined(CONFIG_ASSABET_NEPONSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if (machine_is_assabet() && machine_has_neponset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) neponset_ncr_set(NCR_ENET_OSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) platform_set_drvdata(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ret = smc_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) goto out_release_attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) addr = ioremap(res->start, SMC_IO_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto out_release_attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #ifdef CONFIG_ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) lp->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) lp->physaddr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ret = smc_probe(ndev, addr, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) smc_request_datacs(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) out_release_attrib:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) smc_release_attrib(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) out_release_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) release_mem_region(res->start, SMC_IO_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) out_free_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) pr_info("%s: not found (%d).\n", CARDNAME, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static int smc_drv_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) free_irq(ndev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) #ifdef CONFIG_ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (lp->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) dma_release_channel(lp->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) iounmap(lp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) smc_release_datacs(pdev,ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) smc_release_attrib(pdev,ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) release_mem_region(res->start, SMC_IO_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static int smc_drv_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) if (ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) netif_device_detach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) smc_shutdown(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) smc_phy_powerdown(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static int smc_drv_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) struct smc_local *lp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) smc_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) smc_reset(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) smc_enable(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (lp->phy_type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) smc_phy_configure(&lp->phy_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) netif_device_attach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const struct dev_pm_ops smc_drv_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .suspend = smc_drv_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .resume = smc_drv_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static struct platform_driver smc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .probe = smc_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .remove = smc_drv_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .name = CARDNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .pm = &smc_drv_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .of_match_table = of_match_ptr(smc91x_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .acpi_match_table = smc91x_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) module_platform_driver(smc_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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