Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  . smc9194.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  . Copyright (C) 1996 by Erik Stahlman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  . This software may be used and distributed according to the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  . of the GNU General Public License, incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  . This file contains register information and access macros for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  . the SMC91xxx chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  . Information contained in this file was obtained from the SMC91C94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  . manual from SMC.  To get a copy, if you really want one, you can find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  . information under www.smc.com in the components division.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  . ( this thanks to advice from Donald Becker ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  . Authors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  . 	Erik Stahlman				( erik@vt.edu )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  . History
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  . 01/06/96		 Erik Stahlman   moved definitions here from main .c file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  . 01/19/96		 Erik Stahlman	  polished this up some, and added better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  .										  error handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  ---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #ifndef _SMC9194_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define _SMC9194_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* I want some simple types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) typedef unsigned char			byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) typedef unsigned short			word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) typedef unsigned long int 		dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SMC_IO_EXTENT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  . A description of the SMC registers is probably in order here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  . although for details, the SMC datasheet is invaluable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  . are accessed by writing a number into the BANK_SELECT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  . ( I also use a SMC_SELECT_BANK macro for this ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  . The banks are configured so that for most purposes, bank 2 is all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  . that is needed for simple run time tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  -----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  . Bank Select Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  .		yyyy yyyy 0000 00xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  .		xx 		= bank number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  .		yyyy yyyy	= 0x33, for identification purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	BANK_SELECT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* BANK 0  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	TCR 		0    	/* transmit control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TCR_ENABLE	0x0001	/* if this is 1, we can transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TCR_FDUPLX    	0x0800  /* receive packets sent out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TCR_STP_SQET	0x1000	/* stop transmitting if Signal quality error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	TCR_MON_CNS	0x0400	/* monitors the carrier status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	TCR_PAD_ENABLE	0x0080	/* pads short packets to 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	TCR_CLEAR	0	/* do NOTHING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* the normal settings for the TCR register : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* QUESTION: do I want to enable padding of short packets ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	TCR_NORMAL  	TCR_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define EPH_STATUS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ES_LINK_OK	0x4000	/* is the link integrity ok ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define	RCR		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RCR_SOFTRESET	0x8000 	/* resets the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define	RCR_STRIP_CRC	0x200	/* strips CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RCR_ENABLE	0x100	/* IFF this is set, we can receive packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define RCR_ALMUL	0x4 	/* receive all multicast packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	RCR_PROMISC	0x2	/* enable promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* the normal settings for the RCR register : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	RCR_NORMAL	(RCR_STRIP_CRC | RCR_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define RCR_CLEAR	0x0		/* set it to a base state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	COUNTER		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	MIR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	MCR		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* 12 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* BANK 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CONFIG			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CFG_AUI_SELECT	 	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	BASE			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	ADDR0			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	ADDR1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	ADDR2			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define	GENERAL			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define	CONTROL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define	CTL_POWERDOWN		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	CTL_LE_ENABLE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define	CTL_CR_ENABLE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	CTL_TE_ENABLE		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CTL_AUTO_RELEASE	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define	CTL_EPROM_ACCESS	0x0003 /* high if Eprom is being read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* BANK 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MMU_CMD		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MC_BUSY		1	/* only readable bit in the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MC_NOP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	MC_ALLOC	0x20  	/* or with number of 256 byte packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define	MC_RESET	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	MC_REMOVE	0x60  	/* remove the current rx packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MC_RELEASE  	0x80  	/* remove and release the current rx packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MC_FREEPKT  	0xA0  	/* Release packet in PNR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MC_ENQUEUE	0xC0 	/* Enqueue the packet for transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define	PNR_ARR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FIFO_PORTS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FP_RXEMPTY  0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FP_TXEMPTY  0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	POINTER		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PTR_READ	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	PTR_RCV		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	PTR_AUTOINC 	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PTR_AUTO_INC	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	DATA_1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	DATA_2		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	INTERRUPT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define INT_MASK	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IM_RCV_INT	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define	IM_TX_INT	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	IM_TX_EMPTY_INT	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	IM_ALLOC_INT	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	IM_RX_OVRN_INT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define	IM_EPH_INT	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define	IM_ERCV_INT	0x40 /* not on SMC9192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* BANK 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define	MULTICAST1	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define	MULTICAST2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	MULTICAST3	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define	MULTICAST4	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define	MGMT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define	REVISION	10 /* ( hi: chip id   low: rev # ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* this is NOT on SMC9192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define	ERCV		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CHIP_9190	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CHIP_9194	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CHIP_9195	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CHIP_91100	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const char * chip_ids[ 15 ] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* 3 */ "SMC91C90/91C92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* 4 */ "SMC91C94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* 5 */ "SMC91C95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* 7 */ "SMC91C100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* 8 */ "SMC91C100FD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	NULL, NULL, NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  . Transmit status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TS_SUCCESS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TS_LOSTCAR 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TS_LATCOL  0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TS_16COL   0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  . Receive status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RS_ALGNERR	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RS_BADCRC	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RS_ODDFRAME	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RS_TOOLONG	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RS_TOOSHORT	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RS_MULTICAST	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * interfaces[ 2 ] = { "TP", "AUI" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  .  I define some macros to make it easier to do somewhat common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  . or slightly complicated, repeated tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* select a register bank, 0 to 3  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SMC_SELECT_BANK(x)  { outw( x, ioaddr + BANK_SELECT ); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* define a small delay for the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SMC_DELAY() { inw( ioaddr + RCR );\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			inw( ioaddr + RCR );\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			inw( ioaddr + RCR );  }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* this enables an interrupt in the interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SMC_ENABLE_INT(x) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		unsigned char mask;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		SMC_SELECT_BANK(2);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		mask = inb( ioaddr + INT_MASK );\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		mask |= (x);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		outb( mask, ioaddr + INT_MASK ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* this disables an interrupt from the interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SMC_DISABLE_INT(x) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		unsigned char mask;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		SMC_SELECT_BANK(2);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		mask = inb( ioaddr + INT_MASK );\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		mask &= ~(x);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		outb( mask, ioaddr + INT_MASK ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  . Define the interrupts that I want to receive from the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  . I want:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  .  IM_EPH_INT, for nasty errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  .  IM_RCV_INT, for happy received packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  .  IM_RX_OVRN_INT, because I have to kick the receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif  /* _SMC_9194_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)