^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) . Copyright (C) 2005 Sensoria Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) . Derived from the unified SMC91x driver by Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) . Information contained in this file was obtained from the LAN9118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) . manual from SMC. To get a copy, if you really want one, you can find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) . information under www.smsc.com.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) . Authors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) . Dustin McIntire <dustin@sensoria.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef _SMC911X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _SMC911X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/smc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Use the DMA feature on PXA chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef CONFIG_ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMC_USE_PXA_DMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SMC_USE_16BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SMC_USE_32BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMC_USE_16BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMC_USE_32BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #elif defined(CONFIG_ARCH_OMAP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMC_USE_16BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMC_USE_32BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SMC_MEM_RESERVED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #elif defined(CONFIG_ARCH_OMAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMC_USE_16BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMC_USE_32BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMC_MEM_RESERVED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Default configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMC_DYNAMIC_BUS_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef SMC_USE_PXA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SMC_USE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* store this information for the driver.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct smc911x_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * If I have to wait until the DMA is finished and ready to reload a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * packet, I will store the skbuff here. Then, the DMA will send it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * out and free it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct sk_buff *pending_tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* version/revision of the SMC911x chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int tx_fifo_kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int afc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Contains the current active receive/phy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ctl_rfduplx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ctl_rspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mii_if_info mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct work_struct phy_configure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int tx_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef SMC_USE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* DMA needs the physical address of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u_long physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dma_chan *rxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dma_chan *txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int rxdma_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int txdma_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct sk_buff *current_rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sk_buff *current_tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef SMC_DYNAMIC_BUS_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct smc911x_platdata cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Define the bus width specific IO macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef SMC_DYNAMIC_BUS_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *ioaddr = lp->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (lp->cfg.flags & SMC911X_USE_32BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return readl(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (lp->cfg.flags & SMC911X_USE_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return readw(ioaddr) | (readw(ioaddr + 2) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __iomem *ioaddr = lp->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (lp->cfg.flags & SMC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(value, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (lp->cfg.flags & SMC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writew(value & 0xffff, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writew(value >> 16, ioaddr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void SMC_insl(struct smc911x_local *lp, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void *addr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *ioaddr = lp->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (lp->cfg.flags & SMC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ioread32_rep(ioaddr, addr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (lp->cfg.flags & SMC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ioread16_rep(ioaddr, addr, count * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void SMC_outsl(struct smc911x_local *lp, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void *addr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *ioaddr = lp->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (lp->cfg.flags & SMC911X_USE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) iowrite32_rep(ioaddr, addr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (lp->cfg.flags & SMC911X_USE_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iowrite16_rep(ioaddr, addr, count * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #if SMC_USE_16BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SMC_outl(v, lp, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) do{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writew(v & 0xFFFF, (lp)->base + (r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writew(v >> 16, (lp)->base + (r) + 2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SMC_insl(lp, r, p, l) ioread16_rep((short*)((lp)->base + (r)), p, l*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SMC_outsl(lp, r, p, l) iowrite16_rep((short*)((lp)->base + (r)), p, l*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #elif SMC_USE_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SMC_inl(lp, r) readl((lp)->base + (r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SMC_insl(lp, r, p, l) ioread32_rep((int*)((lp)->base + (r)), p, l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SMC_outsl(lp, r, p, l) iowrite32_rep((int*)((lp)->base + (r)), p, l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* SMC_USE_16BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif /* SMC_DYNAMIC_BUS_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #ifdef SMC_USE_PXA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Use a DMA for RX and TX packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static dma_addr_t rx_dmabuf, tx_dmabuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int rx_dmalen, tx_dmalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void smc911x_rx_dma_irq(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void smc911x_tx_dma_irq(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef SMC_insl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #undef SMC_insl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SMC_insl(lp, r, p, l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int reg, struct dma_chan *dma, u_char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 64 bit alignment is required for memory to memory DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if ((long)buf & 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *((u32 *)buf) = SMC_inl(lp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) len *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rx_dmalen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tx = dmaengine_prep_slave_single(dma, rx_dmabuf, rx_dmalen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DMA_DEV_TO_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tx->callback = smc911x_rx_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tx->callback_param = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dma_async_issue_pending(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifdef SMC_outsl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #undef SMC_outsl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SMC_outsl(lp, r, p, l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int reg, struct dma_chan *dma, u_char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 64 bit alignment is required for memory to memory DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if ((long)buf & 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SMC_outl(*((u32 *)buf), lp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) len *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tx_dmalen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tx = dmaengine_prep_slave_single(dma, tx_dmabuf, tx_dmalen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DMA_DEV_TO_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tx->callback = smc911x_tx_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tx->callback_param = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_async_issue_pending(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif /* SMC_USE_PXA_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Chip Parameters and Register Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SMC911X_IO_EXTENT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SMC911X_EEPROM_LEN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Below are the register offsets and bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * of the Lan911x memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RX_DATA_FIFO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TX_DATA_FIFO (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TX_CMD_A_INT_ON_COMP_ (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TX_CMD_A_BUF_SIZE_ (0x000007FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define RX_STATUS_FIFO (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RX_STS_PKT_LEN_ (0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define RX_STS_ES_ (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define RX_STS_BCST_ (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RX_STS_LEN_ERR_ (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RX_STS_RUNT_ERR_ (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RX_STS_MCAST_ (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RX_STS_TOO_LONG_ (0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RX_STS_COLL_ (0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RX_STS_ETH_TYPE_ (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RX_STS_WDOG_TMT_ (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RX_STS_MII_ERR_ (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RX_STS_DRIBBLING_ (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RX_STS_CRC_ERR_ (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RX_STATUS_FIFO_PEEK (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TX_STATUS_FIFO (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TX_STS_TAG_ (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TX_STS_ES_ (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TX_STS_LOC_ (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TX_STS_NO_CARR_ (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TX_STS_LATE_COLL_ (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TX_STS_MANY_COLL_ (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TX_STS_COLL_CNT_ (0x00000078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TX_STS_MANY_DEFER_ (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TX_STS_UNDERRUN_ (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TX_STS_DEFERRED_ (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TX_STATUS_FIFO_PEEK (0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ID_REV (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define INT_CFG (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INT_CFG_INT_DEAS_CLR_ (0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define INT_CFG_INT_DEAS_STS_ (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define INT_STS (0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define INT_STS_SW_INT_ (0x80000000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define INT_STS_PHY_INT_ (0x00040000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define INT_STS_PME_INT_ (0x00020000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define INT_STS_TXSO_ (0x00010000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define INT_STS_RWT_ (0x00008000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define INT_STS_RXE_ (0x00004000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define INT_STS_TXE_ (0x00002000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) //#define INT_STS_ERX_ (0x00001000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define INT_STS_TDFU_ (0x00000800) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define INT_STS_TDFO_ (0x00000400) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define INT_STS_TDFA_ (0x00000200) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define INT_STS_TSFF_ (0x00000100) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define INT_STS_TSFL_ (0x00000080) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) //#define INT_STS_RXDF_ (0x00000040) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define INT_STS_RDFO_ (0x00000040) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define INT_STS_RDFL_ (0x00000020) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define INT_STS_RSFF_ (0x00000010) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define INT_STS_RSFL_ (0x00000008) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define INT_EN (0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define INT_EN_RWT_EN_ (0x00008000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define INT_EN_RXE_EN_ (0x00004000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define INT_EN_TXE_EN_ (0x00002000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define BYTE_TEST (0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define FIFO_INT (0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RX_CFG (0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define TX_CFG (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TX_CFG_TXSAO_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TX_CFG_TX_ON_ (0x00000002) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define HW_CFG (0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HW_CFG_TTM_ (0x00200000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define HW_CFG_SF_ (0x00100000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define HW_CFG_TR_ (0x00003000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define HW_CFG_SRST_TO_ (0x00000002) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define RX_DP_CTRL (0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define RX_FIFO_INF (0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TX_FIFO_INF (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PMT_CTRL (0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define PMT_CTRL_READY_ (0x00000001) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define GPIO_CFG (0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define GPT_CFG (0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define GPT_CNT (0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define ENDIAN (0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define FREE_RUN (0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define RX_DROP (0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MAC_CSR_CMD (0xA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MAC_CSR_DATA (0xA8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define AFC_CFG (0xAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define AFC_CFG_FCADD_ (0x00000002) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define AFC_CFG_FCANY_ (0x00000001) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define E2P_CMD (0xB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define E2P_DATA (0xB4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* end of LAN register offsets and bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * MAC Control and Status Register (Indirect Address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Offset (through the MAC_CSR CMD and DATA port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MAC_CR (0x01) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* MAC_CR - MAC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MAC_CR_RXALL_ (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) // TODO: delete this bit? It is not described in the data sheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MAC_CR_HBDIS_ (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MAC_CR_RCVOWN_ (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MAC_CR_LOOPBK_ (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MAC_CR_FDPX_ (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MAC_CR_MCPAS_ (0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MAC_CR_PRMS_ (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MAC_CR_INVFILT_ (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MAC_CR_PASSBAD_ (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define MAC_CR_HFILT_ (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MAC_CR_HPFILT_ (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MAC_CR_LCOLL_ (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define MAC_CR_BCAST_ (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MAC_CR_DISRTY_ (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MAC_CR_PADSTR_ (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MAC_CR_BOLMT_MASK_ (0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MAC_CR_DFCHK_ (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define MAC_CR_TXEN_ (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MAC_CR_RXEN_ (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define HASHH (0x04) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define HASHL (0x05) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MII_ACC (0x06) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MII_ACC_PHY_ADDR_ (0x0000F800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MII_ACC_MIIRINDA_ (0x000007C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MII_ACC_MII_WRITE_ (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define MII_ACC_MII_BUSY_ (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define FLOW (0x08) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define FLOW_FCPT_ (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define FLOW_FCPASS_ (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define FLOW_FCEN_ (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define FLOW_FCBSY_ (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define VLAN1_VTI1_ (0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define VLAN2_VTI2_ (0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define WUFF (0x0B) /* WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define WUCSR (0x0C) /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define WUCSR_GUE_ (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define WUCSR_WUFR_ (0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define WUCSR_MPR_ (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define WUCSR_WAKE_EN_ (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define WUCSR_MPEN_ (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Chip Specific MII Defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Phy register offsets and bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) //#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) //#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) //#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) //#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) //#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) //#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) //#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define PHY_INT_SRC ((u32)29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PHY_INT_MASK ((u32)30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PHY_SPECIAL ((u32)31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define PHY_SPECIAL_RES_ ((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define PHY_SPECIAL_SPD_ ((u16)0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define LAN911X_INTERNAL_PHY_ID (0x0007C000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Chip ID values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define CHIP_9115 0x0115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define CHIP_9116 0x0116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define CHIP_9117 0x0117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define CHIP_9118 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define CHIP_9211 0x9211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define CHIP_9215 0x115A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define CHIP_9217 0x117A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define CHIP_9218 0x118A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct chip_id chip_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { CHIP_9115, "LAN9115" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { CHIP_9116, "LAN9116" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { CHIP_9117, "LAN9117" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { CHIP_9118, "LAN9118" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { CHIP_9211, "LAN9211" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { CHIP_9215, "LAN9215" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { CHIP_9217, "LAN9217" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { CHIP_9218, "LAN9218" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define IS_REV_A(x) ((x & 0xFFFF)==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Macros to abstract register access according to the data bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * capabilities. Please use those and not the in/out primitives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* FIFO read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* I/O mapped register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define SMC_SET_FIFO_TDA(lp, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned long __flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int __mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) local_irq_save(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) local_irq_restore(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SMC_SET_FIFO_TSL(lp, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned long __flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int __mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) local_irq_save(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) local_irq_restore(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SMC_SET_FIFO_RSA(lp, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long __flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int __mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) local_irq_save(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) local_irq_restore(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SMC_SET_FIFO_RSL(lp, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned long __flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int __mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) local_irq_save(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) local_irq_restore(__flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* MAC register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define SMC_GET_MAC_CSR(lp,a,v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MAC_CSR_CMD_R_NOT_W_ | (a) ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) v = SMC_GET_MAC_DATA((lp)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SMC_SET_MAC_CSR(lp,a,v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SMC_SET_MAC_DATA((lp), v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* PHY register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SMC_GET_MII(lp,a,phy,v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) SMC_GET_MII_ACC((lp), __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } while ( __v & MII_ACC_MII_BUSY_ ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MII_ACC_MII_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SMC_GET_MII_ACC( (lp), __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } while ( __v & MII_ACC_MII_BUSY_ ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SMC_GET_MII_DATA((lp), v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define SMC_SET_MII(lp,a,phy,v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SMC_GET_MII_ACC((lp), __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } while ( __v & MII_ACC_MII_BUSY_ ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SMC_SET_MII_DATA((lp), v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MII_ACC_MII_BUSY_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MII_ACC_MII_WRITE_ ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SMC_GET_MII_ACC((lp), __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } while ( __v & MII_ACC_MII_BUSY_ ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Misc read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #ifndef SMC_GET_MAC_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define SMC_GET_MAC_ADDR(lp, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned int __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SMC_GET_MAC_CSR((lp), ADDRL, __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) addr[0] = __v; addr[1] = __v >> 8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) addr[2] = __v >> 16; addr[3] = __v >> 24; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SMC_GET_MAC_CSR((lp), ADDRH, __v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) addr[4] = __v; addr[5] = __v >> 8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define SMC_SET_MAC_ADDR(lp, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SMC_SET_MAC_CSR((lp), ADDRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) addr[0] | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) (addr[1] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) (addr[2] << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) (addr[3] << 24)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif /* _SMC911X_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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