Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 1999 Silicon Integrated System Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *   SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	preliminary Rev. 1.0 Jan. 14, 1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	preliminary Rev. 1.0 Nov. 10, 1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	preliminary Rev. 1.0 Jan. 18, 1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *   http://www.sis.com.tw/support/databook.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * SiS 7016 and SiS 900 ethernet controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* The I/O extent, SiS 900 needs 256 bytes of io address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SIS900_TOTAL_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Symbolic offsets to registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum sis900_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	cr=0x0,                 //Command Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	cfg=0x4,                //Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	mear=0x8,               //EEPROM Access Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ptscr=0xc,              //PCI Test Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	isr=0x10,               //Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	imr=0x14,               //Interrupt Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	ier=0x18,               //Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	epar=0x18,              //Enhanced PHY Access Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	txdp=0x20,              //Transmit Descriptor Pointer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)         txcfg=0x24,             //Transmit Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)         rxdp=0x30,              //Receive Descriptor Pointer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)         rxcfg=0x34,             //Receive Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)         flctrl=0x38,            //Flow Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)         rxlen=0x3c,             //Receive Packet Length Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)         rfcr=0x48,              //Receive Filter Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)         rfdr=0x4C,              //Receive Filter Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)         pmctrl=0xB0,            //Power Management Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)         pmer=0xB4               //Power Management Wake-up Event Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Symbolic names for bits in various registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum sis900_command_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	RELOAD  = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	RESET   = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	TxDIS   = 0x00000002, TxENA = 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) enum sis900_configuration_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	SB    = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* 635 & 900B Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	EDB_MASTER_EN = 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) enum sis900_eeprom_access_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MDC  = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	EEDI = 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) enum sis900_interrupt_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	WKEVT  = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	SSERR  = 0x00400000, RMABT  = 0x00200000, RTABT = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MIBINT = 0x00000800, TxURN  = 0x00000400, TxIDLE  = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	TxERR  = 0x00000100, TxDESC = 0x00000080, TxOK  = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	RxORN  = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	RxERR  = 0x00000004, RxDESC = 0x00000002, RxOK  = 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) enum sis900_interrupt_enable_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	IE = 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* maximum dma burst for transmission and receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MAX_DMA_RANGE	7	/* actually 0 means MAXIMUM !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TxMXDMA_shift   	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define RxMXDMA_shift    20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) enum sis900_tx_rx_dma{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DMA_BURST_512 = 0,	DMA_BURST_64 = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* transmit FIFO thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TX_FILL_THRESH   16	/* 1/4 FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TxFILLT_shift   	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TxDRNT_shift    	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TxDRNT_100      	48	/* 3/4 FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TxDRNT_10		16 	/* 1/2 FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) enum sis900_transmit_config_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	TxDRNT = 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* recevie FIFO thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RxDRNT_shift     1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RxDRNT_100	16	/* 1/2 FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RxDRNT_10		24 	/* 3/4 FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum sis900_reveive_config_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	RxAEP  = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	RxAJAB = 0x08000000, RxDRNT = 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RFAA_shift      28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RFADDR_shift    16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum sis900_receive_filter_control_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	RFEN  = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum sis900_reveive_filter_data_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	RFDAT =  0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* EEPROM Addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum sis900_eeprom_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	EEPROMMACAddr   = 0x08, EEPROMChecksum = 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum sis900_eeprom_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	EEread     = 0x0180, EEwrite    = 0x0140, EEerase = 0x01C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	EEeraseAll = 0x0120, EEwriteAll = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	EEaddrMask = 0x013F, EEcmdShift = 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* For SiS962 or SiS963, request the eeprom software access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum sis96x_eeprom_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* PCI Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum sis900_pci_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	CFGPMC 	 = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	CFGPMCSR = 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Power management capabilities bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum sis900_cfgpmc_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PMVER	= 0x00070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	DSI	= 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PMESP	= 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum sis900_pmesp_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PME_D0 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	PME_D1 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PME_D2 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	PME_D3H = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PME_D3C = 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Power management control/status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum sis900_cfgpmcsr_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PMESTS = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PME_EN = 0x00000100, // Power management enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PWR_STA = 0x00000003 // Current power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Wake-on-LAN support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum sis900_power_management_control_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	LINKLOSS  = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	LINKON    = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	MAGICPKT  = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ALGORITHM = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	FRM1EN    = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	FRM2EN    = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	FRM3EN    = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	FRM1ACS   = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	FRM2ACS   = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	FRM3ACS   = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	WAKEALL   = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	GATECLK   = 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Management Data I/O (mdio) frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MIIread         0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MIIwrite        0x5002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MIIpmdShift     7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MIIregShift     2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MIIcmdLen       16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MIIcmdShift     16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Buffer Descriptor Status*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum sis900_buffer_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	OWN    = 0x80000000, MORE   = 0x40000000, INTR = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	SUPCRC = 0x10000000, INCCRC = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	OK     = 0x08000000, DSIZE  = 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Status for TX Buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum sis900_tx_buffer_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ABORT   = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	DEFERD  = 0x00800000, EXCDEFER = 0x00400000, OWCOLL    = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	EXCCOLL = 0x00100000, COLCNT   = 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum sis900_rx_buffer_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	OVERRUN = 0x02000000, DEST = 0x00800000,     BCAST = 0x01800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	MCAST   = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	RUNT    = 0x00200000, RXISERR  = 0x00100000, CRCERR  = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	FAERR   = 0x00040000, LOOPBK   = 0x00020000, RXCOL   = 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* MII register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum mii_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	MII_PHY_ID1 = 0x0003, MII_ANADV  = 0x0004, MII_ANLPAR  = 0x0005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	MII_ANEXT   = 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* mii registers specific to SiS 900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum sis_mii_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	MII_MASK    = 0x0013, MII_RESV    = 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* mii registers specific to ICS 1893 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) enum ics_mii_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	MII_EXTCTRL  = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	MII_EXTCTRL2 = 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* mii registers specific to AMD 79C901 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum amd_mii_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	MII_STATUS_SUMMARY = 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* MII Control register bit definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enum mii_control_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	MII_CNTL_FDX     = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN   = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	MII_CNTL_AUTO    = 0x1000, MII_CNTL_SPEED    = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	MII_CNTL_LPBK    = 0x4000, MII_CNTL_RESET    = 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* MII Status register bit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum mii_status_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	MII_STAT_EXT    = 0x0001, MII_STAT_JAB        = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	MII_STAT_LINK   = 0x0004, MII_STAT_CAN_AUTO   = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	MII_STAT_FAULT  = 0x0010, MII_STAT_AUTO_DONE  = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	MII_STAT_CAN_T  = 0x0800, MII_STAT_CAN_T_FDX  = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	MII_STAT_CAN_T4 = 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define		MII_ID1_OUI_LO		0xFC00	/* low bits of OUI mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define		MII_ID1_MODEL		0x03F0	/* model number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define		MII_ID1_REV		0x000F	/* model number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* MII NWAY Register Bits ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)    valid for the ANAR (Auto-Negotiation Advertisement) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)    ANLPAR (Auto-Negotiation Link Partner) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum mii_nway_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	MII_NWAY_T	  = 0x0020, MII_NWAY_T_FDX   = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	MII_NWAY_TX       = 0x0080, MII_NWAY_TX_FDX  = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	MII_NWAY_T4       = 0x0200, MII_NWAY_PAUSE   = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	MII_NWAY_RF       = 0x2000, MII_NWAY_ACK     = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	MII_NWAY_NP       = 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum mii_stsout_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	MII_STSOUT_LINK_FAIL = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	MII_STSOUT_SPD       = 0x0080, MII_STSOUT_DPLX = 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) enum mii_stsics_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	MII_STSICS_SPD  = 0x8000, MII_STSICS_DPLX = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	MII_STSICS_LINKSTS = 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum mii_stssum_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD  = 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) enum sis900_revision_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	SIS630A_900_REV = 0x80,		SIS630E_900_REV = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	SIS630S_900_REV = 0x82,		SIS630EA1_900_REV = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	SIS630ET_900_REV = 0x84,	SIS635A_900_REV = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	SIS96x_900_REV = 0X91,		SIS900B_900_REV = 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) enum sis630_revision_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	SIS630A0    = 0x00, SIS630A1      = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	SIS630B0    = 0x10, SIS630B1      = 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define FDX_CAPABLE_DUPLEX_UNKNOWN      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define FDX_CAPABLE_HALF_SELECTED       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FDX_CAPABLE_FULL_SELECTED       2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HW_SPEED_UNCONFIG		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HW_SPEED_HOME		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HW_SPEED_10_MBPS        	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HW_SPEED_100_MBPS       	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HW_SPEED_DEFAULT        	(HW_SPEED_100_MBPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CRC_SIZE                4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MAC_HEADER_SIZE         14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #if IS_ENABLED(CONFIG_VLAN_8021Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MAX_FRAME_SIZE  (1518 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MAX_FRAME_SIZE  1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif /* CONFIG_VLAN_802_1Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TX_BUF_SIZE     (MAX_FRAME_SIZE+18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RX_BUF_SIZE     (MAX_FRAME_SIZE+18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define NUM_TX_DESC     16      	/* Number of Tx descriptor registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define NUM_RX_DESC     16       	/* Number of Rx descriptor registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TX_TOTAL_SIZE	NUM_TX_DESC*sizeof(BufferDesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RX_TOTAL_SIZE	NUM_RX_DESC*sizeof(BufferDesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* PCI stuff, should be move to pci.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SIS630_VENDOR_ID        0x1039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SIS630_DEVICE_ID        0x0630