Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* version dependencies have been confined to a separate file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Tunable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #define TX_RING_ENTRIES 64	/* 64-512?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define RX_RING_ENTRIES 16 /* Do not change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /* Internal constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define TX_RING_BUFFER_SIZE	(TX_RING_ENTRIES*sizeof(tx_packet))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define METH_RX_BUFF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define RX_BUCKET_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* For more detailed explanations of what each field menas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    see Nick's great comments to #defines below (or docs, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    you are lucky enough toget hold of them :)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* tx status vector is written over tx command header upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    dma completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) typedef struct tx_status_vector {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u64		sent:1; /* always set to 1...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u64		pad0:34;/* always set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u64		flags:9;			/*I'm too lazy to specify each one separately at the moment*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u64		col_retry_cnt:4;	/*collision retry count*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u64		len:16;				/*Transmit length in bytes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) } tx_status_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Each packet is 128 bytes long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * It consists of header, 0-3 concatination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * buffer pointers and up to 120 data bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) typedef struct tx_packet_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u64		pad1:36; /*should be filled with 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u64		cat_ptr3_valid:1,	/*Concatination pointer valid flags*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			cat_ptr2_valid:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			cat_ptr1_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u64		tx_int_flag:1;		/*Generate TX intrrupt when packet has been sent*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u64		term_dma_flag:1;	/*Terminate transmit DMA on transmit abort conditions*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u64		data_offset:7;		/*Starting byte offset in ring data block*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u64		data_len:16;		/*Length of valid data in bytes-1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) } tx_packet_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) typedef union tx_cat_ptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		u64		pad2:16; /* should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		u64		len:16;				/*length of buffer data - 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		u64		start_addr:29;		/*Physical starting address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		u64		pad1:3; /* should be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	} form;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u64 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) } tx_cat_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) typedef struct tx_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		tx_packet_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		tx_status_vector res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		u64 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		tx_cat_ptr cat_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		char dt[120];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	} data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) } tx_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) typedef union rx_status_vector {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		u64		pad1:1;/*fill it with ones*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		u64		pad2:15;/*fill with 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		u64		ip_chk_sum:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		u64		seq_num:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		u64		mac_addr_match:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		u64		mcast_addr_match:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		u64		carrier_event_seen:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		u64		bad_packet:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		u64		long_event_seen:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		u64		invalid_preamble:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		u64		broadcast:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		u64		multicast:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		u64		crc_error:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		u64		huh:1;/*???*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		u64		rx_code_violation:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		u64		rx_len:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	} parsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	volatile u64 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) } rx_status_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) typedef struct rx_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	rx_status_vector status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)         u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)         u16 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) } rx_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TX_INFO_RPTR    0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TX_INFO_WPTR    0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Bits in METH_MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SGI_MAC_RESET		BIT(0)	/* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define METH_PHY_FDX		BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define METH_PHY_LOOP	BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				       /*    selects ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define METH_100MBIT		BIT(3) /* 0: 10meg mode, 1: 100meg mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define METH_PHY_MII		BIT(4) /* 0: MII selected, 1: SIA selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				       /*   Note: when loopback is set this bit becomes collision control.  Setting this bit will */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				       /*         cause a collision to be reported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				       /* Bits 5 and 6 are used to determine the Destination address filter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define METH_ACCEPT_MY 0			/* 00: Accept PHY address only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define METH_ACCEPT_MCAST 0x20	/* 01: Accept physical, broadcast, and multicast filter matches only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define METH_ACCEPT_AMCAST 0x40	/* 10: Accept physical, broadcast, and all multicast packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define METH_PROMISC 0x60		/* 11: Promiscious mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define METH_PHY_LINK_FAIL	BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define METH_MAC_IPG	0x1ffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 						/* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				       /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				       /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				       /* per increment for 10BaseT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				       /* Bits 15 through 21 are used to determine IPGR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				       /* Bits 22 through 28 are used to determine IPGR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define METH_REV_SHIFT 29       /* Bits 29 through 31 are used to determine the revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				       /* 000: Initial revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				       /* 001: First revision, Improved TX concatenation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* DMA control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define METH_DMA_RX_EN BIT(15) /* Enable RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* RX FIFO MCL Info bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define METH_RX_FIFO_WPTR(x)   (((x)>>16)&0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define METH_RX_FIFO_RPTR(x)   (((x)>>8)&0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define METH_RX_FIFO_DEPTH(x)  ((x)&0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* RX status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define METH_RX_ST_VALID BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define METH_RX_ST_DRBL_NBL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define METH_RX_ST_CRC_ERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define METH_RX_ST_MCAST_PKT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define METH_RX_ST_BCAST_PKT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define METH_RX_ST_BAD_PACKET BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define METH_RX_STATUS_ERRORS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	METH_RX_ST_RCV_CODE_VIOLATION| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	METH_RX_ST_CRC_ERR| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	METH_RX_ST_INV_PREAMBLE_CTX| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	METH_RX_ST_LONG_EVT_SEEN| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	METH_RX_ST_BAD_PACKET| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	METH_RX_ST_CARRIER_EVT_SEEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Bits in METH_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Write _1_ to corresponding bit to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define METH_INT_TX_EMPTY	BIT(0)	/* 0: No interrupt pending, 1: The TX ring buffer is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define METH_INT_TX_PKT		BIT(1)	/* 0: No interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					      	/* 1: A TX message had the INT request bit set, the packet has been sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define METH_INT_TX_LINK_FAIL	BIT(2)	/* 0: No interrupt pending, 1: PHY has reported a link failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define METH_INT_MEM_ERROR	BIT(3)	/* 0: No interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 						/* 1: A memory error occurred during DMA, DMA stopped, Fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define METH_INT_TX_ABORT		BIT(4)	/* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define METH_INT_RX_THRESHOLD	BIT(5)	/* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define METH_INT_RX_UNDERFLOW	BIT(6)	/* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define METH_INT_RX_OVERFLOW		BIT(7)	/* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/		/* Bits 8 through 12 alias of RX read-pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define METH_INT_RX_RPTR_MASK 0x0000F00		/* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 						/* Bits 13 through 15 are always 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define METH_INT_TX_RPTR_MASK	0x1FF0000        /* Bits 16 through 24 alias of TX read-pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define METH_INT_RX_SEQ_MASK	0x2E000000	/* Bits 25 through 29 are the starting seq number for the message at the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 						/* top of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define METH_INT_ERROR	(METH_INT_TX_LINK_FAIL| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			METH_INT_MEM_ERROR| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			METH_INT_TX_ABORT| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			METH_INT_RX_OVERFLOW| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			METH_INT_RX_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define METH_INT_MCAST_HASH		BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* TX status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define METH_TX_ST_DONE      BIT(63) /* TX complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define METH_TX_ST_SUCCESS   BIT(23) /* Packet was transmitted successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define METH_TX_ST_TOOLONG   BIT(24) /* TX abort due to excessive length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define METH_TX_ST_UNDERRUN  BIT(25) /* TX abort due to underrun (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define METH_TX_ST_EXCCOLL   BIT(26) /* TX abort due to excess collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define METH_TX_ST_DEFER     BIT(27) /* TX abort due to excess deferals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define METH_TX_ST_LATECOLL  BIT(28) /* TX abort due to late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Tx command header bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Phy MDIO interface busy flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MDIO_BUSY    BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MDIO_DATA_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* PHY defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PHY_QS6612X    0x0181441    /* Quality TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PHY_ICS1889    0x0015F41    /* ICS FX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PHY_ICS1890    0x0015F42    /* ICS TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PHY_DP83840    0x20005C0    /* National TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ADVANCE_RX_PTR(x)  x=(x+1)&(RX_RING_ENTRIES-1)