^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * meth.c -- O2 Builtin 10/100 Ethernet driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001-2003 Ilya Volynets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/in6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h> /* struct device, et al */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/netdevice.h> /* struct device, and other headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/etherdevice.h> /* eth_type_trans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ip.h> /* struct iphdr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tcp.h> /* struct tcphdr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mii.h> /* MII definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/ip32/mace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/ip32/ip32_ints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "meth.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef MFE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MFE_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #if MFE_DEBUG>=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MFE_RX_DEBUG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DPRINTK(str,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MFE_RX_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char *meth_str="SGI O2 Fast Ethernet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TX_TIMEOUT (400*HZ/1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int timeout = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define METH_MCF_LIMIT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * This structure is private to each device. It is used to pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * packets in and out, so there is place for a packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct meth_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* in-memory copy of MAC Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u64 mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* in-memory copy of DMA Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tx_packet *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sk_buff *tx_skbs[TX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long tx_read, tx_write, tx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rx_packet *rx_ring[RX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sk_buff *rx_skbs[RX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long rx_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Multicast filter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u64 mcast_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spinlock_t meth_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static irqreturn_t meth_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* global, initialized in ip32-setup.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void load_eaddr(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u64 macaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) macaddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mace->eth.mac_addr = macaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Waits for BUSY status of mdio bus to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WAIT_FOR_PHY(___rval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) udelay(25); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*read phy register, return value read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) WAIT_FOR_PHY(rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mace->eth.phy_trans_go = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) udelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WAIT_FOR_PHY(rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return rval & MDIO_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int mdio_probe(struct meth_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long p2, p3, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* check if phy is detected already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if(priv->phy_addr>=0&&priv->phy_addr<32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i=0;i<32;++i){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) priv->phy_addr=i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) p2=mdio_read(priv,2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) p3=mdio_read(priv,3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #if MFE_DEBUG>=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch ((p2<<12)|(p3>>4)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case PHY_QS6612X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DPRINTK("PHY is QS6612X\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case PHY_ICS1889:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DPRINTK("PHY is ICS1889\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case PHY_ICS1890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DPRINTK("PHY is ICS1890\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case PHY_DP83840:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DPRINTK("PHY is DP83840\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if(p2!=0xffff&&p2!=0x0000){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if(priv->phy_addr<32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DPRINTK("Oopsie! PHY is not known!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) priv->phy_addr=-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void meth_check_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long mii_advertising = mdio_read(priv, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long mii_partner = mdio_read(priv, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long negotiated = mii_advertising & mii_partner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long duplex, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (mii_partner == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) METH_PHY_FDX : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) priv->mac_ctrl |= METH_PHY_FDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) priv->mac_ctrl &= ~METH_PHY_FDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mace->eth.mac_ctrl = priv->mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) priv->mac_ctrl |= METH_100MBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) priv->mac_ctrl &= ~METH_100MBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mace->eth.mac_ctrl = priv->mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int meth_init_tx_ring(struct meth_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Init TX ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->tx_ring = dma_alloc_coherent(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TX_RING_BUFFER_SIZE, &priv->tx_ring_dma, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!priv->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) priv->tx_count = priv->tx_read = priv->tx_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mace->eth.tx_ring_base = priv->tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Now init skb save area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int meth_init_rx_ring(struct meth_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < RX_RING_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 8byte status vector + 3quad padding + 2byte padding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * to put data on 64bit aligned boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* I'll need to re-sync it after each RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) priv->rx_ring_dmas[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dma_map_single(&priv->pdev->dev, priv->rx_ring[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mace->eth.rx_fifo = priv->rx_ring_dmas[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->rx_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void meth_free_tx_ring(struct meth_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Remove any pending skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < TX_RING_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_kfree_skb(priv->tx_skbs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) priv->tx_skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_free_coherent(&priv->pdev->dev, TX_RING_BUFFER_SIZE, priv->tx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) priv->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void meth_free_rx_ring(struct meth_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < RX_RING_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dma_unmap_single(&priv->pdev->dev, priv->rx_ring_dmas[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) priv->rx_ring[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) priv->rx_ring_dmas[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kfree_skb(priv->rx_skbs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int meth_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Reset card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mace->eth.mac_ctrl = SGI_MAC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mace->eth.mac_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) udelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Load ethernet address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) load_eaddr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Should load some "errata", but later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Check for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mdio_probe(priv) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DPRINTK("Unable to find PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Initial mode: 10 | Half-duplex | Accept normal packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) priv->mac_ctrl |= METH_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mace->eth.mac_ctrl = priv->mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Autonegotiate speed and duplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) meth_check_link(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Now set dma control, but don't enable DMA, yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*============End Helper Routines=====================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Open and close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int meth_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) priv->phy_addr = -1; /* No PHY is known yet... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = meth_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Allocate the ring buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = meth_init_tx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = meth_init_rx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto out_free_tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto out_free_rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DPRINTK("About to start queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) out_free_rx_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) meth_free_rx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) out_free_tx_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) meth_free_tx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int meth_release(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DPRINTK("Stopping queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) netif_stop_queue(dev); /* can't transmit any more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* shut down DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) meth_free_tx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) meth_free_rx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Receive a packet: retrieve, encapsulate and pass over to upper levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void meth_rx(struct net_device* dev, unsigned long int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned long status, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (int_status & METH_INT_RX_UNDERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) fifo_rptr = (fifo_rptr - 1) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) while (priv->rx_write != fifo_rptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dma_unmap_single(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) priv->rx_ring_dmas[priv->rx_write],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) status = priv->rx_ring[priv->rx_write]->status.raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #if MFE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!(status & METH_RX_ST_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DPRINTK("Not received? status=%016lx\n",status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int len = (status & 0xffff) - 4; /* omit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* length sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (len < 60 || len > 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev->name, priv->rx_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv->rx_ring[priv->rx_write]->status.raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) skb = priv->rx_skbs[priv->rx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Ouch! No memory! Drop packet on the floor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DPRINTK("No mem: dropping packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) skb = priv->rx_skbs[priv->rx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* 8byte status vector + 3quad padding + 2byte padding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * to put data on 64bit aligned boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) skb_reserve(skb, METH_RX_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Write metadata, and then pass to the receive level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) skb_put(skb_c, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) priv->rx_skbs[priv->rx_write] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) skb_c->protocol = eth_type_trans(skb_c, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) netif_rx(skb_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) skb=priv->rx_skbs[priv->rx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #if MFE_DEBUG>0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if(status&METH_RX_ST_RCV_CODE_VIOLATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) printk(KERN_WARNING "Receive Code Violation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if(status&METH_RX_ST_CRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) printk(KERN_WARNING "CRC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if(status&METH_RX_ST_INV_PREAMBLE_CTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) printk(KERN_WARNING "Invalid Preamble Context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if(status&METH_RX_ST_LONG_EVT_SEEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) printk(KERN_WARNING "Long Event Seen...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if(status&METH_RX_ST_BAD_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_WARNING "Bad Packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if(status&METH_RX_ST_CARRIER_EVT_SEEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_WARNING "Carrier Event Seen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) priv->rx_ring[priv->rx_write]->status.raw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) priv->rx_ring_dmas[priv->rx_write] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma_map_single(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) priv->rx_ring[priv->rx_write],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ADVANCE_RX_PTR(priv->rx_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* In case there was underflow, and Rx DMA was disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mace->eth.int_stat = METH_INT_RX_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int meth_tx_full(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return priv->tx_count >= TX_RING_ENTRIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned long status, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Stop DMA notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) while (priv->tx_read != rptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) skb = priv->tx_skbs[priv->tx_read];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) status = priv->tx_ring[priv->tx_read].header.raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #if MFE_DEBUG>=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (priv->tx_read == priv->tx_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (status & METH_TX_ST_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (status & METH_TX_ST_SUCCESS){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #if MFE_DEBUG>=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DPRINTK("TX error: status=%016lx <",status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if(status & METH_TX_ST_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) printk(" SUCCESS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if(status & METH_TX_ST_TOOLONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) printk(" TOOLONG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if(status & METH_TX_ST_UNDERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) printk(" UNDERRUN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if(status & METH_TX_ST_EXCCOLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) printk(" EXCCOLL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if(status & METH_TX_ST_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) printk(" DEFER");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if(status & METH_TX_ST_LATECOLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) printk(" LATECOLL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) printk(" >\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DPRINTK("RPTR points us here, but packet not done?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) priv->tx_skbs[priv->tx_read] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) priv->tx_ring[priv->tx_read].header.raw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) priv->tx_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* wake up queue if it was stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void meth_error(struct net_device* dev, unsigned status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* check for errors too... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (status & (METH_INT_TX_LINK_FAIL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) printk(KERN_WARNING "meth: link failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Should I do full reset in this case? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (status & (METH_INT_MEM_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) printk(KERN_WARNING "meth: memory error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (status & (METH_INT_TX_ABORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) printk(KERN_WARNING "meth: aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (status & (METH_INT_RX_OVERFLOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) printk(KERN_WARNING "meth: Rx overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (status & (METH_INT_RX_UNDERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) printk(KERN_WARNING "meth: Rx underflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* more underflow interrupts will be delivered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * effectively throwing us into an infinite loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Thus I stop processing Rx in this case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) priv->dma_ctrl &= ~METH_DMA_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DPRINTK("Disabled meth Rx DMA temporarily\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mace->eth.int_stat = METH_INT_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * The typical interrupt entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static irqreturn_t meth_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct net_device *dev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) status = mace->eth.int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) while (status & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* First handle errors - if we get Rx underflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Rx DMA will be disabled, and Rx handler will reenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * it. I don't think it's possible to get Rx underflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * without getting Rx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (status & METH_INT_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) meth_error(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* a transmission is over: free the skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) meth_tx_cleanup(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (status & METH_INT_RX_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* send it to meth_rx for handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) meth_rx(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) status = mace->eth.int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Transmits packets that fit into TX descriptor (are <=120B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void meth_tx_short_prepare(struct meth_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tx_packet *desc = &priv->tx_ring[priv->tx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* maybe I should set whole thing to 0 first... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (skb->len < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define TX_CATBUF1 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void meth_tx_1page_prepare(struct meth_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tx_packet *desc = &priv->tx_ring[priv->tx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int buffer_len = skb->len - unaligned_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dma_addr_t catbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* unaligned part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (unaligned_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unaligned_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) desc->header.raw |= (128 - unaligned_len) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* first page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) catbuf = dma_map_single(&priv->pdev->dev, buffer_data, buffer_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) desc->data.cat_buf[0].form.len = buffer_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define TX_CATBUF2 BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void meth_tx_2page_prepare(struct meth_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) tx_packet *desc = &priv->tx_ring[priv->tx_write];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int buffer2_len = skb->len - buffer1_len - unaligned_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dma_addr_t catbuf1, catbuf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* unaligned part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (unaligned_len){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unaligned_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) desc->header.raw |= (128 - unaligned_len) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* first page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) catbuf1 = dma_map_single(&priv->pdev->dev, buffer1_data, buffer1_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) desc->data.cat_buf[0].form.len = buffer1_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* second page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) catbuf2 = dma_map_single(&priv->pdev->dev, buffer2_data, buffer2_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) desc->data.cat_buf[1].form.len = buffer2_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Remember the skb, so we can free it at interrupt time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) priv->tx_skbs[priv->tx_write] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (skb->len <= 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Whole packet fits into descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) meth_tx_short_prepare(priv, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else if (PAGE_ALIGN((unsigned long)skb->data) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Packet crosses page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) meth_tx_2page_prepare(priv, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Packet is in one page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) meth_tx_1page_prepare(priv, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mace->eth.tx_info = priv->tx_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) priv->tx_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Transmit a packet (called by the kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static netdev_tx_t meth_tx(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Stop DMA notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) meth_add_to_tx_ring(priv, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) netif_trans_update(dev); /* save the timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* If TX ring is full, tell the upper layer to stop sending packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (meth_tx_full(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) printk(KERN_DEBUG "TX full: stopping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Restart DMA notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) priv->dma_ctrl |= METH_DMA_TX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * Deal with a transmit timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Protect against concurrent rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) spin_lock_irqsave(&priv->meth_lock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Try to reset the interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) meth_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Clear all rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) meth_free_tx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) meth_free_rx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) meth_init_tx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) meth_init_rx_ring(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Restart dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mace->eth.dma_ctrl = priv->dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Ioctl commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* XXX Not yet implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch(cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case SIOCGMIIPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case SIOCGMIIREG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case SIOCSMIIREG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void meth_set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct meth_private *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spin_lock_irqsave(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) priv->mac_ctrl &= ~METH_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) priv->mac_ctrl |= METH_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) priv->mcast_filter = 0xffffffffffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) (dev->flags & IFF_ALLMULTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) priv->mac_ctrl |= METH_ACCEPT_AMCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) priv->mcast_filter = 0xffffffffffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) priv->mac_ctrl |= METH_ACCEPT_MCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) netdev_for_each_mc_addr(ha, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (volatile unsigned long *)&priv->mcast_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Write the changes to the chip registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mace->eth.mac_ctrl = priv->mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mace->eth.mcast_filter = priv->mcast_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Done! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) spin_unlock_irqrestore(&priv->meth_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct net_device_ops meth_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .ndo_open = meth_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .ndo_stop = meth_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .ndo_start_xmit = meth_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .ndo_do_ioctl = meth_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .ndo_tx_timeout = meth_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ndo_set_rx_mode = meth_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * The init function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int meth_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct meth_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev = alloc_etherdev(sizeof(struct meth_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev->netdev_ops = &meth_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev->watchdog_timeo = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev->irq = MACE_ETHERNET_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev->base_addr = (unsigned long)&mace->eth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) memcpy(dev->dev_addr, o2meth_eaddr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spin_lock_init(&priv->meth_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int meth_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct platform_driver meth_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .probe = meth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .remove = meth_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .name = "meth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) module_platform_driver(meth_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MODULE_ALIAS("platform:meth");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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