^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * o IOC3 ASIC specification 4.51, 1996-04-18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * o IEEE 802.3 specification, 2000 edition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * o DP38840A Specification, National Semiconductor, March 1997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * To do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * o Use prefetching for large packets. What is a good lower limit for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * prefetching?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * o Use hardware checksums.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * o Which PHYs might possibly be attached to the IOC3 in real live,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * which workarounds are required for them? Do we ever have Lucent's?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * o For the 2.5 branch kill the mii-tool ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IOC3_NAME "ioc3-eth"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IOC3_VERSION "2.6.3-4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/crc16.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/tcp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/udp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <net/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/sn/ioc3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/pci/bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CRC16_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CRC16_VALID 0xb001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Number of RX buffers. This is tunable in the range of 16 <= x < 512.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The value must be a power of two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RX_BUFFS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RX_RING_ENTRIES 512 /* fixed in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RX_RING_MASK (RX_RING_ENTRIES - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* 128 TX buffers (not tunable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TX_RING_ENTRIES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TX_RING_MASK (TX_RING_ENTRIES - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* IOC3 does dma transfers in 128 byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IOC3_DMA_XFER_LEN 128UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Every RX buffer starts with 8 byte descriptor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Private per NIC data of the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ioc3_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ioc3_ethregs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 *ssram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long *rxr; /* pointer to receiver ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ioc3_etxd *txr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dma_addr_t rxr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_addr_t txr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sk_buff *rx_skbs[RX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sk_buff *tx_skbs[TX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int rx_ci; /* RX consumer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int rx_pi; /* RX producer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int tx_ci; /* TX consumer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int tx_pi; /* TX producer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int txqlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 emcr, ehar_h, ehar_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spinlock_t ioc3_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct mii_if_info mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Members used by autonegotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct timer_list ioc3_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void ioc3_set_multicast_list(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void ioc3_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline unsigned int ioc3_hash(const unsigned char *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void ioc3_start(struct ioc3_private *ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void ioc3_stop(struct ioc3_private *ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void ioc3_init(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ioc3_alloc_rx_bufs(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void ioc3_free_rx_bufs(struct ioc3_private *ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void ioc3_clean_tx_ring(struct ioc3_private *ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct ethtool_ops ioc3_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sk_buff *new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dma_addr_t d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!new_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offset = aligned_rx_skb_addr((unsigned long)new_skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) skb_reserve(new_skb, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) d = dma_map_single(ip->dma_dev, new_skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RX_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (dma_mapping_error(ip->dma_dev, d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_kfree_skb_any(new_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *rxb_dma = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *rxb = (struct ioc3_erxbuf *)new_skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) skb_reserve(new_skb, RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *skb = new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_PCI_XTALK_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return (addr & ~PCI64_ATTR_BAR) | attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ERBAR_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ioc3eth_nvmem_match(struct device *dev, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const char *prefix = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int prefix_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) prefix_len = strlen(prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (strlen(name) < (prefix_len + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (memcmp(prefix, name, prefix_len) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* found nvmem device which is attached to our ioc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * now check for one wire family code 09, 89 and 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (memcmp(name + prefix_len, "09-", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (memcmp(name + prefix_len, "89-", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (memcmp(name + prefix_len, "91-", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) char prefix[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 prom[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) snprintf(prefix, sizeof(prefix), "ioc3-%012llx-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) res->start & ~0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(nvmem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = nvmem_device_read(nvmem, 0, 16, prom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) nvmem_device_put(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* check, if content is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (prom[0] != 0x0a ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) crc16(CRC16_INIT, prom, 13) != CRC16_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mac_addr[i] = prom[10 - i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void __ioc3_set_mac_address(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel((dev->dev_addr[5] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev->dev_addr[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) &ip->regs->emar_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel((dev->dev_addr[3] << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (dev->dev_addr[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (dev->dev_addr[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev->dev_addr[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &ip->regs->emar_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int ioc3_set_mac_address(struct net_device *dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct sockaddr *sa = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __ioc3_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Caller must hold the ioc3_lock ever for MII readers. This is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * used to protect the transmitter side but it's low contention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) while (readl(®s->micr) & MICR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ®s->micr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) while (readl(®s->micr) & MICR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return readl(®s->midr_r) & MIDR_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) while (readl(®s->micr) & MICR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel(data, ®s->midr_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while (readl(®s->micr) & MICR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int ioc3_mii_init(struct ioc3_private *ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ethhdr *eh = eth_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned char *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct iphdr *ih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 csum, ehsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 *ew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Did hardware handle the checksum at all? The cases we can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * - TCP and UDP checksums of IPv4 only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * - IPv6 would be doable but we keep that for later ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * - Only unfragmented packets. Did somebody already tell you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * fragmentation is evil?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * - don't care about packet size. Worst case when processing a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * malformed packet we'll try to access the packet at ip header +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * 64 bytes which is still inside the skb. Even in the unlikely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * case where the checksum is right the higher layers will still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * drop the packet as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (eh->h_proto != htons(ETH_P_IP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ih = (struct iphdr *)((char *)eh + ETH_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ip_is_fragment(ih))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) proto = ih->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Same as tx - compute csum of pseudo header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) csum = hwsum +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (ih->tot_len - (ih->ihl << 2)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) htons((u16)ih->protocol) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (ih->saddr >> 16) + (ih->saddr & 0xffff) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (ih->daddr >> 16) + (ih->daddr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Sum up ethernet dest addr, src addr and protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ew = (u16 *)eh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ehsum = (ehsum & 0xffff) + (ehsum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ehsum = (ehsum & 0xffff) + (ehsum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) csum += 0xffff ^ ehsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* In the next step we also subtract the 1's complement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * checksum of the trailing ethernet CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cp = (char *)eh + len; /* points at trailing CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (len & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) csum = (csum & 0xffff) + (csum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) csum = (csum & 0xffff) + (csum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (csum == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static inline void ioc3_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct sk_buff *skb, *new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int rx_entry, n_entry, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct ioc3_erxbuf *rxb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned long *rxr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma_addr_t d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 w0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rxr = ip->rxr; /* Ring base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rx_entry = ip->rx_ci; /* RX consume index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) n_entry = ip->rx_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) skb = ip->rx_skbs[rx_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) w0 = be32_to_cpu(rxb->w0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) while (w0 & ERXBUF_V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) err = be32_to_cpu(rxb->err); /* It's valid ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (err & ERXBUF_GOODPKT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Ouch, drop packet and just recycle packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * to keep the ring filled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) new_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) d = rxr[rx_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (likely(dev->features & NETIF_F_RXCSUM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ioc3_tcpudp_checksum(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) w0 & ERXBUF_IPCKSUM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dma_unmap_single(ip->dma_dev, rxr[rx_entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RX_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ip->rx_skbs[rx_entry] = NULL; /* Poison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev->stats.rx_packets++; /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* The frame is invalid and the skb never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * reached the network layer so we can just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * recycle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) new_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) d = rxr[rx_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (err & ERXBUF_CRCERR) /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (err & ERXBUF_FRAMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ip->rx_skbs[n_entry] = new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rxb->w0 = 0; /* Clear valid flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Now go on to the next ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rx_entry = (rx_entry + 1) & RX_RING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) skb = ip->rx_skbs[rx_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) w0 = be32_to_cpu(rxb->w0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ip->rx_pi = n_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ip->rx_ci = rx_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void ioc3_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long packets, bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int tx_entry, o_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 etcir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spin_lock(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) etcir = readl(®s->etcir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tx_entry = (etcir >> 7) & TX_RING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) o_entry = ip->tx_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) packets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) while (o_entry != tx_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) skb = ip->tx_skbs[o_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ip->tx_skbs[o_entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) etcir = readl(®s->etcir); /* More pkts sent? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tx_entry = (etcir >> 7) & TX_RING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->stats.tx_packets += packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->stats.tx_bytes += bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ip->txqlen -= packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ip->tx_ci = o_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_unlock(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Deal with fatal IOC3 errors. This condition might be caused by a hard or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * software problems, so we should try to recover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * more gracefully if this ever happens. In theory we might be flooded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * with such error interrupts if something really goes wrong, so we might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * also consider to take the interface down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void ioc3_error(struct net_device *dev, u32 eisr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_lock(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (eisr & EISR_RXOFLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) net_err_ratelimited("%s: RX overflow.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (eisr & EISR_RXBUFOFLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (eisr & EISR_RXMEMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) net_err_ratelimited("%s: RX PCI error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (eisr & EISR_RXPARERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (eisr & EISR_TXBUFUFLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (eisr & EISR_TXMEMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) net_err_ratelimited("%s: TX PCI error.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ioc3_stop(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ioc3_free_rx_bufs(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ioc3_clean_tx_ring(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ioc3_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ioc3_alloc_rx_bufs(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_unlock(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ioc3_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ioc3_mii_init(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_unlock(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* The interrupt handler does all of the Rx thread work and cleans up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * after the Tx thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static irqreturn_t ioc3_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ioc3_private *ip = netdev_priv(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 eisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) eisr = readl(®s->eisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) writel(eisr, ®s->eisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) readl(®s->eisr); /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ioc3_error(dev_id, eisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (eisr & EISR_RXTIMERINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ioc3_rx(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (eisr & EISR_TXEXPLICIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ioc3_tx(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static inline void ioc3_setup_duplex(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ip->mii.full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(ETCSR_FD, ®s->etcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ip->emcr |= EMCR_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writel(ETCSR_HD, ®s->etcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ip->emcr &= ~EMCR_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel(ip->emcr, ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void ioc3_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ioc3_private *ip = from_timer(ip, t, ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Print the link status if it has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mii_check_media(&ip->mii, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ioc3_setup_duplex(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) add_timer(&ip->ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Try to find a PHY. There is no apparent relation between the MII addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * in the SGI documentation and what we find in reality, so we simply probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * for the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int ioc3_mii_init(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) word = ioc3_mdio_read(ip->mii.dev, i, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (word != 0xffff && word != 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ip->mii.phy_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ip->mii.phy_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void ioc3_mii_start(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) add_timer(&ip->ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct ioc3_etxd *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 cmd, bufcnt, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) desc = &ip->txr[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) cmd = be32_to_cpu(desc->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) bufcnt = be32_to_cpu(desc->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (cmd & ETXD_B1V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (cmd & ETXD_B2V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) for (i = 0; i < TX_RING_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) skb = ip->tx_skbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ioc3_tx_unmap(ip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ip->tx_skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ip->txr[i].cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ip->tx_pi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ip->tx_ci = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void ioc3_free_rx_bufs(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int rx_entry, n_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) n_entry = ip->rx_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rx_entry = ip->rx_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) while (n_entry != rx_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) skb = ip->rx_skbs[n_entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dma_unmap_single(ip->dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) be64_to_cpu(ip->rxr[n_entry]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RX_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) n_entry = (n_entry + 1) & RX_RING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int ioc3_alloc_rx_bufs(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct ioc3_erxbuf *rxb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dma_addr_t d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Now the rx buffers. The RX ring may be larger but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * we only allocate 16 buffers for now. Need to tune
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * this for performance and memory later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for (i = 0; i < RX_BUFFS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) rxb->w0 = 0; /* Clear valid flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ip->rx_ci = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ip->rx_pi = RX_BUFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static inline void ioc3_ssram_disc(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 *ssram0 = &ip->ssram[0x0000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 *ssram1 = &ip->ssram[0x4000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 pattern = 0x5555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Assume the larger size SSRAM and enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) readl(®s->emcr); /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) writel(pattern, ssram0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel(~pattern & IOC3_SSRAM_DM, ssram1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* set ssram size to 64 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ip->emcr |= EMCR_RAMPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void ioc3_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) del_timer_sync(&ip->ioc3_timer); /* Kill if running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writel(EMCR_RST, ®s->emcr); /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) readl(®s->emcr); /* Flush WB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) udelay(4); /* Give it time ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel(0, ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) readl(®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Misc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) writel(ERBAR_VAL, ®s->erbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) readl(®s->etcdc); /* Clear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) writel(15, ®s->ercsr); /* RX low watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel(0, ®s->ertr); /* Interrupt immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __ioc3_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(ip->ehar_h, ®s->ehar_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) writel(ip->ehar_l, ®s->ehar_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writel(42, ®s->ersr); /* XXX should be random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void ioc3_start(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned long ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Now the rx ring base, consume & produce registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writel(ring >> 32, ®s->erbr_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel(ring & 0xffffffff, ®s->erbr_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writel(ip->rx_ci << 3, ®s->ercir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ip->txqlen = 0; /* nothing queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Now the tx ring base, consume & produce registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) writel(ring >> 32, ®s->etbr_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) writel(ring & 0xffffffff, ®s->etbr_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) writel(ip->tx_pi << 7, ®s->etpir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) writel(ip->tx_ci << 7, ®s->etcir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) readl(®s->etcir); /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) writel(ip->emcr, ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) readl(®s->eier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static inline void ioc3_stop(struct ioc3_private *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) writel(0, ®s->emcr); /* Shutup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) writel(0, ®s->eier); /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) readl(®s->eier); /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int ioc3_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ip->ehar_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ip->ehar_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ioc3_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ioc3_alloc_rx_bufs(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ioc3_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ioc3_mii_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int ioc3_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) del_timer_sync(&ip->ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ioc3_stop(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ioc3_free_rx_bufs(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ioc3_clean_tx_ring(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct net_device_ops ioc3_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .ndo_open = ioc3_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ndo_stop = ioc3_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ndo_start_xmit = ioc3_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .ndo_tx_timeout = ioc3_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ndo_get_stats = ioc3_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .ndo_set_rx_mode = ioc3_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .ndo_do_ioctl = ioc3_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .ndo_set_mac_address = ioc3_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int ioc3eth_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 sw_physid1, sw_physid2, vendor, model, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct ioc3_private *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&pdev->dev, "Invalid resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* get mac addr from one wire prom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ioc3eth_get_mac_addr(regs, mac_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EPROBE_DEFER; /* not available yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev = alloc_etherdev(sizeof(struct ioc3_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ip->dma_dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ip->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ERR(ip->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) err = PTR_ERR(ip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ip->ssram = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (IS_ERR(ip->ssram)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) err = PTR_ERR(ip->ssram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (dev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) err = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) IRQF_SHARED, "ioc3-eth", dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(&pdev->dev, "Can't get irq %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) spin_lock_init(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ioc3_stop(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!ip->rxr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pr_err("ioc3-eth: rx ring allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) goto out_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ip->tx_ring = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &ip->txr_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!ip->tx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pr_err("ioc3-eth: tx ring allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto out_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Align TX ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ip->txr = PTR_ALIGN(ip->tx_ring, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ip->txr_dma = ALIGN(ip->txr_dma, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ioc3_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ip->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ip->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ip->mii.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ip->mii.mdio_read = ioc3_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ip->mii.mdio_write = ioc3_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ioc3_mii_init(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ip->mii.phy_id == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) netdev_err(dev, "Didn't find a PHY, goodbye.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) goto out_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ioc3_mii_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ioc3_ssram_disc(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* The IOC3-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev->watchdog_timeo = 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev->netdev_ops = &ioc3_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev->ethtool_ops = &ioc3_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev->features = NETIF_F_IP_CSUM | NETIF_F_HIGHDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) goto out_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mii_check_media(&ip->mii, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ioc3_setup_duplex(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) model = (sw_physid2 >> 4) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rev = sw_physid2 & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ip->mii.phy_id, vendor, model, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ip->emcr & EMCR_BUFSIZ ? 128 : 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) out_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) del_timer_sync(&ip->ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ip->rxr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ip->rxr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ip->tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dma_free_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, ip->tx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ip->txr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int ioc3eth_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dma_free_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, ip->tx_ring, ip->txr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) del_timer_sync(&ip->ioc3_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct ioc3_etxd *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int produce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 w0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* IOC3 has a fairly simple minded checksumming hardware which simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * adds up the 1's complement checksum for the entire packet and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * inserts it at an offset which can be specified in the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * into the transmit packet. This means we have to compensate for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * MAC header which should not be summed and the TCP/UDP pseudo headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) const struct iphdr *ih = ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) const int proto = ntohs(ih->protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int csoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 csum, ehsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u16 *eh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* The MAC header. skb->mac seem the logic approach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * to find the MAC header - except it's a NULL pointer ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) eh = (u16 *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Sum up dest addr, src addr and protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Skip IP header; it's sum is always zero and was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * already filled in by ip_output.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ih->tot_len - (ih->ihl << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) proto, csum_fold(ehsum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) csum = (csum & 0xffff) + (csum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) csoff = ETH_HLEN + (ih->ihl << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (proto == IPPROTO_UDP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) csoff += offsetof(struct udphdr, check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) udp_hdr(skb)->check = csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (proto == IPPROTO_TCP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) csoff += offsetof(struct tcphdr, check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) tcp_hdr(skb)->check = csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) data = (unsigned long)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) produce = ip->tx_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) desc = &ip->txr[produce];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (len <= 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Short packet, let's copy it directly into the ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) skb_copy_from_linear_data(skb, desc->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (len < ETH_ZLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Very short packet, pad with zeros at the end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) memset(desc->data + len, 0, ETH_ZLEN - len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) len = ETH_ZLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) desc->bufcnt = cpu_to_be32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else if ((data ^ (data + len - 1)) & 0x4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned long b2 = (data | 0x3fffUL) + 1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) unsigned long s1 = b2 - data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) unsigned long s2 = data + len - b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dma_addr_t d1, d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ETXD_B1V | ETXD_B2V | w0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) (s2 << ETXD_B2CNT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (dma_mapping_error(ip->dma_dev, d1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) goto drop_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (dma_mapping_error(ip->dma_dev, d2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto drop_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dma_addr_t d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Normal sized packet that doesn't cross a page boundary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (dma_mapping_error(ip->dma_dev, d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto drop_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) mb(); /* make sure all descriptor changes are visible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ip->tx_skbs[produce] = skb; /* Remember skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) produce = (produce + 1) & TX_RING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ip->tx_pi = produce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) writel(produce << 7, &ip->regs->etpir); /* Fire ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ip->txqlen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ip->txqlen >= (TX_RING_ENTRIES - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) drop_packet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static void ioc3_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) netdev_err(dev, "transmit timed out, resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ioc3_stop(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ioc3_free_rx_bufs(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ioc3_clean_tx_ring(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ioc3_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (ioc3_alloc_rx_bufs(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ioc3_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ioc3_mii_init(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ioc3_mii_start(ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Given a multicast ethernet address, this routine calculates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * address's bit index in the logical address filter mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static inline unsigned int ioc3_hash(const unsigned char *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) crc = ether_crc_le(ETH_ALEN, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) for (bits = 6; --bits >= 0; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) temp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) temp |= (crc & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) crc >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static void ioc3_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int ioc3_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mii_ethtool_get_link_ksettings(&ip->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int ioc3_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int ioc3_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) rc = mii_nway_restart(&ip->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static u32 ioc3_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) rc = mii_link_ok(&ip->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const struct ethtool_ops ioc3_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .get_drvinfo = ioc3_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .nway_reset = ioc3_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .get_link = ioc3_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .get_link_ksettings = ioc3_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .set_link_ksettings = ioc3_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void ioc3_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct ioc3_private *ip = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct ioc3_ethregs *regs = ip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u64 ehar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) spin_lock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ip->emcr |= EMCR_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel(ip->emcr, ®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) readl(®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ip->emcr &= ~EMCR_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) readl(®s->emcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if ((dev->flags & IFF_ALLMULTI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) (netdev_mc_count(dev) > 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* Too many for hashing to make sense or we want all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * multicast packets anyway, so skip computing all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * hashes and just accept all packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ip->ehar_h = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ip->ehar_l = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ehar |= (1UL << ioc3_hash(ha->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ip->ehar_h = ehar >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ip->ehar_l = ehar & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) writel(ip->ehar_h, ®s->ehar_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) writel(ip->ehar_l, ®s->ehar_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) spin_unlock_irq(&ip->ioc3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static struct platform_driver ioc3eth_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .probe = ioc3eth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .remove = ioc3eth_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .name = "ioc3-eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) module_platform_driver(ioc3eth_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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