^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Solarflare network controllers and boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2005-2006 Fen Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006-2013 Solarflare Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "net_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "bitfield.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "efx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "efx_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "nic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "farch_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "workarounds.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mcdi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mcdi_pcol.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "mcdi_port.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "mcdi_port_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "selftest.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "siena_sriov.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void siena_init_wol(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void siena_push_irq_moderation(struct efx_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct efx_nic *efx = channel->efx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) efx_dword_t timer_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (channel->irq_moderation_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) EFX_POPULATE_DWORD_2(timer_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FRF_CZ_TC_TIMER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FFE_CZ_TIMER_MODE_INT_HLDOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FRF_CZ_TC_TIMER_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ticks - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EFX_POPULATE_DWORD_2(timer_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FRF_CZ_TC_TIMER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FFE_CZ_TIMER_MODE_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FRF_CZ_TC_TIMER_VAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) channel->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void siena_prepare_flush(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (efx->fc_disable++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) efx_mcdi_set_mac(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void siena_finish_flush(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (--efx->fc_disable == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) efx_mcdi_set_mac(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct efx_farch_register_test siena_register_tests[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { FR_AZ_ADR_REGION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { FR_CZ_USR_EV_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { FR_AZ_RX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { FR_AZ_TX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { FR_AZ_TX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { FR_AZ_SRM_TX_DC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { FR_AZ_RX_DC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { FR_AZ_RX_DC_PF_WM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { FR_BZ_DP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { FR_BZ_RX_RSS_TKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { FR_CZ_RX_RSS_IPV6_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { FR_CZ_RX_RSS_IPV6_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { FR_CZ_RX_RSS_IPV6_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum reset_type reset_method = RESET_TYPE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int rc, rc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) efx_reset_down(efx, reset_method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Reset the chip immediately so that it is completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * quiescent regardless of what any VF driver does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rc = efx_mcdi_reset(efx, reset_method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tests->registers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) efx_farch_test_registers(efx, siena_register_tests,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ARRAY_SIZE(siena_register_tests))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rc = efx_mcdi_reset(efx, reset_method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rc2 = efx_reset_up(efx, reset_method, rc == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return rc ? rc : rc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * PTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) _efx_writed(efx, cpu_to_le32(host_time),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int siena_ptp_set_ts_config(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct hwtstamp_config *init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) switch (init->rx_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case HWTSTAMP_FILTER_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* if TX timestamping is still requested then leave PTP on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return efx_ptp_change_mode(efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) init->tx_type != HWTSTAMP_TX_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) efx_ptp_get_mode(efx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rc = efx_ptp_change_mode(efx, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MC_CMD_PTP_MODE_V2_ENHANCED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* bug 33070 - old versions of the firmware do not support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * improved UUID filtering option. Similarly old versions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * application do not expect it to be enabled. If the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * does not accept the enhanced mode, fall back to the standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * PTP v2 UUID filtering. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Device reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int siena_map_reset_flags(u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ETH_RESET_OFFLOAD | ETH_RESET_MAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ETH_RESET_PHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SIENA_RESET_MC = (SIENA_RESET_PORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *flags &= ~SIENA_RESET_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return RESET_TYPE_WORLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *flags &= ~SIENA_RESET_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return RESET_TYPE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* no invisible reset implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* When a PCI device is isolated from the bus, a subsequent MMIO read is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * required for the kernel EEH mechanisms to notice. As the Solarflare driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * was written to minimise MMIO read (for latency) then a periodic call to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * the EEH status of the device is required so that device recovery can happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * in a timely fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void siena_monitor(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) eeh_dev_check_failure(eehdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int siena_probe_nvconfig(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 caps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) efx->timer_quantum_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 3072 : 6144; /* 768 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) efx->timer_max_ns = efx->type->timer_period_max *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) efx->timer_quantum_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int siena_dimension_resources(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Each port has a small block of internal SRAM dedicated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * the buffer table and descriptor caches. In theory we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * map both blocks to one port, but we don't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * for memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static unsigned int siena_mem_bar(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static unsigned int siena_mem_map_size(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return FR_CZ_MC_TREG_SMEM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int siena_probe_nic(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct siena_nic_data *nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) efx_oword_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Allocate storage for hardware specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!nic_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) nic_data->efx = efx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) efx->nic_data = nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (efx_farch_fpga_ver(efx) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "Siena FPGA not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) efx->max_channels = EFX_MAX_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) efx->max_vis = EFX_MAX_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) efx->max_tx_channels = EFX_MAX_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) efx->tx_queues_per_channel = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) efx_reado(efx, ®, FR_AZ_CS_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rc = efx_mcdi_init(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Now we can reset the NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) siena_init_wol(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Allocate memory for INT_KER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto fail4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BUG_ON(efx->irq_status.dma_addr & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) netif_dbg(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "INT_KER at %llx (virt %p phys %llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) (unsigned long long)efx->irq_status.dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) efx->irq_status.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (unsigned long long)virt_to_phys(efx->irq_status.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Read in the non-volatile configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rc = siena_probe_nvconfig(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (rc == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "NVRAM is invalid therefore using defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) efx->phy_type = PHY_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) efx->mdio.prtad = MDIO_PRTAD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto fail5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rc = efx_mcdi_mon_probe(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto fail5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_SFC_SRIOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) efx_siena_sriov_probe(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) efx_ptp_defer_probe_with_channel(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fail5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) efx_nic_free_buffer(efx, &efx->irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fail4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fail3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) efx_mcdi_detach(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) efx_mcdi_fini(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) kfree(efx->nic_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int siena_rx_pull_rss_config(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) efx_oword_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * first 128 bits of the same key, assuming it's been set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * siena_rx_push_rss_config, below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) efx_farch_rx_pull_indir_table(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const u32 *rx_indir_table, const u8 *key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) efx_oword_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Set hash key for IPv4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Enable IPv6 RSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sizeof(efx->rss_context.rx_indir_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) efx_farch_rx_push_indir_table(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* This call performs hardware-specific global initialisation, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * defining the descriptor cache sizes and number of RSS channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * It does not set up any buffers, descriptor rings or event queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int siena_init_nic(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) efx_oword_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Recover from a failed assertion post-reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rc = efx_mcdi_handle_assertion(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Squash TX of packets of 16 bytes or less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * descriptors (which is bad).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) efx_reado(efx, &temp, FR_AZ_TX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) efx_writeo(efx, &temp, FR_AZ_TX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) efx_reado(efx, &temp, FR_AZ_RX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Enable hash insertion. This is broken for the 'Falcon' hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * if IPv6 hashing is also enabled, so also select Toeplitz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * TCP/IPv4 and IPv4 hashes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) EFX_RX_USR_BUF_SIZE >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) efx_writeo(efx, &temp, FR_AZ_RX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) efx->rss_context.context_id = 0; /* indicates RSS is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Enable event logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rc = efx_mcdi_log_ctrl(efx, true, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Set destination of both TX and RX Flush events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) efx_farch_init_common(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void siena_remove_nic(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) efx_mcdi_mon_remove(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) efx_nic_free_buffer(efx, &efx->irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) efx_mcdi_reset(efx, RESET_TYPE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) efx_mcdi_detach(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) efx_mcdi_fini(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Tear down the private nic state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) kfree(efx->nic_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) efx->nic_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SIENA_DMA_STAT(ext_name, mcdi_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [SIENA_STAT_ ## ext_name] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SIENA_OTHER_STAT(ext_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define GENERIC_SW_STAT(ext_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SIENA_DMA_STAT(tx_bytes, TX_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SIENA_OTHER_STAT(tx_good_bytes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SIENA_DMA_STAT(tx_packets, TX_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SIENA_DMA_STAT(tx_64, TX_64_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SIENA_OTHER_STAT(tx_collision),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SIENA_DMA_STAT(rx_bytes, RX_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SIENA_OTHER_STAT(rx_good_bytes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SIENA_DMA_STAT(rx_packets, RX_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SIENA_DMA_STAT(rx_64, RX_64_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GENERIC_SW_STAT(rx_nodesc_trunc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GENERIC_SW_STAT(rx_noskb_drops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const unsigned long siena_stat_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) siena_stat_mask, names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int siena_try_update_nic_stats(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u64 *stats = nic_data->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __le64 *dma_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __le64 generation_start, generation_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dma_stats = efx->stats_buffer.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) generation_end = dma_stats[efx->num_mac_stats - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) stats, efx->stats_buffer.addr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (generation_end != generation_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Update derived statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) efx_nic_fix_nodesc_drop_stat(efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) stats[SIENA_STAT_tx_bytes] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) stats[SIENA_STAT_tx_bad_bytes]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) stats[SIENA_STAT_tx_collision] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) stats[SIENA_STAT_tx_single_collision] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) stats[SIENA_STAT_tx_multiple_collision] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) stats[SIENA_STAT_tx_excessive_collision] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stats[SIENA_STAT_tx_late_collision];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) stats[SIENA_STAT_rx_bytes] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) stats[SIENA_STAT_rx_bad_bytes]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) efx_update_sw_stats(efx, stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct rtnl_link_stats64 *core_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u64 *stats = nic_data->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* If we're unlucky enough to read statistics wduring the DMA, wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * up to 10ms for it to finish (typically takes <500us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (retry = 0; retry < 100; ++retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (siena_try_update_nic_stats(efx) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (full_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (core_stats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) stats[GENERIC_STAT_rx_nodesc_trunc] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) stats[GENERIC_STAT_rx_noskb_drops];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) core_stats->multicast = stats[SIENA_STAT_rx_multicast];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) core_stats->collisions = stats[SIENA_STAT_tx_collision];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) core_stats->rx_length_errors =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) stats[SIENA_STAT_rx_gtjumbo] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) stats[SIENA_STAT_rx_length_error];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) core_stats->tx_window_errors =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) stats[SIENA_STAT_tx_late_collision];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) core_stats->rx_errors = (core_stats->rx_length_errors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) core_stats->rx_crc_errors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) core_stats->rx_frame_errors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) stats[SIENA_STAT_rx_symbol_error]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) core_stats->tx_errors = (core_stats->tx_window_errors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) stats[SIENA_STAT_tx_bad]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return SIENA_STAT_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only __always_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) sizeof(efx->multicast_hash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) efx_farch_filter_sync_rx_mode(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) WARN_ON(!mutex_is_locked(&efx->mac_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rc = efx_mcdi_set_mac(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) efx->multicast_hash.byte, sizeof(efx->multicast_hash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) inbuf, sizeof(inbuf), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Wake on LAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) wol->supported = WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (nic_data->wol_filter_id != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) wol->wolopts = WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) memset(&wol->sopass, 0, sizeof(wol->sopass));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int siena_set_wol(struct efx_nic *efx, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (type & ~WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (type & WAKE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (nic_data->wol_filter_id != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) efx_mcdi_wol_filter_remove(efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) nic_data->wol_filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &nic_data->wol_filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pci_wake_from_d3(efx->pci_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rc = efx_mcdi_wol_filter_reset(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) nic_data->wol_filter_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pci_wake_from_d3(efx->pci_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __func__, type, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static void siena_init_wol(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* If it failed, attempt to get into a synchronised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * state with MC by resetting any set WoL filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) efx_mcdi_wol_filter_reset(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) nic_data->wol_filter_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else if (nic_data->wol_filter_id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pci_wake_from_d3(efx->pci_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * MCDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MCDI_PDU(efx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MCDI_DOORBELL(efx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define MCDI_STATUS(efx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void siena_mcdi_request(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const efx_dword_t *hdr, size_t hdr_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const efx_dword_t *sdu, size_t sdu_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) EFX_WARN_ON_PARANOID(hdr_len != 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) efx_writed(efx, hdr, pdu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (i = 0; i < inlen_dw; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Ensure the request is written out before the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* ring the doorbell with a distinctive value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static bool siena_mcdi_poll_response(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) efx_dword_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) efx_readd(efx, &hdr, pdu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* All 1's indicates that shared memory is in reset (and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * not a valid hdr). Wait for it to come out reset before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * completing the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) size_t offset, size_t outlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (i = 0; i < outlen_dw; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int siena_mcdi_poll_reboot(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct siena_nic_data *nic_data = efx->nic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) efx_dword_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) efx_readd(efx, ®, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (value == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) EFX_ZERO_DWORD(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) efx_writed(efx, ®, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* MAC statistics have been cleared on the NIC; clear the local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * copies that we update with efx_update_diff_stat().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (value == MC_STATUS_DWORD_ASSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #ifdef CONFIG_SFC_MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct siena_nvram_type_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct siena_nvram_type_info siena_nvram_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int siena_mtd_probe_partition(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct efx_mcdi_mtd_partition *part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) const struct siena_nvram_type_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) size_t size, erase_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) bool protected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (type >= ARRAY_SIZE(siena_nvram_types) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) siena_nvram_types[type].name == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) info = &siena_nvram_types[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (info->port != efx_port_num(efx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (protected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return -ENODEV; /* hide it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) part->nvram_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) part->common.dev_type_name = "Siena NVRAM manager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) part->common.type_name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) part->common.mtd.type = MTD_NORFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) part->common.mtd.flags = MTD_CAP_NORFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) part->common.mtd.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) part->common.mtd.erasesize = erase_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct efx_mcdi_mtd_partition *parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) size_t n_parts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) uint16_t fw_subtype_list[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) for (i = 0; i < n_parts; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int siena_mtd_probe(struct efx_nic *efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct efx_mcdi_mtd_partition *parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 nvram_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) size_t n_parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ASSERT_RTNL();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) rc = efx_mcdi_nvram_types(efx, &nvram_types);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!parts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) n_parts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) while (nvram_types != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (nvram_types & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rc = siena_mtd_probe_partition(efx, &parts[n_parts],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) n_parts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) else if (rc != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) type++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) nvram_types >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) kfree(parts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #endif /* CONFIG_SFC_MTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static unsigned int siena_check_caps(const struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u8 flag, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Siena did not support MC_CMD_GET_CAPABILITIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * Revision-dependent attributes used by efx.c and nic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) **************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) const struct efx_nic_type siena_a0_nic_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .is_vf = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .mem_bar = siena_mem_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .mem_map_size = siena_mem_map_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .probe = siena_probe_nic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .remove = siena_remove_nic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .init = siena_init_nic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .dimension_resources = siena_dimension_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .fini = efx_port_dummy_op_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .monitor = siena_monitor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .monitor = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .map_reset_reason = efx_mcdi_map_reset_reason,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .map_reset_flags = siena_map_reset_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .reset = efx_mcdi_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .probe_port = efx_mcdi_port_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .remove_port = efx_mcdi_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .fini_dmaq = efx_farch_fini_dmaq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .prepare_flush = siena_prepare_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .finish_flush = siena_finish_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .prepare_flr = efx_port_dummy_op_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .finish_flr = efx_farch_finish_flr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .describe_stats = siena_describe_nic_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .update_stats = siena_update_nic_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .start_stats = efx_mcdi_mac_start_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .pull_stats = efx_mcdi_mac_pull_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .stop_stats = efx_mcdi_mac_stop_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .push_irq_moderation = siena_push_irq_moderation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .reconfigure_mac = siena_mac_reconfigure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .check_mac_fault = efx_mcdi_mac_check_fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .reconfigure_port = efx_mcdi_port_reconfigure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .get_wol = siena_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .set_wol = siena_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .resume_wol = siena_init_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .test_chip = siena_test_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .test_nvram = efx_mcdi_nvram_test_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .mcdi_request = siena_mcdi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .mcdi_poll_response = siena_mcdi_poll_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .mcdi_read_response = siena_mcdi_read_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .mcdi_poll_reboot = siena_mcdi_poll_reboot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .irq_enable_master = efx_farch_irq_enable_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .irq_test_generate = efx_farch_irq_test_generate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .irq_disable_non_ev = efx_farch_irq_disable_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .irq_handle_msi = efx_farch_msi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .irq_handle_legacy = efx_farch_legacy_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .tx_probe = efx_farch_tx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .tx_init = efx_farch_tx_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .tx_remove = efx_farch_tx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .tx_write = efx_farch_tx_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .tx_limit_len = efx_farch_tx_limit_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .tx_enqueue = __efx_enqueue_skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .rx_push_rss_config = siena_rx_push_rss_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .rx_pull_rss_config = siena_rx_pull_rss_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .rx_probe = efx_farch_rx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .rx_init = efx_farch_rx_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .rx_remove = efx_farch_rx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .rx_write = efx_farch_rx_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .rx_defer_refill = efx_farch_rx_defer_refill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .rx_packet = __efx_rx_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .ev_probe = efx_farch_ev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .ev_init = efx_farch_ev_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .ev_fini = efx_farch_ev_fini,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .ev_remove = efx_farch_ev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .ev_process = efx_farch_ev_process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .ev_read_ack = efx_farch_ev_read_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ev_test_generate = efx_farch_ev_test_generate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .filter_table_probe = efx_farch_filter_table_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .filter_table_restore = efx_farch_filter_table_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .filter_table_remove = efx_farch_filter_table_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .filter_insert = efx_farch_filter_insert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .filter_remove_safe = efx_farch_filter_remove_safe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .filter_get_safe = efx_farch_filter_get_safe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .filter_clear_rx = efx_farch_filter_clear_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .filter_count_rx_used = efx_farch_filter_count_rx_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #ifdef CONFIG_RFS_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #ifdef CONFIG_SFC_MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .mtd_probe = siena_mtd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .mtd_rename = efx_mcdi_mtd_rename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .mtd_read = efx_mcdi_mtd_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .mtd_erase = efx_mcdi_mtd_erase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .mtd_write = efx_mcdi_mtd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .mtd_sync = efx_mcdi_mtd_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .ptp_write_host_time = siena_ptp_write_host_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ptp_set_ts_config = siena_ptp_set_ts_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #ifdef CONFIG_SFC_SRIOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .sriov_configure = efx_siena_sriov_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .sriov_init = efx_siena_sriov_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .sriov_fini = efx_siena_sriov_fini,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .sriov_wanted = efx_siena_sriov_wanted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .sriov_reset = efx_siena_sriov_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .sriov_flr = efx_siena_sriov_flr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .vswitching_probe = efx_port_dummy_op_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .vswitching_restore = efx_port_dummy_op_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .vswitching_remove = efx_port_dummy_op_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .set_mac_address = efx_siena_sriov_mac_address_changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .revision = EFX_REV_SIENA_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .rx_buffer_padding = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .can_rx_scatter = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .option_descriptors = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .min_interrupt_mode = EFX_INT_MODE_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) NETIF_F_RXHASH | NETIF_F_NTUPLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .mcdi_max_ver = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .rx_hash_key_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .check_caps = siena_check_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .sensor_event = efx_mcdi_sensor_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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