^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Solarflare network controllers and boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2005-2006 Fen Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006-2013 Solarflare Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef EFX_NIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define EFX_NIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "nic_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "efx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 efx_farch_fpga_ver(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PHY_TYPE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PHY_TYPE_TXC43128 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PHY_TYPE_88E1111 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PHY_TYPE_SFX7101 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PHY_TYPE_QT2022C2 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PHY_TYPE_PM8358 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PHY_TYPE_SFT9001A = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PHY_TYPE_QT2025C = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PHY_TYPE_SFT9001B = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SIENA_STAT_tx_good_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SIENA_STAT_tx_bad_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SIENA_STAT_tx_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SIENA_STAT_tx_bad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SIENA_STAT_tx_pause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SIENA_STAT_tx_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SIENA_STAT_tx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SIENA_STAT_tx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SIENA_STAT_tx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SIENA_STAT_tx_lt64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SIENA_STAT_tx_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SIENA_STAT_tx_65_to_127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SIENA_STAT_tx_128_to_255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SIENA_STAT_tx_256_to_511,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SIENA_STAT_tx_512_to_1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SIENA_STAT_tx_1024_to_15xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SIENA_STAT_tx_15xx_to_jumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SIENA_STAT_tx_gtjumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SIENA_STAT_tx_collision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SIENA_STAT_tx_single_collision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SIENA_STAT_tx_multiple_collision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SIENA_STAT_tx_excessive_collision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SIENA_STAT_tx_deferred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SIENA_STAT_tx_late_collision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SIENA_STAT_tx_excessive_deferred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SIENA_STAT_tx_non_tcpudp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SIENA_STAT_tx_mac_src_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SIENA_STAT_tx_ip_src_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SIENA_STAT_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SIENA_STAT_rx_good_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SIENA_STAT_rx_bad_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SIENA_STAT_rx_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SIENA_STAT_rx_good,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SIENA_STAT_rx_bad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SIENA_STAT_rx_pause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SIENA_STAT_rx_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SIENA_STAT_rx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SIENA_STAT_rx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SIENA_STAT_rx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SIENA_STAT_rx_lt64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SIENA_STAT_rx_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SIENA_STAT_rx_65_to_127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SIENA_STAT_rx_128_to_255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SIENA_STAT_rx_256_to_511,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SIENA_STAT_rx_512_to_1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SIENA_STAT_rx_1024_to_15xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SIENA_STAT_rx_15xx_to_jumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SIENA_STAT_rx_gtjumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SIENA_STAT_rx_bad_gtjumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SIENA_STAT_rx_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SIENA_STAT_rx_false_carrier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SIENA_STAT_rx_symbol_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SIENA_STAT_rx_align_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SIENA_STAT_rx_length_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SIENA_STAT_rx_internal_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SIENA_STAT_rx_nodesc_drop_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SIENA_STAT_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * struct siena_nic_data - Siena NIC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @efx: Pointer back to main interface structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @wol_filter_id: Wake-on-LAN packet filter id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @stats: Hardware statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @vf: Array of &struct siena_vf objects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @vfdi_status: Common VFDI status page to be dmad to VF address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @local_addr_list: List of local addresses. Protected by %local_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @local_page_list: List of DMA addressable pages used to broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * %local_addr_list. Protected by %local_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @peer_work: Work item to broadcast peer addresses to VMs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct siena_nic_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct efx_nic *efx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int wol_filter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u64 stats[SIENA_STAT_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_SFC_SRIOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct siena_vf *vf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct efx_channel *vfdi_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned vf_buftbl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct efx_buffer vfdi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct list_head local_addr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct list_head local_page_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mutex local_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct work_struct peer_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EF10_STAT_port_tx_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EF10_STAT_port_tx_pause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EF10_STAT_port_tx_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EF10_STAT_port_tx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EF10_STAT_port_tx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EF10_STAT_port_tx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EF10_STAT_port_tx_lt64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EF10_STAT_port_tx_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) EF10_STAT_port_tx_65_to_127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EF10_STAT_port_tx_128_to_255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EF10_STAT_port_tx_256_to_511,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EF10_STAT_port_tx_512_to_1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EF10_STAT_port_tx_1024_to_15xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) EF10_STAT_port_tx_15xx_to_jumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EF10_STAT_port_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) EF10_STAT_port_rx_bytes_minus_good_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EF10_STAT_port_rx_good_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EF10_STAT_port_rx_bad_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) EF10_STAT_port_rx_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EF10_STAT_port_rx_good,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EF10_STAT_port_rx_bad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) EF10_STAT_port_rx_pause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EF10_STAT_port_rx_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EF10_STAT_port_rx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) EF10_STAT_port_rx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EF10_STAT_port_rx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EF10_STAT_port_rx_lt64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EF10_STAT_port_rx_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EF10_STAT_port_rx_65_to_127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EF10_STAT_port_rx_128_to_255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) EF10_STAT_port_rx_256_to_511,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EF10_STAT_port_rx_512_to_1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EF10_STAT_port_rx_1024_to_15xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) EF10_STAT_port_rx_15xx_to_jumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) EF10_STAT_port_rx_gtjumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EF10_STAT_port_rx_bad_gtjumbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EF10_STAT_port_rx_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EF10_STAT_port_rx_align_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) EF10_STAT_port_rx_length_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EF10_STAT_port_rx_nodesc_drops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) EF10_STAT_port_rx_pm_trunc_bb_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) EF10_STAT_port_rx_pm_discard_bb_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EF10_STAT_port_rx_pm_trunc_vfifo_full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EF10_STAT_port_rx_pm_discard_vfifo_full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EF10_STAT_port_rx_pm_trunc_qbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EF10_STAT_port_rx_pm_discard_qbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EF10_STAT_port_rx_pm_discard_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) EF10_STAT_port_rx_dp_q_disabled_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EF10_STAT_port_rx_dp_di_dropped_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EF10_STAT_port_rx_dp_streaming_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EF10_STAT_port_rx_dp_hlb_fetch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EF10_STAT_port_rx_dp_hlb_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EF10_STAT_rx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) EF10_STAT_rx_unicast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EF10_STAT_rx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EF10_STAT_rx_multicast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EF10_STAT_rx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) EF10_STAT_rx_broadcast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) EF10_STAT_rx_bad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EF10_STAT_rx_bad_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EF10_STAT_rx_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) EF10_STAT_tx_unicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EF10_STAT_tx_unicast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) EF10_STAT_tx_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EF10_STAT_tx_multicast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) EF10_STAT_tx_broadcast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EF10_STAT_tx_broadcast_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) EF10_STAT_tx_bad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EF10_STAT_tx_bad_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) EF10_STAT_tx_overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EF10_STAT_V1_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) EF10_STAT_fec_corrected_errors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) EF10_STAT_fec_corrected_symbols_lane0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) EF10_STAT_fec_corrected_symbols_lane1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) EF10_STAT_fec_corrected_symbols_lane2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EF10_STAT_fec_corrected_symbols_lane3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) EF10_STAT_ctpio_vi_busy_fallback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) EF10_STAT_ctpio_long_write_success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EF10_STAT_ctpio_missing_dbell_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EF10_STAT_ctpio_overflow_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EF10_STAT_ctpio_underflow_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) EF10_STAT_ctpio_timeout_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EF10_STAT_ctpio_noncontig_wr_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EF10_STAT_ctpio_frm_clobber_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EF10_STAT_ctpio_invalid_wr_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EF10_STAT_ctpio_vi_clobber_fallback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) EF10_STAT_ctpio_unqualified_fallback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EF10_STAT_ctpio_runt_fallback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EF10_STAT_ctpio_success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EF10_STAT_ctpio_fallback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EF10_STAT_ctpio_poison,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EF10_STAT_ctpio_erase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EF10_STAT_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Maximum number of TX PIO buffers we may allocate to a function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * This matches the total number of buffers on each SFC9100-family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EF10_TX_PIOBUF_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * struct efx_ef10_nic_data - EF10 architecture NIC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @mcdi_buf: DMA buffer for MCDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @warm_boot_count: Last seen MC warm boot count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @vi_base: Absolute index of first VI in this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @n_allocated_vis: Number of VIs allocated to this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @n_piobufs: Number of PIO buffers allocated to this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @wc_membase: Base address of write-combining mapping of the memory BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @pio_write_base: Base address for writing PIO buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @pio_write_vi_base: Relative VI number for @pio_write_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @piobuf_handle: Handle of each PIO buffer allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @piobuf_size: size of a single PIO buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @mc_stats: Scratch buffer for converting statistics to the kernel's format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @stats: Hardware statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @workaround_35388: Flag: firmware supports workaround for bug 35388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @workaround_26807: Flag: firmware supports workaround for bug 26807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @workaround_61265: Flag: firmware supports workaround for bug 61265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * after MC reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * %MC_CMD_GET_CAPABILITIES response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * %MC_CMD_GET_CAPABILITIES response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @pf_index: The number for this PF, or the parent PF if this is a VF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef CONFIG_SFC_SRIOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @vf: Pointer to VF data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @vlan_lock: Lock to serialize access to vlan_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @udp_tunnels: UDP tunnel port numbers and types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @udp_tunnels to hardware and thus the push must be re-done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct efx_ef10_nic_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct efx_buffer mcdi_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u16 warm_boot_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int vi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int n_allocated_vis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int n_piobufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *wc_membase, *pio_write_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int pio_write_vi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 piobuf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) bool must_restore_piobufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le64 *mc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u64 stats[EF10_STAT_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bool workaround_35388;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool workaround_26807;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bool workaround_61265;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bool must_check_datapath_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 datapath_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 datapath_caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int rx_dpcpu_fw_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int tx_dpcpu_fw_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool must_probe_vswitching;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int pf_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 port_id[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifdef CONFIG_SFC_SRIOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int vf_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct ef10_vf *vf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 vport_mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct list_head vlan_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct mutex vlan_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct efx_udp_tunnel udp_tunnels[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bool udp_tunnels_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct mutex udp_tunnels_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u64 licensed_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* TSOv2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bool *data_mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int efx_init_sriov(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void efx_fini_sriov(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) extern const struct efx_nic_type siena_a0_nic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) extern const struct efx_nic_type efx_hunt_a0_nic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Falcon/Siena queue operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_addr_t dma_addr, unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int efx_farch_ev_probe(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int efx_farch_ev_init(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void efx_farch_ev_fini(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void efx_farch_ev_remove(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int efx_farch_ev_process(struct efx_channel *channel, int quota);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void efx_farch_ev_read_ack(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void efx_farch_ev_test_generate(struct efx_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Falcon/Siena filter operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int efx_farch_filter_table_probe(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void efx_farch_filter_table_restore(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void efx_farch_filter_table_remove(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool replace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int efx_farch_filter_remove_safe(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum efx_filter_priority priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int efx_farch_filter_get_safe(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) enum efx_filter_priority priority, u32 filter_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct efx_filter_spec *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int efx_farch_filter_clear_rx(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) enum efx_filter_priority priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum efx_filter_priority priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum efx_filter_priority priority, u32 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #ifdef CONFIG_RFS_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Falcon/Siena interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void efx_farch_irq_enable_master(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int efx_farch_irq_test_generate(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void efx_farch_irq_disable_master(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Global Resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void siena_prepare_flush(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int efx_farch_fini_dmaq(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void efx_farch_finish_flr(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void siena_finish_flush(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void falcon_start_nic_stats(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void falcon_stop_nic_stats(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int falcon_reset_xaui(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void efx_farch_init_common(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void efx_farch_rx_push_indir_table(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct efx_farch_register_test {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) efx_oword_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int efx_farch_test_registers(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct efx_farch_register_test *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) size_t n_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) efx_qword_t *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif /* EFX_NIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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