^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Solarflare network controllers and boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2005-2018 Solarflare Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019-2020 Xilinx Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * under the terms of the GNU General Public License version 2 as published
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * by the Free Software Foundation, incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "net_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "efx_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "efx_channels.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ef100_nic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ef100_netdev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ef100_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ef100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EFX_EF100_PCI_DEFAULT_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Number of bytes at start of vendor specified extended capability that indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * that the capability is vendor specified. i.e. offset from value returned by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * pci_find_next_ext_capability() to beginning of vendor specified capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_EXT_CAP_HDR_LENGTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Expected size of a Xilinx continuation address table entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ef100_func_ctl_window {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct ef100_func_ctl_window *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Number of bytes to offset when reading bit position x with dword accessors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ROUND_DOWN_TO_DWORD(x) (((x) & (~31)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXTRACT_BITS(x, lbn, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (((x) >> ((lbn) & 31)) & ((1ull << (width)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u32 _ef100_pci_get_bar_bits_with_width(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int structure_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int lbn, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) efx_dword_t dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) efx_readd(efx, &dword, structure_start + ROUND_DOWN_TO_DWORD(lbn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return EXTRACT_BITS(le32_to_cpu(dword.u32[0]), lbn, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ef100_pci_get_bar_bits(efx, entry_location, bitdef) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) _ef100_pci_get_bar_bits_with_width(efx, entry_location, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ESF_GZ_CFGBAR_ ## bitdef ## _LBN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ESF_GZ_CFGBAR_ ## bitdef ## _WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int ef100_pci_parse_ef100_entry(struct efx_nic *efx, int entry_location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ef100_func_ctl_window *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u64 offset = ef100_pci_get_bar_bits(efx, entry_location, EF100_FUNC_CTL_WIN_OFF) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 bar = ef100_pci_get_bar_bits(efx, entry_location, EF100_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) netif_dbg(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "Found EF100 function control window bar=%d offset=0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bar, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (result->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "Duplicated EF100 table entry.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) result->bar = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) result->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) result->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u64 next_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return next_entry + ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci_resource_len(efx->pci_dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Parse a Xilinx capabilities table entry describing a continuation to a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * sub-table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ef100_pci_parse_continue_entry(struct efx_nic *efx, int entry_location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ef100_func_ctl_window *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int previous_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) efx_oword_t entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) efx_reado(efx, &entry, entry_location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bar = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_CONT_CAP_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) offset = EFX_OWORD_FIELD64(entry, ESF_GZ_CFGBAR_CONT_CAP_OFFSET) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) previous_bar = efx->mem_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (bar == ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bar == ESE_GZ_VSEC_BAR_NUM_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "Bad BAR value of %d in Xilinx capabilities sub-table.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (bar != previous_bar) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) efx_fini_io(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ef100_pci_does_bar_overflow(efx, bar, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bar, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Temporarily map new BAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rc = efx_init_io(efx, bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_resource_len(efx->pci_dev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "Mapping new BAR for Xilinx table failed, rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rc = ef100_pci_walk_xilinx_table(efx, offset, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (bar != previous_bar) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) efx_fini_io(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Put old BAR back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rc = efx_init_io(efx, previous_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_resource_len(efx->pci_dev, previous_bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "Putting old BAR back failed, rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * call ef100_pci_parse_ef100_entry() on any EF100 entries and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * ef100_pci_parse_continue_entry() on any table continuations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct ef100_func_ctl_window *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u64 current_entry = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 id = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 last = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 rev = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (id == ESE_GZ_CFGBAR_ENTRY_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) entry_size = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) netif_dbg(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) id, entry_size, current_entry, efx->mem_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (entry_size < sizeof(u32) * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "Xilinx table entry too short len=0x%x\n", entry_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case ESE_GZ_CFGBAR_ENTRY_EF100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (rev != ESE_GZ_CFGBAR_ENTRY_REV_EF100 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) entry_size < ESE_GZ_CFGBAR_ENTRY_SIZE_EF100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "Bad length or rev for EF100 entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) entry_size, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rc = ef100_pci_parse_ef100_entry(efx, current_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (rev != 0 || entry_size < ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "Bad length or rev for continue entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) entry_size, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rc = ef100_pci_parse_continue_entry(efx, current_entry, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Ignore unknown table entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) current_entry += entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ef100_pci_does_bar_overflow(efx, efx->mem_bar, current_entry)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "Xilinx table overrun at position=0x%llx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) current_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int _ef100_pci_get_config_bits_with_width(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int structure_start, int lbn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int width, u32 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int rc, pos = structure_start + ROUND_DOWN_TO_DWORD(lbn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rc = pci_read_config_dword(efx->pci_dev, pos, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "Failed to read PCI config dword at %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *result = EXTRACT_BITS(temp, lbn, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ef100_pci_get_config_bits(efx, entry_location, bitdef, result) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) _ef100_pci_get_config_bits_with_width(efx, entry_location, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ESF_GZ_VSEC_ ## bitdef ## _LBN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ESF_GZ_VSEC_ ## bitdef ## _WIDTH, result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Call ef100_pci_walk_xilinx_table() for the Xilinx capabilities table pointed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * to by this PCI_EXT_CAP_ID_VNDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int ef100_pci_parse_xilinx_cap(struct efx_nic *efx, int vndr_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bool has_offset_hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct ef100_func_ctl_window *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 offset_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 offset_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u64 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_BAR, &bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "Failed to read ESF_GZ_VSEC_TBL_BAR, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "Bad BAR value of %d in Xilinx capabilities sub-table.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_LO, &offset_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Failed to read ESF_GZ_VSEC_TBL_OFF_LO, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Get optional extension to 64bit offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (has_offset_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_HI, &offset_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "Failed to read ESF_GZ_VSEC_TBL_OFF_HI, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) offset = (((u64)offset_lo) << ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) (((u64)offset_high) << ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (offset > pci_resource_len(efx->pci_dev, bar) - sizeof(u32) * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bar, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Temporarily map BAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rc = efx_init_io(efx, bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pci_resource_len(efx->pci_dev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "efx_init_io failed, rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rc = ef100_pci_walk_xilinx_table(efx, offset, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Unmap temporarily mapped BAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) efx_fini_io(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Call ef100_pci_parse_ef100_entry() for each Xilinx PCI_EXT_CAP_ID_VNDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int ef100_pci_find_func_ctrl_window(struct efx_nic *efx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ef100_func_ctl_window *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int num_xilinx_caps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) result->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while ((cap = pci_find_next_ext_capability(efx->pci_dev, cap, PCI_EXT_CAP_ID_VNDR)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int vndr_cap = cap + PCI_EXT_CAP_HDR_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 vsec_ver = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 vsec_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 vsec_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) num_xilinx_caps++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rc = ef100_pci_get_config_bits(efx, vndr_cap, ID, &vsec_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "Failed to read ESF_GZ_VSEC_ID, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rc = ef100_pci_get_config_bits(efx, vndr_cap, VER, &vsec_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Failed to read ESF_GZ_VSEC_VER, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Get length of whole capability - i.e. starting at cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rc = ef100_pci_get_config_bits(efx, vndr_cap, LEN, &vsec_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "Failed to read ESF_GZ_VSEC_LEN, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (vsec_id == ESE_GZ_XILINX_VSEC_ID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) vsec_ver == ESE_GZ_VSEC_VER_XIL_CFGBAR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) vsec_len >= ESE_GZ_VSEC_LEN_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) bool has_offset_hi = (vsec_len >= ESE_GZ_VSEC_LEN_HIGH_OFFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rc = ef100_pci_parse_xilinx_cap(efx, vndr_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) has_offset_hi, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (num_xilinx_caps && !result->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "Seen %d Xilinx tables, but no EF100 entry.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) num_xilinx_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Final NIC shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * This is called only at module unload (or hotplug removal). A PF can call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * this on its VFs to ensure they are unbound first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void ef100_pci_remove(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct efx_nic *efx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) efx = pci_get_drvdata(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!efx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_close(efx->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Unregistering our netdev notifier triggers unbinding of TC indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * blocks, so we have to do it before PCI removal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unregister_netdevice_notifier(&efx->netdev_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ef100_remove(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) efx_fini_io(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pci_set_drvdata(pci_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) efx_fini_struct(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) free_netdev(efx->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_disable_pcie_error_reporting(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int ef100_pci_probe(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const struct pci_device_id *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct ef100_func_ctl_window fcw = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct net_device *net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct efx_nic *efx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Allocate and initialise a struct net_device and struct efx_nic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) efx = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) efx->type = (const struct efx_nic_type *)entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci_set_drvdata(pci_dev, efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SET_NETDEV_DEV(net_dev, &pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rc = efx_init_struct(efx, pci_dev, net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) efx->vi_stride = EF100_DEFAULT_VI_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) netif_info(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "Solarflare EF100 NIC detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rc = ef100_pci_find_func_ctrl_window(efx, &fcw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "Error looking for ef100 function control window, rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!fcw.valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Extended capability not found - use defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fcw.bar = EFX_EF100_PCI_DEFAULT_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fcw.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) fcw.valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (fcw.offset > pci_resource_len(efx->pci_dev, fcw.bar) - ESE_GZ_FCW_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "Func control window overruns BAR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Set up basic I/O (BAR mappings etc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rc = efx_init_io(efx, fcw.bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_resource_len(efx->pci_dev, fcw.bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) efx->reg_base = fcw.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) efx->netdev_notifier.notifier_call = ef100_netdev_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) rc = register_netdevice_notifier(&efx->netdev_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) netif_err(efx, probe, efx->net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "Failed to register netdevice notifier, rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rc = efx->type->probe(efx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ef100_pci_remove(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* PCI device ID table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct pci_device_id ef100_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x0100), /* Riverhead PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .driver_data = (unsigned long) &ef100_pf_nic_type },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x1100), /* Riverhead VF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .driver_data = (unsigned long) &ef100_vf_nic_type },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0} /* end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct pci_driver ef100_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .name = "sfc_ef100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .id_table = ef100_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .probe = ef100_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .remove = ef100_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .err_handler = &efx_err_handlers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DEVICE_TABLE(pci, ef100_pci_table);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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