^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/acorn/net/ether3.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * network driver for Acorn/ANT Ether3 cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _LINUX_ether3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _LINUX_ether3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DEBUG_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEBUG_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEBUG_INT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEBUG_IC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef NET_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NET_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define priv(dev) ((struct dev_priv *)netdev_priv(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Command register definitions & bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_COMMAND (priv(dev)->seeq + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CMD_ENINTDMA 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMD_ENINTRX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMD_ENINTTX 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMD_ENINTBUFWIN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMD_ACKINTDMA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMD_ACKINTRX 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMD_ACKINTTX 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMD_ACKINTBUFWIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMD_DMAON 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMD_RXON 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMD_TXON 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMD_DMAOFF 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMD_RXOFF 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMD_TXOFF 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMD_FIFOREAD 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_FIFOWRITE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_STATUS (priv(dev)->seeq + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STAT_ENINTSTAT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STAT_ENINTRX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STAT_ENINTTX 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STAT_ENINTBUFWIN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STAT_INTDMA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STAT_INTRX 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STAT_INTTX 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STAT_INTBUFWIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STAT_DMAON 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STAT_RXON 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STAT_TXON 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STAT_FIFOFULL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STAT_FIFOEMPTY 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STAT_FIFODIR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* configuration register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_CONFIG1 (priv(dev)->seeq + 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CFG1_BUFSELSTAT0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CFG1_BUFSELSTAT1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CFG1_BUFSELSTAT2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CFG1_BUFSELSTAT3 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CFG1_BUFSELSTAT4 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CFG1_BUFSELSTAT5 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CFG1_ADDRPROM 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CFG1_TRANSEND 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CFG1_LOCBUFMEM 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CFG1_INTVECTOR 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CFG1_RECVSPECONLY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CFG1_RECVSPECBROAD 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CFG1_RECVSPECBRMULTI 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CFG1_RECVPROMISC 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* The following aren't in 8004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CFG1_DMABURSTCONT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CFG1_DMABURST800NS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CFG1_DMABURST1600NS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CFG1_DMABURST3200NS 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CFG1_DMABURST1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CFG1_DMABURST4 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CFG1_DMABURST8 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CFG1_DMABURST16 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CFG1_RECVCOMPSTAT0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CFG1_RECVCOMPSTAT1 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CFG1_RECVCOMPSTAT2 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CFG1_RECVCOMPSTAT3 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CFG1_RECVCOMPSTAT4 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CFG1_RECVCOMPSTAT5 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* configuration register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_CONFIG2 (priv(dev)->seeq + 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CFG2_BYTESWAP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CFG2_ERRENCRC 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CFG2_ERRENDRIBBLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CFG2_ERRSHORTFRAME 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CFG2_SLOTSELECT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CFG2_PREAMSELECT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CFG2_ADDRLENGTH 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CFG2_RECVCRC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CFG2_XMITNOCRC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CFG2_LOOPBACK 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CFG2_CTRLO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CFG2_RESET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_RECVEND (priv(dev)->seeq + 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_BUFWIN (priv(dev)->seeq + 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_RECVPTR (priv(dev)->seeq + 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_TRANSMITPTR (priv(dev)->seeq + 0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_DMAADDR (priv(dev)->seeq + 0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Cards transmit/receive headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TX_NEXT (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TXHDR_ENBABBLEINT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TXHDR_ENCOLLISIONINT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TXHDR_EN16COLLISION (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TXHDR_ENSUCCESS (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TXHDR_DATAFOLLOWS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TXHDR_CHAINCONTINUE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TXHDR_TRANSMIT (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TXSTAT_BABBLED (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TXSTAT_COLLISION (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TXSTAT_16COLLISIONS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TXSTAT_DONE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RX_NEXT (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RXHDR_CHAINCONTINUE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RXHDR_RECEIVE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RXSTAT_OVERSIZE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RXSTAT_CRCERROR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RXSTAT_DRIBBLEERROR (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RXSTAT_SHORTPACKET (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RXSTAT_DONE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TX_START 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TX_END 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RX_START 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RX_LEN 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RX_END 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* must be a power of 2 and greater than MAX_TX_BUFFERED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MAX_TXED 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAX_TX_BUFFERED 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct dev_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *seeq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char tx_head; /* buffer nr to insert next packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char tx_tail; /* buffer nr of transmitting packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int rx_head; /* address to fetch next packet from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int broken; /* 0 = ok, 1 = something went wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ether3_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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