^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Renesas Ethernet AVB device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014-2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on the SuperH Ethernet driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __RAVB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __RAVB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mdio-bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BE_TX_RING_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BE_RX_RING_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BE_TX_RING_MAX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BE_RX_RING_MAX 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PKT_BUF_SZ 1538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Driver's parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RAVB_ALIGN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Hardware time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum ravb_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* AVB-DMAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CCC = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DBAT = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DLR = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CSR = 0x000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CDAR0 = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CDAR1 = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CDAR2 = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CDAR3 = 0x001C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CDAR4 = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CDAR5 = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CDAR6 = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CDAR7 = 0x002C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CDAR8 = 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CDAR9 = 0x0034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CDAR10 = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CDAR11 = 0x003C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CDAR12 = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CDAR13 = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CDAR14 = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CDAR15 = 0x004C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CDAR16 = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CDAR17 = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CDAR18 = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CDAR19 = 0x005C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CDAR20 = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CDAR21 = 0x0064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ESR = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) APSR = 0x008C, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RCR = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RQC0 = 0x0094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RQC1 = 0x0098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RQC2 = 0x009C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RQC3 = 0x00A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RQC4 = 0x00A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RPC = 0x00B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) UFCW = 0x00BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) UFCS = 0x00C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) UFCV0 = 0x00C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) UFCV1 = 0x00C8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) UFCV2 = 0x00CC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) UFCV3 = 0x00D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) UFCV4 = 0x00D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) UFCD0 = 0x00E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) UFCD1 = 0x00E4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) UFCD2 = 0x00E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) UFCD3 = 0x00EC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) UFCD4 = 0x00F0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SFO = 0x00FC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SFP0 = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SFP1 = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SFP2 = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SFP3 = 0x010C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SFP4 = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SFP5 = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SFP6 = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SFP7 = 0x011C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SFP8 = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SFP9 = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SFP10 = 0x0128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SFP11 = 0x012C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SFP12 = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SFP13 = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SFP14 = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SFP15 = 0x013C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SFP16 = 0x0140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SFP17 = 0x0144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SFP18 = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SFP19 = 0x014C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SFP20 = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SFP21 = 0x0154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SFP22 = 0x0158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SFP23 = 0x015C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SFP24 = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SFP25 = 0x0164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SFP26 = 0x0168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SFP27 = 0x016C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SFP28 = 0x0170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SFP29 = 0x0174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SFP30 = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SFP31 = 0x017C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SFM0 = 0x01C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SFM1 = 0x01C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) TGC = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TCCR = 0x0304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TSR = 0x0308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) TFA0 = 0x0310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TFA1 = 0x0314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TFA2 = 0x0318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CIVR0 = 0x0320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CIVR1 = 0x0324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CDVR0 = 0x0328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CDVR1 = 0x032C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CUL0 = 0x0330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CUL1 = 0x0334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLL0 = 0x0338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLL1 = 0x033C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DIC = 0x0350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DIS = 0x0354,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EIC = 0x0358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EIS = 0x035C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) RIC0 = 0x0360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) RIS0 = 0x0364,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) RIC1 = 0x0368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) RIS1 = 0x036C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) RIC2 = 0x0370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RIS2 = 0x0374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TIC = 0x0378,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TIS = 0x037C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ISS = 0x0380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CIE = 0x0384, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GCCR = 0x0390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GMTT = 0x0394,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GPTC = 0x0398,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GTI = 0x039C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GTO0 = 0x03A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GTO1 = 0x03A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GTO2 = 0x03A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GIC = 0x03AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GIS = 0x03B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) GCPT = 0x03B4, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GCT0 = 0x03B8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) GCT1 = 0x03BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GCT2 = 0x03C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GIE = 0x03CC, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) GID = 0x03D0, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DIL = 0x0440, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RIE0 = 0x0460, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RID0 = 0x0464, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RIE2 = 0x0470, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RID2 = 0x0474, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) TIE = 0x0478, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TID = 0x047c, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* E-MAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ECMR = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) RFLR = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ECSR = 0x0510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ECSIPR = 0x0518,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PIR = 0x0520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PSR = 0x0528,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PIPR = 0x052c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MPR = 0x0558,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PFTCR = 0x055c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PFRCR = 0x0560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GECMR = 0x05b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MAHR = 0x05c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MALR = 0x05c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) TROCR = 0x0700, /* R-Car Gen3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CEFCR = 0x0740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FRECR = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TSFRCR = 0x0750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TLFRCR = 0x0758,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) RFCR = 0x0760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MAFCR = 0x0778,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Register bits of the Ethernet AVB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* CCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) enum CCC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CCC_OPC = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CCC_OPC_RESET = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CCC_OPC_CONFIG = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CCC_OPC_OPERATION = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CCC_GAC = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CCC_DTSR = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CCC_CSEL = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CCC_CSEL_HPB = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CCC_CSEL_ETH_TX = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CCC_CSEL_GMII_REF = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CCC_LBME = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) enum CSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CSR_OPS = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CSR_OPS_RESET = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CSR_OPS_CONFIG = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CSR_OPS_OPERATION = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CSR_OPS_STANDBY = 0x00000008, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CSR_DTS = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CSR_TPO0 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CSR_TPO1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CSR_TPO2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CSR_TPO3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CSR_RPO = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* ESR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum ESR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ESR_EQN = 0x0000001F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ESR_ET = 0x00000F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ESR_EIL = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* APSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum APSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) APSR_MEMS = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) APSR_CMSW = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) APSR_DM = 0x00006000, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) APSR_DM_RDM = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) APSR_DM_TDM = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* RCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum RCR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RCR_EFFS = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RCR_ENCF = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) RCR_ESF = 0x0000000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RCR_ETS0 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RCR_ETS2 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RCR_RFCL = 0x1FFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* RQC0/1/2/3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) enum RQC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) RQC_RSM0 = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) RQC_UFCC0 = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) RQC_RSM1 = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) RQC_UFCC1 = 0x00003000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RQC_RSM2 = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RQC_UFCC2 = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) RQC_RSM3 = 0x03000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) RQC_UFCC3 = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* RPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum RPC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RPC_PCNT = 0x00000700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) RPC_DCNT = 0x00FF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* UFCW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum UFCW_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) UFCW_WL0 = 0x0000003F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) UFCW_WL1 = 0x00003F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) UFCW_WL2 = 0x003F0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) UFCW_WL3 = 0x3F000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* UFCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum UFCS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) UFCS_SL0 = 0x0000003F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) UFCS_SL1 = 0x00003F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) UFCS_SL2 = 0x003F0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) UFCS_SL3 = 0x3F000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* UFCV0/1/2/3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum UFCV_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) UFCV_CV0 = 0x0000003F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) UFCV_CV1 = 0x00003F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) UFCV_CV2 = 0x003F0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) UFCV_CV3 = 0x3F000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* UFCD0/1/2/3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum UFCD_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) UFCD_DV0 = 0x0000003F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) UFCD_DV1 = 0x00003F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) UFCD_DV2 = 0x003F0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) UFCD_DV3 = 0x3F000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* SFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum SFO_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SFO_FBP = 0x0000003F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum RTC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RTC_MFL0 = 0x00000FFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RTC_MFL1 = 0x0FFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* TGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum TGC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TGC_TSM0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) TGC_TSM1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) TGC_TSM2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) TGC_TSM3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) TGC_TQP = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) TGC_TQP_NONAVB = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) TGC_TQP_AVBMODE1 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) TGC_TQP_AVBMODE2 = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) TGC_TBD0 = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) TGC_TBD1 = 0x00003000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) TGC_TBD2 = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) TGC_TBD3 = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* TCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum TCCR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) TCCR_TSRQ0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) TCCR_TSRQ1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) TCCR_TSRQ2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) TCCR_TSRQ3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) TCCR_TFEN = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) TCCR_TFR = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* TSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum TSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TSR_CCS0 = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TSR_CCS1 = 0x0000000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TSR_TFFL = 0x00000700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* TFA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum TFA2_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TFA2_TSV = 0x0000FFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TFA2_TST = 0x03FF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* DIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) enum DIC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DIC_DPE1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DIC_DPE2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DIC_DPE3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DIC_DPE4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DIC_DPE5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DIC_DPE6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DIC_DPE7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DIC_DPE8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DIC_DPE9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DIC_DPE10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DIC_DPE11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DIC_DPE12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DIC_DPE13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DIC_DPE14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DIC_DPE15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* DIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum DIS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DIS_DPF1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DIS_DPF2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DIS_DPF3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DIS_DPF4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DIS_DPF5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DIS_DPF6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DIS_DPF7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DIS_DPF8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DIS_DPF9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DIS_DPF10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DIS_DPF11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DIS_DPF12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DIS_DPF13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DIS_DPF14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DIS_DPF15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* EIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enum EIC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EIC_MREE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) EIC_MTEE = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) EIC_QEE = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) EIC_SEE = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) EIC_CLLE0 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) EIC_CLLE1 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) EIC_CULE0 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) EIC_CULE1 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EIC_TFFE = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* EIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum EIS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) EIS_MREF = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) EIS_MTEF = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) EIS_QEF = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) EIS_SEF = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) EIS_CLLF0 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) EIS_CLLF1 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) EIS_CULF0 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) EIS_CULF1 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) EIS_TFFF = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) EIS_QFS = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) EIS_RESERVED = (GENMASK(31, 17) | GENMASK(15, 11)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* RIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum RIC0_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RIC0_FRE0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RIC0_FRE1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RIC0_FRE2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RIC0_FRE3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RIC0_FRE4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RIC0_FRE5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RIC0_FRE6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) RIC0_FRE7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RIC0_FRE8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RIC0_FRE9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) RIC0_FRE10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RIC0_FRE11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RIC0_FRE12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) RIC0_FRE13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RIC0_FRE14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RIC0_FRE15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RIC0_FRE16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RIC0_FRE17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* RIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enum RIS0_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RIS0_FRF0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) RIS0_FRF1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RIS0_FRF2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RIS0_FRF3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RIS0_FRF4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RIS0_FRF5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RIS0_FRF6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RIS0_FRF7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RIS0_FRF8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) RIS0_FRF9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RIS0_FRF10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RIS0_FRF11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RIS0_FRF12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RIS0_FRF13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RIS0_FRF14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RIS0_FRF15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RIS0_FRF16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) RIS0_FRF17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RIS0_RESERVED = GENMASK(31, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* RIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum RIC1_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RIC1_RFWE = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* RIS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) enum RIS1_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RIS1_RFWF = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* RIC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum RIC2_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RIC2_QFE0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RIC2_QFE1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RIC2_QFE2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RIC2_QFE3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) RIC2_QFE4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RIC2_QFE5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) RIC2_QFE6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RIC2_QFE7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RIC2_QFE8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RIC2_QFE9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) RIC2_QFE10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RIC2_QFE11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RIC2_QFE12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RIC2_QFE13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) RIC2_QFE14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) RIC2_QFE15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RIC2_QFE16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RIC2_QFE17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RIC2_RFFE = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* RIS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enum RIS2_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RIS2_QFF0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RIS2_QFF1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RIS2_QFF2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RIS2_QFF3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RIS2_QFF4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RIS2_QFF5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) RIS2_QFF6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RIS2_QFF7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RIS2_QFF8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) RIS2_QFF9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) RIS2_QFF10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RIS2_QFF11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) RIS2_QFF12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RIS2_QFF13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RIS2_QFF14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RIS2_QFF15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RIS2_QFF16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RIS2_QFF17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RIS2_RFFF = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RIS2_RESERVED = GENMASK(30, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* TIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) enum TIC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) TIC_FTE0 = 0x00000001, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) TIC_FTE1 = 0x00000002, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) TIC_TFUE = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) TIC_TFWE = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* TIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) enum TIS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TIS_FTF0 = 0x00000001, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) TIS_FTF1 = 0x00000002, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) TIS_TFUF = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) TIS_TFWF = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TIS_RESERVED = (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* ISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum ISS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ISS_FRS = 0x00000001, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ISS_FTS = 0x00000004, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ISS_ES = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ISS_MS = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ISS_TFUS = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ISS_TFWS = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ISS_RFWS = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ISS_CGIS = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ISS_DPS1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ISS_DPS2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ISS_DPS3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ISS_DPS4 = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ISS_DPS5 = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ISS_DPS6 = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ISS_DPS7 = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ISS_DPS8 = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ISS_DPS9 = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ISS_DPS10 = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ISS_DPS11 = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ISS_DPS12 = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ISS_DPS13 = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ISS_DPS14 = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ISS_DPS15 = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* CIE (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) enum CIE_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CIE_CRIE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CIE_CTIE = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CIE_RQFM = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CIE_CL0M = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CIE_RFWL = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CIE_RFFL = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* GCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) enum GCCR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GCCR_TCR = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GCCR_TCR_NOREQ = 0x00000000, /* No request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GCCR_LTO = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GCCR_LTI = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GCCR_LPTC = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GCCR_LMTT = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GCCR_TCSS = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* GTI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) enum GTI_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GTI_TIV = 0x0FFFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define GTI_TIV_MAX GTI_TIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define GTI_TIV_MIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* GIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) enum GIC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GIC_PTCE = 0x00000001, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GIC_PTME = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* GIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) enum GIS_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GIS_PTCF = 0x00000001, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GIS_PTMF = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GIS_RESERVED = GENMASK(15, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* GIE (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) enum GIE_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GIE_PTCS = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GIE_PTOS = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GIE_PTMS0 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GIE_PTMS1 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GIE_PTMS2 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GIE_PTMS3 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GIE_PTMS4 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GIE_PTMS5 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GIE_PTMS6 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GIE_PTMS7 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GIE_ATCS0 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GIE_ATCS1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GIE_ATCS2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GIE_ATCS3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GIE_ATCS4 = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GIE_ATCS5 = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GIE_ATCS6 = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GIE_ATCS7 = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GIE_ATCS8 = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GIE_ATCS9 = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GIE_ATCS10 = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GIE_ATCS11 = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GIE_ATCS12 = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GIE_ATCS13 = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GIE_ATCS14 = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GIE_ATCS15 = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* GID (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) enum GID_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GID_PTCD = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GID_PTOD = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GID_PTMD0 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GID_PTMD1 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GID_PTMD2 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GID_PTMD3 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GID_PTMD4 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GID_PTMD5 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GID_PTMD6 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GID_PTMD7 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GID_ATCD0 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GID_ATCD1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GID_ATCD2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GID_ATCD3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GID_ATCD4 = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GID_ATCD5 = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GID_ATCD6 = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GID_ATCD7 = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GID_ATCD8 = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GID_ATCD9 = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GID_ATCD10 = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GID_ATCD11 = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GID_ATCD12 = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GID_ATCD13 = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GID_ATCD14 = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GID_ATCD15 = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* RIE0 (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) enum RIE0_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RIE0_FRS0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RIE0_FRS1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RIE0_FRS2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RIE0_FRS3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RIE0_FRS4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RIE0_FRS5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RIE0_FRS6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) RIE0_FRS7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RIE0_FRS8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RIE0_FRS9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RIE0_FRS10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RIE0_FRS11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RIE0_FRS12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RIE0_FRS13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RIE0_FRS14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RIE0_FRS15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RIE0_FRS16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RIE0_FRS17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* RID0 (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum RID0_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RID0_FRD0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RID0_FRD1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RID0_FRD2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RID0_FRD3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RID0_FRD4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RID0_FRD5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RID0_FRD6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RID0_FRD7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RID0_FRD8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RID0_FRD9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RID0_FRD10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RID0_FRD11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RID0_FRD12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RID0_FRD13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RID0_FRD14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RID0_FRD15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RID0_FRD16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) RID0_FRD17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* RIE2 (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) enum RIE2_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RIE2_QFS0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RIE2_QFS1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RIE2_QFS2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RIE2_QFS3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RIE2_QFS4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RIE2_QFS5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RIE2_QFS6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RIE2_QFS7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RIE2_QFS8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RIE2_QFS9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RIE2_QFS10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RIE2_QFS11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RIE2_QFS12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) RIE2_QFS13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RIE2_QFS14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RIE2_QFS15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RIE2_QFS16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RIE2_QFS17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RIE2_RFFS = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* RID2 (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) enum RID2_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RID2_QFD0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RID2_QFD1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RID2_QFD2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RID2_QFD3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RID2_QFD4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RID2_QFD5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RID2_QFD6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RID2_QFD7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) RID2_QFD8 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RID2_QFD9 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RID2_QFD10 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RID2_QFD11 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RID2_QFD12 = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RID2_QFD13 = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RID2_QFD14 = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RID2_QFD15 = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RID2_QFD16 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RID2_QFD17 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RID2_RFFD = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* TIE (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) enum TIE_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TIE_FTS0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TIE_FTS1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) TIE_FTS2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TIE_FTS3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TIE_TFUS = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TIE_TFWS = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TIE_MFUS = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TIE_MFWS = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TIE_TDPS0 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TIE_TDPS1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TIE_TDPS2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TIE_TDPS3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* TID (R-Car Gen3 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) enum TID_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) TID_FTD0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TID_FTD1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TID_FTD2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TID_FTD3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TID_TFUD = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TID_TFWD = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TID_MFUD = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TID_MFWD = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) TID_TDPD0 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TID_TDPD1 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TID_TDPD2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TID_TDPD3 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* ECMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) enum ECMR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ECMR_PRM = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ECMR_DM = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ECMR_TE = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ECMR_RE = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ECMR_MPDE = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ECMR_TXF = 0x00010000, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ECMR_RXF = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ECMR_PFR = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ECMR_ZPF = 0x00080000, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ECMR_RZPF = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ECMR_DPAD = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ECMR_RCSC = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ECMR_TRCCM = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* ECSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) enum ECSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ECSR_ICD = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ECSR_MPD = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ECSR_LCHNG = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ECSR_PHYI = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* ECSIPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) enum ECSIPR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ECSIPR_ICDIP = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ECSIPR_MPDIP = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ECSIPR_LCHNGIP = 0x00000004, /* Undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* PIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) enum PIR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PIR_MDC = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PIR_MMD = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PIR_MDO = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PIR_MDI = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* PSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) enum PSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PSR_LMON = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* PIPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) enum PIPR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PIPR_PHYIP = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* MPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) enum MPR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MPR_MP = 0x0000ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* GECMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) enum GECMR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) GECMR_SPEED = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GECMR_SPEED_100 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) GECMR_SPEED_1000 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* The Ethernet AVB descriptor definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct ravb_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) __le16 ds; /* Descriptor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 cc; /* Content control MSBs (reserved) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u8 die_dt; /* Descriptor interrupt enable and type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __le32 dptr; /* Descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DPTR_ALIGN 4 /* Required descriptor pointer alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) enum DIE_DT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Frame data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DT_FMID = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DT_FSTART = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DT_FEND = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DT_FSINGLE = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Chain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DT_LINK = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DT_LINKFIX = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DT_EOS = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* HW/SW arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DT_FEMPTY = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DT_FEMPTY_IS = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DT_FEMPTY_IC = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DT_FEMPTY_ND = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DT_LEMPTY = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DT_EEMPTY = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct ravb_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __le16 ds_cc; /* Descriptor size and content control LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u8 msc; /* MAC status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u8 die_dt; /* Descriptor interrupt enable and type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __le32 dptr; /* Descpriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct ravb_ex_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __le16 ds_cc; /* Descriptor size and content control lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u8 msc; /* MAC status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u8 die_dt; /* Descriptor interrupt enable and type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) __le32 dptr; /* Descpriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) __le32 ts_n; /* Timestampe nsec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __le32 ts_sl; /* Timestamp low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) __le16 ts_sh; /* Timestamp high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __le16 res; /* Reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) enum RX_DS_CC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) RX_DS = 0x0fff, /* Data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RX_TR = 0x1000, /* Truncation indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) RX_EI = 0x2000, /* Error indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RX_PS = 0xc000, /* Padding selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* E-MAC status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) enum MSC_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MSC_CRC = 0x01, /* Frame CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MSC_RTSF = 0x04, /* Frame length error (frame too short) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MSC_RTLF = 0x08, /* Frame length error (frame too long) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MSC_CRL = 0x20, /* Carrier lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MSC_CEEF = 0x40, /* Carrier extension error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MSC_MC = 0x80, /* Multicast frame reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct ravb_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) __le16 ds_tagl; /* Descriptor size and frame tag LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u8 die_dt; /* Descriptor interrupt enable and type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __le32 dptr; /* Descpriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) enum TX_DS_TAGL_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) TX_DS = 0x0fff, /* Data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) TX_TAGL = 0xf000, /* Frame tag LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) enum TX_TAGH_TSR_BIT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) TX_TAGH = 0x3f, /* Frame tag MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) TX_TSR = 0x40, /* Timestamp storage request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) enum RAVB_QUEUE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RAVB_BE = 0, /* Best Effort Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RAVB_NC, /* Network Control Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define DBAT_ENTRY_NUM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define RX_QUEUE_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define NUM_RX_QUEUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define NUM_TX_QUEUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* TX descriptors per packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define NUM_TX_DESC_GEN2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define NUM_TX_DESC_GEN3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct ravb_tstamp_skb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct ravb_ptp_perout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define N_EXT_TS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define N_PER_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct ravb_ptp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct ptp_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct ptp_clock_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 default_addend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 current_addend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int extts[N_EXT_TS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct ravb_ptp_perout perout[N_PER_OUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) enum ravb_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) RCAR_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RCAR_GEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct ravb_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct mdiobb_ctrl mdiobb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 num_rx_ring[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 num_tx_ring[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u32 desc_bat_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dma_addr_t desc_bat_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct ravb_desc *desc_bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void *tx_align[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct sk_buff **rx_skb[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct sk_buff **tx_skb[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 rx_over_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 rx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct net_device_stats stats[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u32 tstamp_tx_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 tstamp_rx_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct list_head ts_skb_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 ts_skb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct ravb_ptp ptp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) spinlock_t lock; /* Register access lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 cur_tx[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u32 dirty_tx[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct napi_struct napi[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* MII transceiver section. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct mii_bus *mii_bus; /* MDIO bus control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) phy_interface_t phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) int emac_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) enum ravb_chip_id chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int rx_irqs[NUM_RX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int tx_irqs[NUM_TX_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned no_avb_link:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unsigned avb_link_active_low:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) unsigned wol_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned rxcidm:1; /* RX Clock Internal Delay Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned txcidm:1; /* TX Clock Internal Delay Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned rgmii_override:1; /* Deprecated rgmii-*id behavior */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int num_tx_desc; /* TX descriptors per packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct ravb_private *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return ioread32(priv->addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static inline void ravb_write(struct net_device *ndev, u32 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) enum ravb_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct ravb_private *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) iowrite32(data, priv->addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) void ravb_ptp_interrupt(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) void ravb_ptp_stop(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #endif /* #ifndef __RAVB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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