^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Written 1998-2000 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Updates 2000 by Keith Underwood.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Drivers based on or derived from this code fall under the GPL and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) retain the authorship, copyright and license notice. This file is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) a complete program and may only be used when the entire operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) system is licensed under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The author may be reached as becker@scyld.com, or C/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Scyld Computing Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 410 Severn Ave., Suite 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Annapolis MD 21403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Support and updates available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) http://www.scyld.com/network/hamachi.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [link no longer provides useful info -jgarzik]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) http://www.parl.clemson.edu/~keithu/hamachi.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_NAME "hamachi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_VERSION "2.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRV_RELDATE "Sept 11, 2006"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* A few user-configurable values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define final_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define hamachi_debug debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int max_interrupt_work = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Default values selected by testing on a dual processor PIII-450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* These six interrupt control parameters may be set directly when loading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * module, or through the rx_params and tx_params variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int max_rx_latency = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int max_rx_gap = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int min_rx_pkt = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int max_tx_latency = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int max_tx_gap = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int min_tx_pkt = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) -Setting to > 1518 causes all frames to be copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) -Setting to 0 disables copies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* An override for the hardware detection of bus width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Add 2 to disable parity detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int force32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Used to pass the media type, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) These exist for driver interoperability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) No media types are currently defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - The lower 4 bits are reserved for the media type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - The next three bits may be set to one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x00000000 : Autodetect PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x00000010 : Force 32 bit PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x00000020 : Disable parity detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x00000040 : Force 64 bit PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Default is autodetect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - The next bit can be used to force half-duplex. This is a bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) idea since no known implementations implement half-duplex, and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) in general, half-duplex for gigabit ethernet is a bad idea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x00000080 : Force half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Default is full-duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - In the original driver, the ninth bit could be used to force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) full-duplex. Maintain that for compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x00000200 : Force full-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX_UNITS 8 /* More are supported, limit only on options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* The Hamachi chipset supports 3 parameters each for Rx and Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * interruput management. Parameters will be loaded as specified into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * the TxIntControl and RxIntControl registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * The registers are arranged as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 23 - 16 15 - 8 7 - 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * _________________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * | min_pkt | max_gap | max_latency |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * ---------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * min_pkt : The minimum number of packets processed between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * max_gap : The maximum inter-packet gap in units of 8.192 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * max_latency : The absolute time between interrupts in units of 8.192 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Operational parameters that are set at compile time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Keep the ring sizes a power of two for compile efficiency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) The compiler will convert <unsigned>'%'<2^N> into a bit mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Making the Tx ring too large decreases the effectiveness of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bonding and packet priority.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) There are no ill effects from too-large receive rings, except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) excessive memory usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Empirically it appears that the Tx ring needs to be a little bigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for these Gbit adapters or you get into an overrun condition really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) easily. Also, things appear to work a bit better in back-to-back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) configurations if the Rx ring is 8 times the size of the Tx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TX_RING_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RX_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* #define ADDRLEN 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * RX_CHECKSUM turns on card-generated receive checksum generation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * TCP and UDP packets. Otherwise the upper layers do the calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RX_CHECKSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Operational parameters that usually are not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Time in jiffies before concluding the transmitter is hung. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TX_TIMEOUT (5*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #include <linux/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #include <asm/processor.h> /* Processor type for cache alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) " Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) " Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* IP_MF appears to be only defined in <netinet/ip.h>, however,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) we need it for hardware checksumming support. FYI... some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) the definitions in <netinet/ip.h> conflict/duplicate those in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) other linux headers causing many compiler warnings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifndef IP_MF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Define IP_OFFSET to be IPOPT_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifndef IP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef IPOPT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IP_OFFSET IPOPT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IP_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RUN_AT(x) (jiffies + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifndef ADDRLEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ADDRLEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Condensed bus+endian portability operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #if ADDRLEN == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define cpu_to_leXX(addr) cpu_to_le64(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define leXX_to_cpu(addr) le64_to_cpu(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define cpu_to_leXX(addr) cpu_to_le32(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define leXX_to_cpu(addr) le32_to_cpu(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) Theory of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) I. Board Compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) This device driver is designed for the Packet Engines "Hamachi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 66Mhz PCI card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) II. Board-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) No jumpers exist on the board. The chip supports software correction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) various motherboard wiring errors, however this driver does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) that feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) III. Driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IIIa. Ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) The Hamachi uses a typical descriptor based bus-master architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) The descriptor list is similar to that used by the Digital Tulip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) This driver uses two statically allocated fixed-size descriptor lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) formed into rings by a branch from the final descriptor to the beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) This driver uses a zero-copy receive and transmit scheme similar my other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) network drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) The driver allocates full frame size skbuffs for the Rx ring buffers at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) open() time and passes the skb->data field to the Hamachi as receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) a fresh skbuff is allocated and the frame is copied to the new skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) When the incoming frame is larger, the skbuff is passed directly up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) protocol stack and replaced by a newly allocated skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) The RX_COPYBREAK value is chosen to trade-off the memory wasted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) using a full-sized skbuff for small frames vs. the copying costs of larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) frames. Gigabit cards are typically used on generously configured machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) and the underfilled buffers have negligible impact compared to the benefit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) a single allocation size, so the default value of zero results in never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) copying packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IIIb/c. Transmit/Receive Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) The Rx and Tx descriptor structure are straight-forward, with no historical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) baggage that must be explained. Unlike the awkward DBDMA structure, there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) are no unused fields or option bits that had only one allowable setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) Two details should be noted about the descriptors: The chip supports both 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bit and 64 bit address structures, and the length field is overwritten on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) the receive descriptors. The descriptor length is set in the control word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for each channel. The development driver uses 32 bit addresses only, however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 64 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IIId. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) This driver is very similar to my other network drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) The driver runs as two independent, single-threaded flows of control. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) is the send-packet routine, which enforces single-threaded use by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev->tbusy flag. The other thread is the interrupt handler, which is single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) threaded by the hardware and other software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) The send packet thread has partial control over the Tx ring and 'dev->tbusy'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) queue slot is empty, it clears the tbusy flag when finished otherwise it sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) the 'hmp->tx_full' flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) The interrupt handler has exclusive control over the Rx ring and records stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) from the Tx ring. After reaping the stats, it marks the Tx queue entry as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clears both the tx_full and tbusy flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IV. Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IVb. References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) Hamachi Engineering Design Specification, 5/15/97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (Note: This version was marked "Confidential".)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IVc. Errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) None noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) V. Recent Changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 01/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) to help avoid some stall conditions -- this needs further research.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 01/15/1999 EPK Creation of the hamachi_tx function. This function cleans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) the Tx ring and is called from hamachi_start_xmit (this used to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) called from hamachi_interrupt but it tends to delay execution of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) interrupt handler and thus reduce bandwidth by reducing the latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) between hamachi_rx()'s). Notably, some modification has been made so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) that the cleaning loop checks only to make sure that the DescOwn bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) isn't set in the status flag since the card is not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) to set the entire flag to zero after processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 01/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) checked before attempting to add a buffer to the ring. If the ring is full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) an attempt is made to free any dirty buffers and thus find space for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) the new buffer or the function returns non-zero which should case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) scheduler to reschedule the buffer later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 01/15/1999 EPK Some adjustments were made to the chip initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) End-to-end flow control should now be fully active and the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) algorithm vars have been changed. These could probably use further tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 01/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) set the rx and tx latencies for the Hamachi interrupts. If you're having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) problems with network stalls, try setting these to higher values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) Valid values are 0x00 through 0xff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 01/15/1999 EPK In general, the overall bandwidth has increased and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) latencies are better (sometimes by a factor of 2). Stalls are rare at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) this point, however there still appears to be a bug somewhere between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hardware and driver. TCP checksum errors under load also appear to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) eliminated at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 01/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) Rx and Tx rings. This appears to have been affecting whether a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) peer-to-peer connection would hang under high load. I believe the Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) rings was typically getting set correctly, but the Tx ring wasn't getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) the DescEndRing bit set during initialization. ??? Does this mean the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hamachi card is using the DescEndRing in processing even if a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) slot isn't in use -- hypothetically, the card might be searching the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) entire Tx ring for slots with the DescOwn bit set and then processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) them. If the DescEndRing bit isn't set, then it might just wander off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) through memory until it hits a chunk of data with that bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) and then looping back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 02/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) problem (TxCmd and RxCmd need only to be set when idle or stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 02/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (Michel Mueller pointed out the ``permanently busy'' potential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) problem here).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 02/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 02/23/1999 EPK Verified that the interrupt status field bits for Tx were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) incorrectly defined and corrected (as per Michel Mueller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 02/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) were available before resetting the tbusy and tx_full flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (as per Michel Mueller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 03/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 12/31/1999 KDU Cleaned up assorted things and added Don's code to force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 32 bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 02/20/2000 KDU Some of the control was just plain odd. Cleaned up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) hamachi_start_xmit() and hamachi_interrupt() code. There is still some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) re-structuring I would like to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 03/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) parameters on a dual P3-450 setup yielded the new default interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mitigation parameters. Tx should interrupt VERY infrequently due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) Eric's scheme. Rx should be more often...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 03/13/2000 KDU Added a patch to make the Rx Checksum code interact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) nicely with non-linux machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 03/13/2000 KDU Experimented with some of the configuration values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) -It seems that enabling PCI performance commands for descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) performance impact for any of my tests. (ttcp, netpipe, netperf) I will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) leave them that way until I hear further feedback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) -Increasing the PCI_LATENCY_TIMER to 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) degrade performance. Leaving default at 64 pending further information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 03/14/2000 KDU Further tuning:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) -adjusted boguscnt in hamachi_rx() to depend on interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mitigation parameters chosen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) -Selected a set of interrupt parameters based on some extensive testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) These may change with more testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) TO DO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) -Consider borrowing from the acenic driver code to check PCI_COMMAND for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) -fix the reset procedure. It doesn't quite work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* A few values that may be tweaked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Size of each temporary Rx buffer, calculated as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PKT_BUF_SZ 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* For now, this is going to be set to the maximum size of an ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * packet. Eventually, we may want to make it a variable that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * related to the MTU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MAX_FRAME_SIZE 1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* The rest of these values should never change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void hamachi_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum capability_flags {CanHaveMII=1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 vendor_id, device_id, device_id_mask, pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) void (*media_timer)(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } chip_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Offsets to the Hamachi registers. Various sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum hamachi_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) TxChecksum=0x074, RxChecksum=0x076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) EventStatus=0x08C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* See enum MII_offsets below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AddrMode=0x0D0, StationAddr=0x0D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Gigabit AutoNegotiation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ANLinkPartnerAbility=0x0EA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FIFOcfg=0x0F8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Offsets to the MII-mode registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) enum MII_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MII_Status=0xAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Bits in the interrupt status/mask registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) enum intr_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* The Hamachi Rx and Tx buffer descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct hamachi_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __le32 status_n_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #if ADDRLEN == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Bits in hamachi_desc.status_n_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) enum desc_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DescIntr=0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PRIV_ALIGN 15 /* Required alignment mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MII_CNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct hamachi_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Descriptor rings first for alignment. Tx requires a second descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct hamachi_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct hamachi_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sk_buff* rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct sk_buff* tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct timer_list timer; /* Media selection timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Frequently used and paired value: keep adjacent for cache effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int cur_tx, dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int rx_buf_sz; /* Based on MTU+slack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int tx_full:1; /* The Tx queue is full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int duplex_lock:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int default_port:4; /* Last dev->if_port value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* MII transceiver section. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int mii_cnt; /* MII device addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct mii_if_info mii_if; /* MII lib hooks/info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 rx_int_var, tx_int_var; /* interrupt control variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 option; /* Hold on to a copy of the options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) module_param(max_interrupt_work, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) module_param(mtu, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) module_param(min_rx_pkt, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) module_param(max_rx_gap, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) module_param(max_rx_latency, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) module_param(min_tx_pkt, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) module_param(max_tx_gap, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) module_param(max_tx_latency, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) module_param(rx_copybreak, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) module_param_array(rx_params, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) module_param_array(tx_params, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) module_param_array(options, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) module_param_array(full_duplex, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_param(force32, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int read_eeprom(void __iomem *ioaddr, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int mdio_read(struct net_device *dev, int phy_id, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int hamachi_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void hamachi_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void hamachi_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void hamachi_init_ring(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int hamachi_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline int hamachi_tx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void hamachi_error(struct net_device *dev, int intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int hamachi_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void set_rx_mode(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct ethtool_ops ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct ethtool_ops ethtool_ops_no_mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct net_device_ops hamachi_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ndo_open = hamachi_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .ndo_stop = hamachi_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .ndo_start_xmit = hamachi_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ndo_get_stats = hamachi_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .ndo_set_rx_mode = set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .ndo_tx_timeout = hamachi_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .ndo_do_ioctl = netdev_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int hamachi_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct hamachi_private *hmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int option, i, rx_int_var, tx_int_var, boguscnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int chip_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) void *ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma_addr_t ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* when built into the kernel, we only print version if device is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int printed_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!printed_version++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) printk(version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) base = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef __alpha__ /* Really "64 bit addrs" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) base |= (pci_resource_start(pdev, 1) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) i = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ioaddr = ioremap(base, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto err_out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev = alloc_etherdev(sizeof(struct hamachi_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) : readb(ioaddr + StationAddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #if ! defined(final_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (hamachi_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < 0x10; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) printk("%2.2x%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) spin_lock_init(&hmp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) hmp->mii_if.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) hmp->mii_if.mdio_read = mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hmp->mii_if.mdio_write = mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) hmp->mii_if.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) hmp->mii_if.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!ring_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) goto err_out_cleardev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hmp->tx_ring = ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) hmp->tx_ring_dma = ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!ring_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto err_out_unmap_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hmp->rx_ring = ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hmp->rx_ring_dma = ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Check for options being passed in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) option = card_idx < MAX_UNITS ? options[card_idx] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (dev->mem_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) option = dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* If the bus size is misidentified, do the following. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) force32 = force32 ? force32 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (force32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writeb(force32, ioaddr + VirtualJumpers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Hmmm, do we really need to reset the chip???. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writeb(0x01, ioaddr + ChipReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* After a reset, the clock speed measurement of the PCI bus will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * be valid for a moment. Wait for a little while until it is. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * it takes more than 10ms, forget it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) i = readb(ioaddr + PCIClkMeas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) i = readb(ioaddr + PCIClkMeas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) hmp->base = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) hmp->chip_id = chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) hmp->pci_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* The lower four bits are the media type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (option > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hmp->option = option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (option & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) hmp->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else if (option & 0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hmp->mii_if.full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) hmp->default_port = option & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (hmp->default_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hmp->mii_if.force_media = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hmp->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* lock the duplex mode if someone specified a value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (hmp->mii_if.full_duplex || (option & 0x080))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hmp->duplex_lock = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Set interrupt tuning parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) max_rx_latency = max_rx_latency & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) max_rx_gap = max_rx_gap & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) min_rx_pkt = min_rx_pkt & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) max_tx_latency = max_tx_latency & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) max_tx_gap = max_tx_gap & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) min_tx_pkt = min_tx_pkt & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* The Hamachi-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev->netdev_ops = &hamachi_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev->ethtool_ops = (chip_tbl[hmp->chip_id].flags & CanHaveMII) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ðtool_ops : ðtool_ops_no_mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev->watchdog_timeo = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev->mtu = mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) i = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto err_out_unmap_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ioaddr, dev->dev_addr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) i = readb(ioaddr + PCIClkMeas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "%2.2x, LPA %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) readw(ioaddr + ANLinkPartnerAbility));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int phy, phy_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int mii_status = mdio_read(dev, phy, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (mii_status != 0xffff &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mii_status != 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) hmp->phys[phy_idx++] = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) printk(KERN_INFO "%s: MII PHY found at address %d, status "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "0x%4.4x advertising %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev->name, phy, mii_status, hmp->mii_if.advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hmp->mii_cnt = phy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (hmp->mii_cnt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) hmp->mii_if.phy_id = hmp->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Configure gigabit autonegotiation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) card_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err_out_unmap_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, hmp->rx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) hmp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) err_out_unmap_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, hmp->tx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hmp->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) err_out_cleardev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) free_netdev (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) err_out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int read_eeprom(void __iomem *ioaddr, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int bogus_cnt = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* We should check busy first - per docs -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writew(location, ioaddr + EEAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writeb(0x02, ioaddr + EECmdStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bogus_cnt = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (hamachi_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) printk(" EEPROM status is %2.2x after %d ticks.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return readb(ioaddr + EEData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* MII Managemen Data I/O accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) These routines assume the MDIO controller is idle, and do not exit until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) the command is finished. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int mdio_read(struct net_device *dev, int phy_id, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* We should check busy first - per docs -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) for (i = 10000; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((readw(ioaddr + MII_Status) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) writew((phy_id<<8) + location, ioaddr + MII_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) writew(0x0001, ioaddr + MII_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for (i = 10000; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if ((readw(ioaddr + MII_Status) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return readw(ioaddr + MII_Rd_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* We should check busy first - per docs -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) for (i = 10000; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if ((readw(ioaddr + MII_Status) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writew((phy_id<<8) + location, ioaddr + MII_Addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) writew(value, ioaddr + MII_Wr_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Wait for the command to finish. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (i = 10000; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if ((readw(ioaddr + MII_Status) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int hamachi_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 rx_int_var, tx_int_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u16 fifo_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) i = request_irq(hmp->pci_dev->irq, hamachi_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hamachi_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #if ADDRLEN == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* writellll anyone ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) writel(hmp->rx_ring_dma, ioaddr + RxPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) writel(hmp->tx_ring_dma, ioaddr + TxPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) writel(hmp->rx_ring_dma, ioaddr + RxPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) writel(hmp->tx_ring_dma, ioaddr + TxPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* TODO: It would make sense to organize this as words since the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * documentation does. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Initialize other registers: with so many this eventually this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) converted to an offset/value list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Configure the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) switch (fifo_info){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* No FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writew(0x0000, ioaddr + FIFOcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case 1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Configure the FIFO for 512K external, 16K used for Tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) writew(0x0028, ioaddr + FIFOcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case 2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Configure the FIFO for 1024 external, 32K used for Tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) writew(0x004C, ioaddr + FIFOcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case 3 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Configure the FIFO for 2048 external, 32K used for Tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) writew(0x006C, ioaddr + FIFOcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) printk(KERN_WARNING "%s: Unsupported external memory config!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Default to no FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) writew(0x0000, ioaddr + FIFOcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (dev->if_port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev->if_port = hmp->default_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* Setting the Rx mode will start the Rx process. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* If someone didn't choose a duplex, default to full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (hmp->duplex_lock != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) hmp->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* always 1, takes no more time to do it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) writew(0x0001, ioaddr + RxChecksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) writew(0x0000, ioaddr + TxChecksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) writew(0x215F, ioaddr + MACCnfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) writew(0x000C, ioaddr + FrameGap0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writew(0x1018, ioaddr + FrameGap1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Why do we enable receives/transmits here? -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Enable automatic generation of flow control frames, period 0xffff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel(0x0030FFFF, ioaddr + FlowCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Enable legacy links. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Initial Link LED to blinking red. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) writeb(0x03, ioaddr + LEDCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Configure interrupt mitigation. This has a great effect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) performance, so systems tuning should start here!. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rx_int_var = hmp->rx_int_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) tx_int_var = hmp->tx_int_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (hamachi_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (tx_int_var & 0x00ff0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (rx_int_var & 0x00ff0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) writel(tx_int_var, ioaddr + TxIntrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) writel(rx_int_var, ioaddr + RxIntrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Enable interrupts by setting the interrupt mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) writel(0x80878787, ioaddr + InterruptEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Configure and start the DMA channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Burst sizes are in the low three bits: size = 4<<(val&7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #if ADDRLEN == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) writew(0x005D, ioaddr + TxDMACtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) writew(0x001D, ioaddr + RxDMACtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) writew(0x001D, ioaddr + TxDMACtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) writew(0x0001, ioaddr + RxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (hamachi_debug > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Set the timer to check for link beat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) timer_setup(&hmp->timer, hamachi_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) add_timer(&hmp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static inline int hamachi_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Update the dirty pointer until we find an entry that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) still owned by the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int entry = hmp->dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Free the original skb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) skb = hmp->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) leXX_to_cpu(hmp->tx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) hmp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) hmp->tx_ring[entry].status_n_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (entry >= TX_RING_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) cpu_to_le32(DescEndRing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void hamachi_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct hamachi_private *hmp = from_timer(hmp, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct net_device *dev = hmp->mii_if.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int next_tick = 10*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (hamachi_debug > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) readw(ioaddr + ANLinkPartnerAbility));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "%4.4x %4.4x %4.4x.\n", dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) readw(ioaddr + 0x0e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) readw(ioaddr + 0x0e2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) readw(ioaddr + 0x0e4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) readw(ioaddr + 0x0e6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) readw(ioaddr + 0x0e8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) readw(ioaddr + 0x0eA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* We could do something here... nah. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) hmp->timer.expires = RUN_AT(next_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) add_timer(&hmp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static void hamachi_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) for (i = 0; i < RX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) printk(KERN_CONT " %8.8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) le32_to_cpu(hmp->rx_ring[i].status_n_length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) printk(KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) printk(KERN_CONT " %4.4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) le32_to_cpu(hmp->tx_ring[i].status_n_length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Reinit the hardware and make sure the Rx and Tx processes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) are up and running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev->if_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* The right way to do Reset. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * -Clear OWN bit in all Rx/Tx descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * -Wait 50 uS for channels to go idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * -Turn off MAC receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * -Issue Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) for (i = 0; i < RX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Presume that all packets in the Tx queue are gone if we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * re-init the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) for (i = 0; i < TX_RING_SIZE; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (i >= TX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) hmp->tx_ring[i].status_n_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) cpu_to_le32(DescEndRing) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (hmp->tx_ring[i].status_n_length &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) cpu_to_le32(0x0000ffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) skb = hmp->tx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (skb){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) leXX_to_cpu(hmp->tx_ring[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) hmp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) udelay(60); /* Sleep 60 us just for safety sake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) hmp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) hmp->cur_rx = hmp->cur_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) hmp->dirty_rx = hmp->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Rx packets are also presumed lost; however, we need to make sure a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * ring of buffers is in tact. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) for (i = 0; i < RX_RING_SIZE; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct sk_buff *skb = hmp->rx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (skb){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) leXX_to_cpu(hmp->rx_ring[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) hmp->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) hmp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Fill in the Rx buffers. Handle allocation failure gracefully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) skb = netdev_alloc_skb_ip_align(dev, hmp->rx_buf_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) hmp->rx_skbuff[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) hmp->rx_ring[i].addr = cpu_to_leXX(dma_map_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) DMA_FROM_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Mark the last entry as wrapping the ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Trigger an immediate transmit demand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Restart the chip's Tx/Rx processes . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) writew(0x0001, ioaddr + TxCmd); /* START Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) writew(0x0001, ioaddr + RxCmd); /* START Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static void hamachi_init_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) hmp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) hmp->cur_rx = hmp->cur_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) hmp->dirty_rx = hmp->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * card needs room to do 8 byte alignment, +2 so we can reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * the first 2 bytes, and +16 gets room for the status word from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * card. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) (((dev->mtu+26+7) & ~7) + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Initialize all Rx descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) hmp->rx_ring[i].status_n_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) hmp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Fill in the Rx buffers. Handle allocation failure gracefully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) hmp->rx_skbuff[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) skb_reserve(skb, 2); /* 16 byte align the IP header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) hmp->rx_ring[i].addr = cpu_to_leXX(dma_map_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) DMA_FROM_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) hmp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) hmp->tx_ring[i].status_n_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Mark the last entry of the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) unsigned entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Ok, now make sure that the queue has space before trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) add another skbuff. if we return non-zero the scheduler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) should interpret this as a queue full and requeue the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (hmp->tx_full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* We should NEVER reach this point -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Wake the potentially-idle transmit channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* If we don't need to read status, DON'T -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) status=readw(hmp->base + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if( !(status & 0x0001) || (status & 0x0002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) writew(0x0001, hmp->base + TxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* Caution: the write order is important here, set the field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) with the "ownership" bits last. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Calculate the next Tx descriptor entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) entry = hmp->cur_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) hmp->tx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) hmp->tx_ring[entry].addr = cpu_to_leXX(dma_map_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DMA_TO_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* Hmmmm, could probably put a DescIntr on these, but the way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) the driver is currently coded makes Tx interrupts unnecessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) since the clearing of the Tx ring is handled by the start_xmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) routine. This organization helps mitigate the interrupts a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) bit and probably renders the max_tx_latency param useless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) Update: Putting a DescIntr bit on all of the descriptors and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (entry >= TX_RING_SIZE-1) /* Wrap ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) DescEndPacket | DescEndRing | DescIntr | skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) DescEndPacket | DescIntr | skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) hmp->cur_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Non-x86 Todo: explicitly flush cache lines here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Wake the potentially-idle transmit channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* If we don't need to read status, DON'T -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) status=readw(hmp->base + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if( !(status & 0x0001) || (status & 0x0002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) writew(0x0001, hmp->base + TxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Immediately before returning, let's clear as many entries as we can. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) hamachi_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* We should kick the bottom half here, since we are not accepting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * interrupts with every packet. i.e. realize that Gigabit ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * can transmit faster than ordinary machines can load packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * hence, any packet that got put off because we were in the transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * routine should IMMEDIATELY get a chance to be re-queued. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) netif_wake_queue(dev); /* Typical path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) hmp->tx_full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (hamachi_debug > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev->name, hmp->cur_tx, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* The interrupt handler does all of the Rx thread work and cleans up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) after the Tx thread. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct net_device *dev = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) long boguscnt = max_interrupt_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #ifndef final_version /* Can never occur. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) spin_lock(&hmp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) u32 intr_status = readl(ioaddr + InterruptClear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (hamachi_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev->name, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (intr_status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (intr_status & IntrRxDone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) hamachi_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (intr_status & IntrTxDone){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* This code should RARELY need to execute. After all, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * a gigabit link, it should consume packets as fast as we put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * them in AND we clear the Tx ring in hamachi_start_xmit().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (hmp->tx_full){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int entry = hmp->dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) skb = hmp->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* Free the original skb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (skb){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) leXX_to_cpu(hmp->tx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) hmp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) hmp->tx_ring[entry].status_n_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (entry >= TX_RING_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) cpu_to_le32(DescEndRing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* The ring is no longer full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) hmp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Abnormal error summary/uncommon events handlers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (intr_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) LinkChange | NegotiationChange | StatsMax))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) hamachi_error(dev, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (--boguscnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev->name, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (hamachi_debug > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev->name, readl(ioaddr + IntrStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #ifndef final_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Code that should never be run! Perhaps remove after testing.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int stopit = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (dev->start == 0 && --stopit < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) free_irq(irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) spin_unlock(&hmp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* This routine is logically part of the interrupt handler, but separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) for clarity and better register allocation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int hamachi_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int entry = hmp->cur_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (hamachi_debug > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) entry, hmp->rx_ring[entry].status_n_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* If EOP is set on the next entry, it's a new packet. Send it up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) u32 desc_status = le32_to_cpu(desc->status_n_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u16 data_size = desc_status; /* Implicit truncate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u8 *buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) s32 frame_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (desc_status & DescOwn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dma_sync_single_for_cpu(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) leXX_to_cpu(desc->addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) hmp->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (hamachi_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) frame_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (--boguscnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if ( ! (desc_status & DescEndPacket)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) "multiple buffers, entry %#x length %d status %4.4x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev->name, hmp->cur_rx, data_size, desc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) } /* else Omit for prototype errata??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (frame_status & 0x00380000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* There was an error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (hamachi_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) frame_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (frame_status & 0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (frame_status & 0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (frame_status & 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (frame_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Omit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u16 pkt_len = (frame_status & 0x07ff) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #ifdef RX_CHECKSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u32 pfck = *(u32 *) &buf_addr[data_size - 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #ifndef final_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (hamachi_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) " of %d, bogus_cnt %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pkt_len, data_size, boguscnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (hamachi_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) *(s32*)&(buf_addr[data_size - 20]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) *(s32*)&(buf_addr[data_size - 16]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) *(s32*)&(buf_addr[data_size - 12]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) *(s32*)&(buf_addr[data_size - 8]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) *(s32*)&(buf_addr[data_size - 4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Check if the packet is long enough to accept without copying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) to a minimally-sized skbuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (pkt_len < rx_copybreak &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #ifdef RX_CHECKSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) printk(KERN_ERR "%s: rx_copybreak non-zero "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) "not good with RX_CHECKSUM\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) skb_reserve(skb, 2); /* 16 byte align the IP header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dma_sync_single_for_cpu(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) leXX_to_cpu(hmp->rx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Call copy + cksum if available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #if 1 || USE_IP_COPYSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) skb_copy_to_linear_data(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) hmp->rx_skbuff[entry]->data, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) skb_put_data(skb, hmp->rx_ring_dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) + entry*sizeof(*desc), pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dma_sync_single_for_device(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) leXX_to_cpu(hmp->rx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) leXX_to_cpu(hmp->rx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) hmp->rx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #ifdef RX_CHECKSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* TCP or UDP on ipv4, DIX encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct iphdr *ih = (struct iphdr *) skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* Check that IP packet is at least 46 bytes, otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * there may be pad bytes included in the hardware checksum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * This wouldn't happen if everyone padded with 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ntohs(ih->tot_len) >= 46){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* don't worry about frags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u32 inv = *(u32 *) &buf_addr[data_size - 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u32 *p = (u32 *) &buf_addr[data_size - 20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) register u32 crc, p_r, p_r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (inv & 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) inv &= ~4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) --p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) p_r = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) p_r1 = *(p-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) switch (inv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) crc = (p_r & 0xffff) + (p_r >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) crc = (p_r >> 16) + (p_r & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) + (p_r1 >> 16 & 0xff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) crc = p_r + (p_r1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) default: /*NOTREACHED*/ crc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (crc & 0xffff0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) crc &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ++crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* tcp/udp will add in pseudo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) skb->csum = ntohs(pfck & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (skb->csum > crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) skb->csum -= crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) skb->csum += (~crc & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * could do the pseudo myself and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * CHECKSUM_UNNECESSARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #endif /* RX_CHECKSUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) entry = (++hmp->cur_rx) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* Refill the Rx ring buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct hamachi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) entry = hmp->dirty_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) desc = &(hmp->rx_ring[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (hmp->rx_skbuff[entry] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) hmp->rx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) break; /* Better luck next round. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) desc->addr = cpu_to_leXX(dma_map_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) hmp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) DMA_FROM_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (entry >= RX_RING_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) desc->status_n_length |= cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) DescEndPacket | DescEndRing | DescIntr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) desc->status_n_length |= cpu_to_le32(DescOwn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) DescEndPacket | DescIntr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* Restart Rx engine if stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* If we don't need to check status, don't. -KDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (readw(hmp->base + RxStatus) & 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) writew(0x0001, hmp->base + RxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* This is more properly named "uncommon interrupt events", as it covers more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) than just errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static void hamachi_error(struct net_device *dev, int intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (intr_status & (LinkChange|NegotiationChange)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (hamachi_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) readw(ioaddr + ANLinkPartnerAbility),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) readl(ioaddr + IntrStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (readw(ioaddr + ANStatus) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) writeb(0x01, ioaddr + LEDCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) writeb(0x03, ioaddr + LEDCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (intr_status & StatsMax) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) hamachi_get_stats(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* Read the overflow bits to clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) readl(ioaddr + 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) readl(ioaddr + 0x3F0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) hamachi_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev->name, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* Hmmmmm, it's not clear how to recover from PCI faults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int hamachi_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (hamachi_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dev->name, readw(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* Disable interrupts by clearing the interrupt mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) writel(0x0000, ioaddr + InterruptEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* Stop the chip's Tx and Rx processes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) writel(2, ioaddr + RxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) writew(2, ioaddr + TxCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #ifdef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (hamachi_debug > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) printk(KERN_DEBUG " Tx ring at %8.8x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (int)hmp->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) printk(KERN_DEBUG " Rx ring %8.8x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) (int)hmp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (hamachi_debug > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) u16 *addr = (u16 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) hmp->rx_skbuff[i]->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) printk(KERN_DEBUG "Addr: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) for (j = 0; j < 0x50; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) printk(" %4.4x", addr[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #endif /* __i386__ debugging only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) free_irq(hmp->pci_dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) del_timer_sync(&hmp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* Free all the skbuffs in the Rx queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) skb = hmp->rx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) hmp->rx_ring[i].status_n_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) leXX_to_cpu(hmp->rx_ring[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) hmp->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) hmp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) skb = hmp->tx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dma_unmap_single(&hmp->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) leXX_to_cpu(hmp->tx_ring[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) hmp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) writeb(0x00, ioaddr + LEDCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* We should lock this segment of code for SMP eventually, although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) the vulnerability window is very small and statistics are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) non-critical. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* Ok, what goes here? This appears to be stuck at 21 packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) according to ifconfig. It does get incremented in hamachi_tx(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) so I think I'll comment it out here and see if better things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /* dev->stats.tx_packets = readl(ioaddr + 0x000); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* Total Uni+Brd+Multi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev->stats.rx_bytes = readl(ioaddr + 0x330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* Total Uni+Brd+Multi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev->stats.tx_bytes = readl(ioaddr + 0x3B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Multicast Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dev->stats.multicast = readl(ioaddr + 0x320);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* Over+Undersized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) dev->stats.rx_length_errors = readl(ioaddr + 0x368);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) dev->stats.rx_over_errors = readl(ioaddr + 0x35C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev->stats.rx_crc_errors = readl(ioaddr + 0x360);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* Symbol Errs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev->stats.rx_frame_errors = readl(ioaddr + 0x364);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* Dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) dev->stats.rx_missed_errors = readl(ioaddr + 0x36C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static void set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) void __iomem *ioaddr = hmp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) writew(0x000F, ioaddr + AddrMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) } else if ((netdev_mc_count(dev) > 63) || (dev->flags & IFF_ALLMULTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* Too many to match, or accept all multicasts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) writew(0x000B, ioaddr + AddrMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) } else if (!netdev_mc_empty(dev)) { /* Must use the CAM filter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) writel(*(u32 *)(ha->addr), ioaddr + 0x100 + i*8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) writel(0x20000 | (*(u16 *)&ha->addr[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ioaddr + 0x104 + i*8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* Clear remaining entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) for (; i < 64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) writel(0, ioaddr + 0x104 + i*8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) writew(0x0003, ioaddr + AddrMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) } else { /* Normal, unicast/broadcast-only mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) writew(0x0001, ioaddr + AddrMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static int check_if_running(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static int hamachi_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) mii_ethtool_get_link_ksettings(&np->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static int hamachi_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) res = mii_ethtool_set_link_ksettings(&np->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static int hamachi_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return mii_nway_restart(&np->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static u32 hamachi_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return mii_link_ok(&np->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static const struct ethtool_ops ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .begin = check_if_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .get_drvinfo = hamachi_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .nway_reset = hamachi_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .get_link = hamachi_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .get_link_ksettings = hamachi_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .set_link_ksettings = hamachi_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) static const struct ethtool_ops ethtool_ops_no_mii = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .begin = check_if_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .get_drvinfo = hamachi_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct hamachi_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct mii_ioctl_data *data = if_mii(rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) u32 *d = (u32 *)&rq->ifr_ifru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* Should add this check here or an ordinary user can do nasty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * things. -KDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * TODO: Shut down the Rx and Tx engines while doing this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) writel(d[0], np->base + TxIntrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) writel(d[1], np->base + RxIntrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) (u32) readl(np->base + TxIntrCtrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) (u32) readl(np->base + RxIntrCtrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static void hamachi_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) struct net_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) struct hamachi_private *hmp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, hmp->rx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) hmp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, hmp->tx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) hmp->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) iounmap(hmp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const struct pci_device_id hamachi_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static struct pci_driver hamachi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .id_table = hamachi_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .probe = hamachi_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .remove = hamachi_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static int __init hamachi_init (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* when a module, this is printed whether or not devices are found in probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) printk(version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return pci_register_driver(&hamachi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static void __exit hamachi_exit (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pci_unregister_driver(&hamachi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) module_init(hamachi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) module_exit(hamachi_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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