^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2002-2010 Exar Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Drivers based on or derived from this code fall under the GPL and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * retain the authorship, copyright and license notice. This file is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a complete program and may only be used when the entire operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * system is licensed under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * See the file COPYING in this distribution for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _S2IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _S2IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TBD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define s2BIT(loc) (0x8000000000000000ULL >> (loc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #undef SUCCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FAILURE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S2IO_BIT_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S2IO_BIT_SET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CHECKBIT(value, nbit) (value & (1 << nbit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Maximum time to flicker LED when asked to identify NIC using ethtool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_FLICKER_TIME 60000 /* 60 Secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Maximum outstanding splits to be configured into xena. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) XENA_ONE_SPLIT_TRANSACTION = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) XENA_TWO_SPLIT_TRANSACTION = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) XENA_THREE_SPLIT_TRANSACTION = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) XENA_FOUR_SPLIT_TRANSACTION = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) XENA_EIGHT_SPLIT_TRANSACTION = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) XENA_TWELVE_SPLIT_TRANSACTION = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* OS concerned variables and constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WATCH_DOG_TIMEOUT 15*HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EFILL 0x1234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ALIGN_SIZE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCIX_COMMAND_REGISTER 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Debug related variables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* different debug levels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ERR_DBG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INIT_DBG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INFO_DBG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TX_DBG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INTR_DBG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Global variable that defines the present debug level of the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int debug_level = ERR_DBG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* DEBUG message print. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DBG_PRINT(dbg_level, fmt, args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (dbg_level <= debug_level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_info(fmt, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Protocol assist features of the NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define L3_CKSUM_OK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define L4_CKSUM_OK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S2IO_JUMBO_SIZE 9600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Driver statistics maintained by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct swStat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long long single_ecc_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long long double_ecc_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long long parity_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long long serious_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long long soft_reset_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long long fifo_full_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long long ring_full_cnt[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* LRO statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long long clubbed_frms_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long long sending_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long long outof_sequence_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long long flush_max_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long long sum_avg_pkts_aggregated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long long num_aggregations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Other statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long long mem_alloc_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long long pci_map_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long long watchdog_timer_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long long mem_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long long mem_freed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long long link_up_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long long link_down_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long long link_up_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long long link_down_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Transfer Code statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long long tx_buf_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long long tx_desc_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long long tx_parity_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long long tx_link_loss_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long long tx_list_proc_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long long rx_parity_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long long rx_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long long rx_parity_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long long rx_rda_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long long rx_unkn_prot_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long long rx_fcs_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long long rx_buf_size_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long long rx_rxd_corrupt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long long rx_unkn_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Error/alarm statistics*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long long tda_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long long pfc_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long long pcc_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long long tti_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long long lso_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long long tpa_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long long sm_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long long mac_tmac_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long long mac_rmac_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long long xgxs_txgxs_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long long xgxs_rxgxs_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long long rc_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long long prc_pcix_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long long rpa_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long long rda_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long long rti_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long long mc_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Xpak releated alarm and warnings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct xpakStat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u64 alarm_transceiver_temp_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 alarm_transceiver_temp_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 alarm_laser_bias_current_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u64 alarm_laser_bias_current_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 alarm_laser_output_power_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u64 alarm_laser_output_power_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u64 warn_transceiver_temp_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u64 warn_transceiver_temp_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 warn_laser_bias_current_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 warn_laser_bias_current_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u64 warn_laser_output_power_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 warn_laser_output_power_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u64 xpak_regs_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 xpak_timer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* The statistics block of Xena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct stat_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Tx MAC statistics counters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le32 tmac_data_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __le32 tmac_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __le64 tmac_drop_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __le32 tmac_bcst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __le32 tmac_mcst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __le64 tmac_pause_ctrl_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __le32 tmac_ucst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __le32 tmac_ttl_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __le32 tmac_any_err_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le32 tmac_nucst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le64 tmac_ttl_less_fb_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __le64 tmac_vld_ip_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __le32 tmac_drop_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __le32 tmac_vld_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __le32 tmac_rst_tcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le32 tmac_icmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __le64 tmac_tcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __le32 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le32 tmac_udp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Rx MAC Statistics counters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le32 rmac_data_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le32 rmac_vld_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __le64 rmac_fcs_err_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __le64 rmac_drop_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le32 rmac_vld_bcst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le32 rmac_vld_mcst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __le32 rmac_out_rng_len_err_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __le32 rmac_in_rng_len_err_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __le64 rmac_long_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le64 rmac_pause_ctrl_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le64 rmac_unsup_ctrl_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 rmac_accepted_ucst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le32 rmac_ttl_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le32 rmac_discarded_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 rmac_accepted_nucst_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __le32 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __le32 rmac_drop_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __le64 rmac_ttl_less_fb_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __le64 rmac_ttl_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __le64 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 rmac_usized_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __le32 reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __le32 rmac_frag_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __le32 rmac_osized_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __le32 reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __le32 rmac_jabber_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __le64 rmac_ttl_64_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le64 rmac_ttl_65_127_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le64 reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __le64 rmac_ttl_128_255_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le64 rmac_ttl_256_511_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le64 reserved_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __le64 rmac_ttl_512_1023_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __le64 rmac_ttl_1024_1518_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __le32 rmac_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __le32 reserved_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le64 rmac_ip_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __le32 rmac_drop_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __le32 rmac_hdr_err_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le32 reserved_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __le32 rmac_icmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __le64 rmac_tcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __le32 rmac_err_drp_udp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le32 rmac_udp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __le64 rmac_xgmii_err_sym;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __le64 rmac_frms_q0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __le64 rmac_frms_q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __le64 rmac_frms_q2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __le64 rmac_frms_q3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __le64 rmac_frms_q4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __le64 rmac_frms_q5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __le64 rmac_frms_q6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __le64 rmac_frms_q7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __le16 rmac_full_q3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le16 rmac_full_q2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __le16 rmac_full_q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __le16 rmac_full_q0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __le16 rmac_full_q7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __le16 rmac_full_q6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __le16 rmac_full_q5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __le16 rmac_full_q4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __le32 reserved_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __le32 rmac_pause_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __le64 rmac_xgmii_data_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __le64 rmac_xgmii_ctrl_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __le32 rmac_err_tcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __le32 rmac_accepted_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* PCI/PCI-X Read transaction statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __le32 new_rd_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __le32 rd_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __le32 rd_rtry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __le32 new_rd_req_rtry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* PCI/PCI-X Write/Read transaction statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __le32 wr_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __le32 wr_rtry_rd_ack_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __le32 new_wr_req_rtry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le32 new_wr_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __le32 wr_disc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __le32 wr_rtry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PCI/PCI-X Write / DMA Transaction statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __le32 txp_wr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __le32 rd_rtry_wr_ack_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __le32 txd_wr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 txd_rd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le32 rxd_wr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le32 rxd_rd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le32 rxf_wr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __le32 txf_rd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Tx MAC statistics overflow counters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __le32 tmac_data_octets_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __le32 tmac_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le32 tmac_bcst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __le32 tmac_mcst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __le32 tmac_ucst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __le32 tmac_ttl_octets_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le32 tmac_any_err_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 tmac_nucst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __le64 tmac_vlan_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __le32 tmac_drop_ip_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le32 tmac_vld_ip_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __le32 tmac_rst_tcp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __le32 tmac_icmp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __le32 tpa_unknown_protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __le32 tmac_udp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __le32 reserved_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __le32 tpa_parse_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Rx MAC Statistics overflow counters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __le32 rmac_data_octets_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le32 rmac_vld_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le32 rmac_vld_bcst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __le32 rmac_vld_mcst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __le32 rmac_accepted_ucst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) __le32 rmac_ttl_octets_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __le32 rmac_discarded_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __le32 rmac_accepted_nucst_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __le32 rmac_usized_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) __le32 rmac_drop_events_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __le32 rmac_frag_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __le32 rmac_osized_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __le32 rmac_ip_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __le32 rmac_jabber_frms_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __le32 rmac_icmp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __le32 rmac_drop_ip_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __le32 rmac_err_drp_udp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) __le32 rmac_udp_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __le32 reserved_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __le32 rmac_pause_cnt_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __le64 rmac_ttl_1519_4095_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __le64 rmac_ttl_4096_8191_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __le64 rmac_ttl_8192_max_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __le64 rmac_ttl_gt_max_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __le64 rmac_osized_alt_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __le64 rmac_jabber_alt_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __le64 rmac_gt_max_alt_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le64 rmac_vlan_frms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __le32 rmac_len_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __le32 rmac_fcs_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __le32 rmac_pf_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __le32 rmac_da_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __le32 rmac_red_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __le32 rmac_rts_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __le32 reserved_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __le32 rmac_ingm_full_discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __le32 reserved_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __le32 rmac_accepted_ip_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __le32 reserved_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __le32 link_fault_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 buffer[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct swStat sw_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct xpakStat xpak_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Default value for 'vlan_strip_tag' configuration parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define NO_STRIP_IN_PROMISC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Structures representing different init time configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * parameters of the NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MAX_TX_FIFOS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MAX_RX_RINGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define FIFO_DEFAULT_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FIFO_OTHER_MAX_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* FIFO mappings for all possible number of fifos configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const int fifo_map[][MAX_TX_FIFOS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0, 0, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0, 0, 0, 0, 1, 1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0, 0, 0, 1, 1, 1, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0, 0, 1, 1, 2, 2, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0, 0, 1, 1, 2, 2, 3, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0, 0, 1, 1, 2, 3, 4, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0, 0, 1, 2, 3, 4, 5, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0, 1, 2, 3, 4, 5, 6, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Maintains Per FIFO related information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct tx_fifo_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MAX_AVAILABLE_TXDS 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 fifo_len; /* specifies len of FIFO up to 8192, ie no of TxDLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Priority definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TX_FIFO_PRI_0 0 /*Highest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TX_FIFO_PRI_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TX_FIFO_PRI_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TX_FIFO_PRI_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TX_FIFO_PRI_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TX_FIFO_PRI_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TX_FIFO_PRI_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TX_FIFO_PRI_7 7 /*lowest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 fifo_priority; /* specifies pointer level for FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* user should not set twos fifos with same pri */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 f_no_snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define NO_SNOOP_TXD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define NO_SNOOP_TXD_BUFFER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Maintains per Ring related information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct rx_ring_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 num_rxd; /*No of RxDs per Rx Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RX_RING_PRI_0 0 /* highest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RX_RING_PRI_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RX_RING_PRI_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RX_RING_PRI_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define RX_RING_PRI_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define RX_RING_PRI_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define RX_RING_PRI_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define RX_RING_PRI_7 7 /* lowest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 ring_priority; /*Specifies service priority of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* OSM should not set any two rings with same priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 ring_org; /*Organization of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RING_ORG_BUFF1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define RX_RING_ORG_BUFF3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define RX_RING_ORG_BUFF5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 f_no_snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define NO_SNOOP_RXD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define NO_SNOOP_RXD_BUFFER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* This structure provides contains values of the tunable parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * of the H/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct config_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Tx Side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 tx_fifo_num; /*Number of Tx FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* 0-No steering, 1-Priority steering, 2-Default fifo map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define NO_STEERING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define TX_PRIORITY_STEERING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TX_DEFAULT_STEERING 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 tx_steering_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 fifo_mapping[MAX_TX_FIFOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u64 tx_intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define INTA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MSI_X 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Rx Side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 rx_ring_num; /*Number of receive rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MAX_RX_BLOCKS_PER_RING 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HEADER_ETHERNET_II_802_3_SIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define HEADER_802_2_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define HEADER_SNAP_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HEADER_VLAN_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MIN_MTU 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MAX_PYLD 1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MAX_MTU (MAX_PYLD+18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MAX_MTU_VLAN (MAX_PYLD+22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MAX_PYLD_JUMBO 9600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u16 bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int max_mc_addr; /* xena=64 herc=256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int max_mac_addr; /* xena=16 herc=64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int mc_start_offset; /* xena=16 herc=64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 multiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Structure representing MAC Addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct mac_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Structure that represent every FIFO element in the BAR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Address location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct TxFIFO_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u64 TxDL_Pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u64 List_Control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TX_FIFO_FIRST_LIST s2BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TX_FIFO_LAST_LIST s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TX_FIFO_SPECIAL_FUNC s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define TX_FIFO_DS_NO_SNOOP s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Tx descriptor structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct TxD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 Control_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define TXD_LIST_OWN_XENA s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define TXD_GATHER_CODE_FIRST s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TXD_GATHER_CODE_LAST s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define TXD_TCP_LSO_EN s2BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TXD_UDP_COF_EN s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define TXD_UFO_EN s2BIT(31) | s2BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define TXD_UFO_MSS(val) vBIT(val,34,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u64 Control_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define TXD_TX_CKO_IPV4_EN s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define TXD_TX_CKO_TCP_EN s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TXD_TX_CKO_UDP_EN s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define TXD_VLAN_ENABLE s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define TXD_VLAN_TAG(val) vBIT(val,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define TXD_INT_NUMBER(val) vBIT(val,34,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define TXD_INT_TYPE_PER_LIST s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define TXD_INT_TYPE_UTILZ s2BIT(46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define TXD_SET_MARKER vBIT(0x6,0,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u64 Buffer_Pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u64 Host_Control; /* reserved for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Structure to hold the phy and virt addr of every TxDL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct list_info_hold {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dma_addr_t list_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void *list_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Rx descriptor structure for 1 buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct RxD_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u64 Host_Control; /* reserved for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u64 Control_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define RXD_OWN_XENA s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define RXD_FRAME_VLAN_TAG s2BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define RXD_FRAME_PROTO_IPV4 s2BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define RXD_FRAME_PROTO_IPV6 s2BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define RXD_FRAME_IP_FRAG s2BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define RXD_FRAME_PROTO_TCP s2BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define RXD_FRAME_PROTO_UDP s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u64 Control_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define THE_RXD_MARK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SET_VLAN_TAG(val) vBIT(val,48,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SET_NUM_TAG(val) vBIT(val,16,32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Rx descriptor structure for 1 buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct RxD1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct RxD_t h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u64 Buffer0_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Rx descriptor structure for 3 or 2 buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct RxD3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct RxD_t h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define BUF0_LEN 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define BUF1_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u64 Buffer0_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u64 Buffer1_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u64 Buffer2_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Structure that represents the Rx descriptor block which contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * 128 Rx descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct RxD_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MAX_RXDS_PER_BLOCK_1 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u64 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Rxd in this blk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * the upper 32 bits should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SIZE_OF_BLOCK 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define RXD_MODE_1 0 /* One Buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define RXD_MODE_3B 1 /* Two Buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Structure to hold virtual addresses of Buf0 and Buf1 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * 2buf mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct buffAdd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void *ba_0_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void *ba_1_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) void *ba_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) void *ba_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Structure which stores all the MAC control parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* This structure stores the offset of the RxD in the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * from which the Rx Interrupt processor can start picking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * up the RxDs for processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct rx_curr_get_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 block_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 ring_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct rx_curr_put_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 block_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 ring_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* This structure stores the offset of the TxDl in the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * from which the Tx Interrupt processor can start picking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * up the TxDLs for send complete interrupt processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct tx_curr_get_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct tx_curr_put_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct rxd_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) void *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Structure that holds the Phy and virt addresses of the Blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct rx_block_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void *block_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dma_addr_t block_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct rxd_info *rxds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Data structure to represent a LRO session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct lro {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct sk_buff *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct sk_buff *last_frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 *l2h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct iphdr *iph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct tcphdr *tcph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 tcp_next_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __be32 tcp_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int frags_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int sg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __be16 window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u16 vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 cur_tsval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __be32 cur_tsecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 saw_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Ring specific structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* The ring number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int ring_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* per-ring buffer counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 rx_bufs_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define MAX_LRO_SESSIONS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct lro lro0_n[MAX_LRO_SESSIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u8 lro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* copy of sp->rxd_mode flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int rxd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Number of rxds per block for the rxd_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int rxd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* copy of sp pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct s2io_nic *nic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* copy of sp->dev pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* copy of sp->pdev pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Per ring napi struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned long interrupt_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * Place holders for the virtual and physical addresses of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * all the Rx Blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int pkt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * Put pointer info which indictes which RxD has to be replenished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * with a new buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct rx_curr_put_info rx_curr_put_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * Get pointer info which indictes which is the last RxD that was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * processed by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct rx_curr_get_info rx_curr_get_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* interface MTU value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Buffer Address store. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct buffAdd **ba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Fifo specific structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct fifo_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* FIFO number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int fifo_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Maximum TxDs per TxDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int max_txds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Place holder of all the TX List's Phy and Virt addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct list_info_hold *list_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Current offset within the tx FIFO where driver would write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * new Tx frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct tx_curr_put_info tx_curr_put_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Current offset within tx FIFO from where the driver would start freeing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * the buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct tx_curr_get_info tx_curr_get_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define FIFO_QUEUE_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define FIFO_QUEUE_STOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int queue_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* copy of sp->dev pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* copy of multiq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 multiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Per fifo lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spinlock_t tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Per fifo UFO in band structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u64 *ufo_in_band_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct s2io_nic *nic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Information related to the Tx and Rx FIFOs and Rings of Xena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * is maintained in this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct mac_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* tx side stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* logical pointer of start of each Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Fifo specific structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct fifo_info fifos[MAX_TX_FIFOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Save virtual address of TxD page with zero DMA addr(if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void *zerodma_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* rx side stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Ring specific structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct ring_info rings[MAX_RX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u16 rmac_pause_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u16 mc_pause_threshold_q0q3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u16 mc_pause_threshold_q4q7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void *stats_mem; /* orignal pointer to allocated mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dma_addr_t stats_mem_phy; /* Physical address of the stat block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 stats_mem_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct stat_block *stats_info; /* Logical address of the stat block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Default Tunable parameters of the NIC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DEFAULT_FIFO_0_LEN 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DEFAULT_FIFO_1_7_LEN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SMALL_BLK_CNT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define LARGE_BLK_CNT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * Structure to keep track of the MSI-X vectors and the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * argument registered against each vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MAX_REQUESTED_MSI_X 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct s2io_msix_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u16 vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u16 entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) void *arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MSIX_ALARM_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MSIX_RING_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MSIX_REGISTERED_SUCCESS 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct msix_info_st {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* These flags represent the devices temporary state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) enum s2io_device_state_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __S2IO_STATE_LINK_TASK=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __S2IO_STATE_CARD_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Structure representing one instance of the NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct s2io_nic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int rxd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Count of packets to be processed in a given iteration, it will be indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * by the quota field of the device structure when NAPI is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int pkts_to_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct mac_info mac_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct config_param config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) void __iomem *bar0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) void __iomem *bar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define MAX_MAC_SUPPORTED 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct mac_addr def_mac_addr[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct net_device_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int high_dma_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int device_enabled_once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) char name[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* Timer that handles I/O errors/exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct timer_list alarm_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Space to back up the PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 config_space[256 / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define PROMISC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define ALL_MULTI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MAX_ADDRS_SUPPORTED 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u16 mc_addr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u16 m_cast_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u16 all_multi_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u16 promisc_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Restart timer, used to restart NIC if the device is stuck and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * a schedule task that will set the correct Link state once the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * NIC's PHY has stabilized after a state change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct work_struct rst_timer_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct work_struct set_link_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Flag that can be used to turn on or turn off the Rx checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * offload feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int rx_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Below variables are used for fifo selection to transmit a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u16 fifo_selector[MAX_TX_FIFOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Total fifos for tcp packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u8 total_tcp_fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * Beginning index of udp for udp packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * Value will be equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u8 udp_fifo_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 total_udp_fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * Beginning index of fifo for all other packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u8 other_fifo_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* after blink, the adapter must be restored with original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u64 adapt_ctrl_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Last known link state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u16 last_link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define LINK_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define LINK_UP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int task_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) unsigned long long start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int vlan_strip_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define MSIX_FLG 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct msix_entry *entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int msi_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) wait_queue_head_t msi_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct s2io_msix_entry *s2io_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) char desc[MAX_REQUESTED_MSI_X][25];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct msix_info_st msix_info[0x3f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define XFRAME_I_DEVICE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define XFRAME_II_DEVICE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u8 device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) unsigned long clubbed_frms_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned long sending_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u16 lro_max_aggr_per_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) volatile unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u64 general_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define VPD_STRING_LEN 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u8 product_name[VPD_STRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 serial_num[VPD_STRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define RESET_ERROR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define CMD_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Some registers have to be written in a particular order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * expect correct hardware operation. The macro SPECIAL_REG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * is used to perform such ordered writes. Defines UF (Upper First)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * and LF (Lower First) will be used to specify the required write order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define UF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define LF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (order == LF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) writel((u32) (val), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) (void) readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) writel((u32) (val >> 32), (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) (void) readl(addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writel((u32) (val >> 32), (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) (void) readl(addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) writel((u32) (val), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (void) readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* Interrupt related values of Xena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define ENABLE_INTRS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define DISABLE_INTRS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Highest level interrupt blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define TX_PIC_INTR (0x0001<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define TX_DMA_INTR (0x0001<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define TX_MAC_INTR (0x0001<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define TX_XGXS_INTR (0x0001<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define TX_TRAFFIC_INTR (0x0001<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define RX_PIC_INTR (0x0001<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define RX_DMA_INTR (0x0001<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define RX_MAC_INTR (0x0001<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define RX_XGXS_INTR (0x0001<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define RX_TRAFFIC_INTR (0x0001<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define MC_INTR (0x0001<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define ENA_ALL_INTRS ( TX_PIC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) TX_DMA_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) TX_MAC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) TX_XGXS_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) TX_TRAFFIC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RX_PIC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RX_DMA_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RX_MAC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RX_XGXS_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) RX_TRAFFIC_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MC_INTR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Interrupt masks for the general interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define TXPIC_INT_M s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define TXDMA_INT_M s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define TXMAC_INT_M s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define TXXGXS_INT_M s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define TXTRAFFIC_INT_M s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define PIC_RX_INT_M s2BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define RXDMA_INT_M s2BIT(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define RXMAC_INT_M s2BIT(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define MC_INT_M s2BIT(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define RXXGXS_INT_M s2BIT(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define RXTRAFFIC_INT_M s2BIT(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* PIC level Interrupts TODO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* DMA level Inressupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define TXDMA_PFC_INT_M s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define TXDMA_PCC_INT_M s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* PFC block interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* PCC block interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PCC_FB_ECC Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * Prototype declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void s2io_rem_nic(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int init_shared_mem(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static void free_shared_mem(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int init_nic(struct s2io_nic *nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int rx_intr_handler(struct ring_info *ring_data, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static void s2io_txpic_intr_handle(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void tx_intr_handler(struct fifo_info *fifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static void s2io_handle_errors(void * dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void s2io_set_multicast(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static void s2io_link(struct s2io_nic * sp, int link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static void s2io_reset(struct s2io_nic * sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int s2io_poll_msix(struct napi_struct *napi, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int s2io_poll_inta(struct napi_struct *napi, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static void s2io_init_pci(struct s2io_nic * sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static void s2io_alarm_handle(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) s2io_msix_ring_handle(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) s2io_msix_fifo_handle(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static irqreturn_t s2io_isr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int verify_xena_quiescence(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const struct ethtool_ops netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static void s2io_set_link(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int s2io_set_swapper(struct s2io_nic * sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static void s2io_card_down(struct s2io_nic *nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int s2io_card_up(struct s2io_nic *nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int bit_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int s2io_add_isr(struct s2io_nic * sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static void s2io_rem_isr(struct s2io_nic * sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void restore_xmsi_data(struct s2io_nic *nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct s2io_nic *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static void clear_lro_session(struct lro *lro);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct sk_buff *skb, u32 tcp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pci_channel_state_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static void s2io_io_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define S2IO_PARM_INT(X, def_val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static unsigned int X = def_val;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) module_param(X , uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #endif /* _S2IO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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