^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2002-2010 Exar Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Drivers based on or derived from this code fall under the GPL and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * retain the authorship, copyright and license notice. This file is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a complete program and may only be used when the entire operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * system is licensed under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * See the file COPYING in this distribution for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TBD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct XENA_dev_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Convention: mHAL_XXX is mask, vHAL_XXX is value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* General Control-Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u64 general_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GEN_INTR_TXPIC s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GEN_INTR_TXDMA s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GEN_INTR_TXMAC s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GEN_INTR_TXXGXS s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GEN_INTR_TXTRAFFIC s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GEN_INTR_RXPIC s2BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GEN_INTR_RXDMA s2BIT(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GEN_INTR_RXMAC s2BIT(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GEN_INTR_MC s2BIT(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GEN_INTR_RXXGXS s2BIT(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GEN_INTR_RXTRAFFIC s2BIT(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) GEN_INTR_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u64 general_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 unused0[0x100 - 0x10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u64 sw_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* XGXS must be removed from reset only once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SW_RESET_XENA vBIT(0xA5,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SW_RESET_FLASH vBIT(0xA5,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SW_RESET_EOI vBIT(0xA5,16,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SW_RESET_ALL (SW_RESET_XENA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SW_RESET_FLASH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SW_RESET_EOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* The SW_RESET register must read this value after a successful reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SW_RESET_RAW_VAL 0xA5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 adapter_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADAPTER_STATUS_TDMA_READY s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADAPTER_STATUS_RDMA_READY s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADAPTER_STATUS_PFC_READY s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u64 adapter_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADAPTER_CNTL_EN s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADAPTER_EOI_TX_ON s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADAPTER_LED_ON s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADAPTER_UDPI(val) vBIT(val,36,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADAPTER_WAIT_INT s2BIT(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADAPTER_ECC_EN s2BIT(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 serr_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SERR_SOURCE_PIC s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SERR_SOURCE_TXDMA s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SERR_SOURCE_RXDMA s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SERR_SOURCE_MAC s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SERR_SOURCE_MC s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SERR_SOURCE_XGXS s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SERR_SOURCE_TXDMA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SERR_SOURCE_RXDMA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SERR_SOURCE_MAC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SERR_SOURCE_MC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SERR_SOURCE_XGXS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 pci_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCI_MODE_PCI_33 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCI_MODE_PCI_66 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCI_MODE_PCIX_M1_66 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCI_MODE_PCIX_M1_100 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCI_MODE_PCIX_M1_133 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCI_MODE_PCIX_M2_66 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCI_MODE_PCIX_M2_100 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCI_MODE_PCIX_M2_133 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCI_MODE_UNSUPPORTED s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCI_MODE_32_BITS s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCI_MODE_UNKNOWN_MODE s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 unused_0[0x800 - 0x128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* PCI-X Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 pic_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u64 pic_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PIC_INT_TX s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PIC_INT_FLSH s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PIC_INT_MDIO s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PIC_INT_IIC s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PIC_INT_GPIO s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PIC_INT_RX s2BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 txpic_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u64 txpic_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u64 txpic_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u64 rxpic_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 rxpic_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u64 rxpic_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 flsh_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 flsh_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PIC_FLSH_INT_REG_ERR s2BIT(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u64 flash_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u64 mdio_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 mdio_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MDIO_INT_REG_LASI s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u64 mdio_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u64 iic_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u64 iic_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IIC_INT_REG_ACK_ERR s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u64 iic_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 unused4[0x08];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u64 gpio_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPIO_INT_REG_DP_ERR_INT s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GPIO_INT_REG_LINK_DOWN s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPIO_INT_REG_LINK_UP s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 gpio_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GPIO_INT_MASK_LINK_UP s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u64 gpio_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 unused5[0x38];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u64 tx_traffic_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TX_TRAFFIC_INT_n(n) s2BIT(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u64 tx_traffic_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u64 rx_traffic_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RX_TRAFFIC_INT_n(n) s2BIT(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u64 rx_traffic_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* PIC Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u64 pic_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u64 swapper_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SWAPPER_CTRL_PIF_R_FE s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SWAPPER_CTRL_PIF_W_SE s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SWAPPER_CTRL_TXP_FE s2BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SWAPPER_CTRL_TXP_SE s2BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SWAPPER_CTRL_TXD_R_FE s2BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SWAPPER_CTRL_TXD_R_SE s2BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SWAPPER_CTRL_TXD_W_FE s2BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SWAPPER_CTRL_TXD_W_SE s2BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SWAPPER_CTRL_TXF_R_FE s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SWAPPER_CTRL_TXF_R_SE s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SWAPPER_CTRL_RXD_R_FE s2BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SWAPPER_CTRL_RXD_R_SE s2BIT(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SWAPPER_CTRL_RXD_W_FE s2BIT(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SWAPPER_CTRL_RXD_W_SE s2BIT(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SWAPPER_CTRL_RXF_W_FE s2BIT(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SWAPPER_CTRL_RXF_W_SE s2BIT(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SWAPPER_CTRL_XMSI_FE s2BIT(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SWAPPER_CTRL_XMSI_SE s2BIT(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SWAPPER_CTRL_STATS_FE s2BIT(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SWAPPER_CTRL_STATS_SE s2BIT(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u64 pif_rd_swapper_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u64 scheduled_int_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCHED_INT_CTRL_TIMER_EN s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SCHED_INT_PERIOD TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u64 txreqtimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TXREQTO_VAL(val) vBIT(val,0,32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TXREQTO_EN s2BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u64 statsreqtimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define STATREQTO_VAL(n) TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define STATREQTO_EN s2BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u64 read_retry_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 read_retry_acceleration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u64 write_retry_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u64 write_retry_acceleration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 xmsi_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 xmsi_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 xmsi_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u64 xmsi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u64 rx_mat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 unused6[0x8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 tx_mat0_n[0x8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 xmsi_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u64 stat_byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STAT_BC(n) vBIT(n,4,12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Automated statistics collection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u64 stat_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define STAT_CFG_STAT_EN s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define STAT_CFG_ONE_SHOT_EN s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define STAT_CFG_STAT_NS_EN s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define STAT_CFG_STAT_RO s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define STAT_TRSF_PER(n) TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PER_SEC 0x208d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 stat_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* General Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 mdio_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MDIO_OP(val) vBIT(val, 60, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MDIO_OP_ADDR_TRANS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MDIO_OP_WRITE_TRANS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MDIO_OP_READ_POST_INC_TRANS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MDIO_OP_READ_TRANS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u64 dtx_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u64 i2c_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define I2C_CONTROL_READ s2BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define I2C_CONTROL_NACK s2BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u64 gpio_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GPIO_CTRL_GPIO_0 s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u64 misc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define FAULT_BEHAVIOUR s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EXT_REQ_EN s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 unused7_1[0x230 - 0x208];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u64 pic_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u64 ini_dperr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 wreq_split_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 unused7_2[0x800 - 0x248];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* TxDMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u64 txdma_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u64 txdma_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TXDMA_PFC_INT s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TXDMA_TDA_INT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TXDMA_PCC_INT s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TXDMA_TTI_INT s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TXDMA_LSO_INT s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TXDMA_TPA_INT s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TXDMA_SM_INT s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u64 pfc_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PFC_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PFC_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PFC_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PFC_MISC_0_ERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PFC_MISC_1_ERR s2BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PFC_PCIX_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u64 pfc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u64 pfc_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u64 tda_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TDA_SM0_ERR_ALARM s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TDA_SM1_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TDA_PCIX_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u64 tda_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u64 tda_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u64 pcc_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PCC_N_SERR vBIT(0xff,48,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PCC_6_COF_OV_ERR s2BIT(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PCC_7_COF_OV_ERR s2BIT(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PCC_6_LSO_OV_ERR s2BIT(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PCC_7_LSO_OV_ERR s2BIT(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u64 pcc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u64 pcc_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u64 tti_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TTI_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TTI_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TTI_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u64 tti_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u64 tti_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u64 lso_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define LSO6_SEND_OFLOW s2BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define LSO7_SEND_OFLOW s2BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define LSO6_ABORT s2BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define LSO7_ABORT s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define LSO6_SM_ERR_ALARM s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define LSO7_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u64 lso_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 lso_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u64 tpa_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TPA_TX_FRM_DROP s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TPA_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 tpa_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u64 tpa_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u64 sm_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SM_SM_ERR_ALARM s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u64 sm_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u64 sm_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 unused8[0x100 - 0xB8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* TxDMA arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u64 tx_dma_wrap_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Tx FIFO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define X_MAX_FIFOS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define X_FIFO_MAX_LEN 0x1FFF /*8191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u64 tx_fifo_partition_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TX_FIFO_PARTITION_EN s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u64 tx_fifo_partition_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u64 tx_fifo_partition_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u64 tx_fifo_partition_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define TX_FIFO_PARTITION_PRI_0 0 /* highest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define TX_FIFO_PARTITION_PRI_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define TX_FIFO_PARTITION_PRI_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define TX_FIFO_PARTITION_PRI_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TX_FIFO_PARTITION_PRI_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TX_FIFO_PARTITION_PRI_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TX_FIFO_PARTITION_PRI_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u64 tx_w_round_robin_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u64 tx_w_round_robin_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u64 tx_w_round_robin_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u64 tx_w_round_robin_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u64 tx_w_round_robin_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u64 tti_command_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define TTI_CMD_MEM_WE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u64 tti_data1_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u64 tti_data2_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Tx Protocol assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u64 tx_pa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Recent add, used only debug purposes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u64 pcc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 unused9[0x700 - 0x178];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u64 txdma_debug_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 unused10[0x1800 - 0x1708];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* RxDMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u64 rxdma_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u64 rxdma_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RXDMA_INT_RC_INT_M s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RXDMA_INT_RPA_INT_M s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RXDMA_INT_RDA_INT_M s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define RXDMA_INT_RTI_INT_M s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u64 rda_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define RDA_FRM_ECC_SG_ERR s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RDA_FRM_ECC_DB_N_AERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RDA_SM1_ERR_ALARM s2BIT(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RDA_SM0_ERR_ALARM s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define RDA_MISC_ERR s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define RDA_PCIX_ERR s2BIT(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define RDA_RXD_ECC_DB_SERR s2BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u64 rda_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u64 rda_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 rc_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define RC_FTC_ECC_SG_ERR s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define RC_FTC_ECC_DB_ERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define RC_FTC_SM_ERR_ALARM s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u64 rc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u64 rc_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u64 prc_pcix_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u64 prc_pcix_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u64 prc_pcix_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u64 rpa_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define RPA_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define RPA_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define RPA_FLUSH_REQUEST s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define RPA_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define RPA_CREDIT_ERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u64 rpa_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u64 rpa_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u64 rti_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define RTI_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define RTI_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define RTI_SM_ERR_ALARM s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u64 rti_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u64 rti_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 unused11[0x100 - 0x88];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* DMA arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u64 rx_queue_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define RX_QUEUE_PRI_0 0 /* highest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define RX_QUEUE_PRI_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define RX_QUEUE_PRI_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define RX_QUEUE_PRI_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define RX_QUEUE_PRI_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define RX_QUEUE_PRI_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define RX_QUEUE_PRI_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define RX_QUEUE_PRI_7 7 /* lowest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u64 rx_w_round_robin_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u64 rx_w_round_robin_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 rx_w_round_robin_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u64 rx_w_round_robin_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u64 rx_w_round_robin_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Per-ring controller regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define RX_MAX_RINGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define RX_MIN_RINGS_SZ 0x3F /* 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u64 prc_rxd0_n[RX_MAX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u64 prc_ctrl_n[RX_MAX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define PRC_CTRL_RC_ENABLED s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define PRC_CTRL_GROUP_READS s2BIT(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u64 prc_alarm_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Receive traffic interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u64 rti_command_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define RTI_CMD_MEM_WE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define RTI_CMD_MEM_STROBE s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u64 rti_data1_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u64 rti_data2_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u64 rx_pa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u64 unused_11_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u64 ring_bump_counter1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u64 ring_bump_counter2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 unused12[0x700 - 0x1F0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u64 rxdma_debug_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 unused13[0x2000 - 0x1f08];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Media Access Controller Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u64 mac_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u64 mac_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MAC_INT_STATUS_TMAC_INT s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MAC_INT_STATUS_RMAC_INT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u64 mac_tmac_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define TMAC_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define TMAC_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define TMAC_TX_BUF_OVRN s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define TMAC_TX_CRI_ERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define TMAC_TX_SM_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define TMAC_DESC_ECC_SG_ERR s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define TMAC_DESC_ECC_DB_ERR s2BIT(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u64 mac_tmac_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u64 mac_tmac_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u64 mac_rmac_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define RMAC_RX_BUFF_OVRN s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define RMAC_FRM_RCVD_INT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define RMAC_UNUSED_INT s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define RMAC_RX_SM_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) s2BIT(8) | s2BIT(9) | s2BIT(10)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) s2BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) s2BIT(16) | s2BIT(17) | s2BIT(18)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) s2BIT(19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u64 mac_rmac_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u64 mac_rmac_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 unused14[0x100 - 0x40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u64 mac_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MAC_CFG_TMAC_ENABLE s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define MAC_CFG_RMAC_ENABLE s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define MAC_CFG_LAN_NOT_WAN s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define MAC_CFG_TMAC_LOOPBACK s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define MAC_RMAC_DISCARD_PFRM s2BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define MAC_RMAC_BCAST_ENABLE s2BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u64 tmac_avg_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TMAC_AVG_IPG(val) vBIT(val,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u64 rmac_max_pyld_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u64 rmac_err_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define RMAC_ERR_FCS s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define RMAC_ERR_FCS_ACCEPT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define RMAC_ERR_TOO_LONG s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define RMAC_ERR_RUNT s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define RMAC_ERR_RUNT_ACCEPT s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define RMAC_ERR_LEN_MISMATCH s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u64 rmac_cfg_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define RMAC_CFG_KEY(val) vBIT(val,0,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define S2IO_MAC_ADDR_START_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define S2IO_HERC_MAX_MC_ADDRESSES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define S2IO_XENA_MAX_MAC_ADDRESSES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define S2IO_HERC_MAX_MAC_ADDRESSES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define S2IO_XENA_MC_ADDR_START_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define S2IO_HERC_MC_ADDR_START_OFFSET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u64 rmac_addr_cmd_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define RMAC_ADDR_CMD_MEM_RD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u64 rmac_addr_data0_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define RMAC_ADDR_DATA0_MEM_USER s2BIT(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u64 rmac_addr_data1_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 unused15[0x8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u64 rmac_addr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define RMAC_ADDR_BCAST_EN vBIT(0)_48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u64 tmac_ipg_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u64 rmac_pause_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define RMAC_PAUSE_GEN s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define RMAC_PAUSE_GEN_ENABLE s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define RMAC_PAUSE_RX s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define RMAC_PAUSE_RX_ENABLE s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u64 rmac_red_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u64 rmac_red_rate_q0q3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u64 rmac_red_rate_q4q7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u64 mac_link_util;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) MAC_RX_LINK_UTIL_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u64 rmac_invalid_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* rx traffic steering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u64 rts_frm_len_n[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u64 rts_qos_steering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MAX_DIX_MAP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u64 rts_dix_map_n[MAX_DIX_MAP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u64 rts_q_alternates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u64 rts_default_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u64 rts_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u64 rts_pn_cam_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define RTS_PN_CAM_CTRL_WE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u64 rts_pn_cam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u64 rts_ds_mem_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define RTS_DS_MEM_CTRL_WE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u64 rts_ds_mem_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u8 unused16[0x700 - 0x220];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u64 mac_debug_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 unused17[0x2800 - 0x2708];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* memory controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u64 mc_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define MC_INT_STATUS_MC_INT s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u64 mc_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MC_INT_MASK_MC_INT s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u64 mc_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MC_ERR_REG_SM_ERR s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) s2BIT(17) | s2BIT(19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) s2BIT(13) | s2BIT(18) | s2BIT(20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define PLL_LOCK_N s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u64 mc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u64 mc_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 unused18[0x100 - 0x28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* MC configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64 rx_queue_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u64 mc_rldram_mrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define MC_RLDRAM_MRS_ENABLE s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u64 mc_rldram_interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u64 mc_pause_thresh_q0q3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u64 mc_pause_thresh_q4q7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u64 mc_red_thresh_q[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 unused19[0x200 - 0x168];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u64 mc_rldram_ref_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 unused20[0x220 - 0x208];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u64 mc_rldram_test_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MC_RLDRAM_TEST_MODE s2BIT(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MC_RLDRAM_TEST_WRITE s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MC_RLDRAM_TEST_GO s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define MC_RLDRAM_TEST_DONE s2BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define MC_RLDRAM_TEST_PASS s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u8 unused21[0x240 - 0x228];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u64 mc_rldram_test_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u8 unused22[0x260 - 0x248];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u64 mc_rldram_test_d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u8 unused23[0x280 - 0x268];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u64 mc_rldram_test_d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u8 unused24[0x300 - 0x288];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u64 mc_rldram_test_d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u8 unused24_1[0x360 - 0x308];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u64 mc_rldram_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MC_RLDRAM_ENABLE_ODT s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u8 unused24_2[0x640 - 0x368];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u64 mc_rldram_ref_per_herc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u8 unused24_3[0x660 - 0x648];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u64 mc_rldram_mrs_herc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u8 unused25[0x700 - 0x668];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u64 mc_debug_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u8 unused26[0x3000 - 0x2f08];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* XGXG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* XGXS control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u64 xgxs_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define XGXS_INT_STATUS_TXGXS s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define XGXS_INT_STATUS_RXGXS s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u64 xgxs_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define XGXS_INT_MASK_TXGXS s2BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define XGXS_INT_MASK_RXGXS s2BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u64 xgxs_txgxs_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define TXGXS_ECC_SG_ERR s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define TXGXS_ECC_DB_ERR s2BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define TXGXS_ESTORE_UFLOW s2BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define TXGXS_TX_SM_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u64 xgxs_txgxs_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u64 xgxs_txgxs_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u64 xgxs_rxgxs_err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define RXGXS_ESTORE_OFLOW s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define RXGXS_RX_SM_ERR s2BIT(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u64 xgxs_rxgxs_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u64 xgxs_rxgxs_err_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u8 unused27[0x100 - 0x40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u64 xgxs_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u64 xgxs_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u64 xgxs_cfg_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u64 xgxs_efifo_cfg; /* CHANGED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u64 rxgxs_ber_0; /* CHANGED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u64 rxgxs_ber_1; /* CHANGED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u64 spi_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define SPI_CONTROL_KEY(key) vBIT(key,0,4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define SPI_CONTROL_SEL1 s2BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define SPI_CONTROL_REQ s2BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define SPI_CONTROL_NACK s2BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define SPI_CONTROL_DONE s2BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u64 spi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define XENA_REG_SPACE sizeof(struct XENA_dev_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define XENA_EEPROM_SPACE (0x01 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #endif /* _REGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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