^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Header file for sonic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Waldorf Electronics, Germany
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written by Andreas Busse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * NOTE: most of the structure definitions here are endian dependent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * If you want to use this driver on big endian machines, the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and pad structure members must be exchanged. Also, the structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * need to be changed accordingly to the bus size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 981229 MSch: did just that for the 68k Mac port (32 bit, big endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 990611 David Huggins-Daines <dhd@debian.org>: This machine abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * does not cope with 16-bit bus sizes very well. Therefore I have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * rewritten it with ugly macros and evil inlines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 050625 Finn Thain: introduced more 32-bit cards and dhd's support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * for 16-bit cards (from the mac68k project).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef SONIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SONIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SONIC register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SONIC_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SONIC_DCR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SONIC_RCR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SONIC_TCR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SONIC_IMR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SONIC_ISR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SONIC_UTDA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SONIC_CTDA 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SONIC_URDA 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SONIC_CRDA 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SONIC_EOBC 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SONIC_URRA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SONIC_RSA 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SONIC_REA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SONIC_RRP 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SONIC_RWP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SONIC_RSC 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SONIC_CEP 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SONIC_CAP2 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SONIC_CAP1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SONIC_CAP0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SONIC_CE 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SONIC_CDP 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SONIC_CDC 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SONIC_WT0 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SONIC_WT1 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SONIC_SR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* test-only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SONIC_TPS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SONIC_TFC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SONIC_TSA0 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SONIC_TSA1 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SONIC_TFS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SONIC_CRBA0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SONIC_CRBA1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SONIC_RBWC0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SONIC_RBWC1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SONIC_TTDA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SONIC_MDT 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SONIC_TRBA0 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SONIC_TRBA1 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SONIC_TBWC0 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SONIC_TBWC1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SONIC_LLFA 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SONIC_ADDR0 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SONIC_ADDR1 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Error counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SONIC_CRCT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SONIC_FAET 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SONIC_MPT 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SONIC_DCR2 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * SONIC command bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SONIC_CR_LCAM 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SONIC_CR_RRRA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SONIC_CR_RST 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SONIC_CR_ST 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SONIC_CR_STP 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SONIC_CR_RXEN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SONIC_CR_RXDIS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SONIC_CR_TXP 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SONIC_CR_HTX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SONIC_CR_ALL (SONIC_CR_LCAM | SONIC_CR_RRRA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SONIC_CR_RXEN | SONIC_CR_TXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * SONIC data configuration bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SONIC_DCR_EXBUS 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SONIC_DCR_LBR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SONIC_DCR_PO1 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SONIC_DCR_PO0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SONIC_DCR_SBUS 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SONIC_DCR_USR1 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SONIC_DCR_USR0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SONIC_DCR_WC1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SONIC_DCR_WC0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SONIC_DCR_DW 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SONIC_DCR_BMS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SONIC_DCR_RFT1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SONIC_DCR_RFT0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SONIC_DCR_TFT1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SONIC_DCR_TFT0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Constants for the SONIC receive control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SONIC_RCR_ERR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SONIC_RCR_RNT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SONIC_RCR_BRD 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SONIC_RCR_PRO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SONIC_RCR_AMC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SONIC_RCR_LB1 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SONIC_RCR_LB0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SONIC_RCR_MC 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SONIC_RCR_BC 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SONIC_RCR_LPKT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SONIC_RCR_CRS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SONIC_RCR_COL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SONIC_RCR_CRCR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SONIC_RCR_FAER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SONIC_RCR_LBK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SONIC_RCR_PRX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SONIC_RCR_LB_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SONIC_RCR_LB_MAC SONIC_RCR_LB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SONIC_RCR_LB_ENDEC SONIC_RCR_LB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SONIC_RCR_LB_TRANS (SONIC_RCR_LB0 | SONIC_RCR_LB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* default RCR setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SONIC_RCR_DEFAULT (SONIC_RCR_BRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * SONIC Transmit Control register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SONIC_TCR_PINTR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SONIC_TCR_POWC 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SONIC_TCR_CRCI 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SONIC_TCR_EXDIS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SONIC_TCR_EXD 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SONIC_TCR_DEF 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SONIC_TCR_NCRS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SONIC_TCR_CRLS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SONIC_TCR_EXC 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SONIC_TCR_OWC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SONIC_TCR_PMB 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SONIC_TCR_FU 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SONIC_TCR_BCM 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SONIC_TCR_PTX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SONIC_TCR_DEFAULT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Constants for the SONIC_INTERRUPT_MASK and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * SONIC_INTERRUPT_STATUS registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SONIC_INT_BR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SONIC_INT_HBL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SONIC_INT_LCD 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SONIC_INT_PINT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SONIC_INT_PKTRX 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SONIC_INT_TXDN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SONIC_INT_TXER 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SONIC_INT_TC 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SONIC_INT_RDE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SONIC_INT_RBE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SONIC_INT_RBAE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SONIC_INT_CRC 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SONIC_INT_FAE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SONIC_INT_MP 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SONIC_INT_RFO 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * The interrupts we allow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SONIC_IMR_DEFAULT ( SONIC_INT_BR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SONIC_INT_LCD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SONIC_INT_RFO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SONIC_INT_PKTRX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SONIC_INT_TXDN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SONIC_INT_TXER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SONIC_INT_RDE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SONIC_INT_RBAE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SONIC_INT_CRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SONIC_INT_FAE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SONIC_INT_MP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SONIC_EOL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CAM_DESCRIPTORS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Offsets in the various DMA buffers accessed by the SONIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SONIC_BITMODE16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SONIC_BITMODE32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SONIC_BUS_SCALE(bitmode) ((bitmode) ? 4 : 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Note! These are all measured in bus-size units, so use SONIC_BUS_SCALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SIZEOF_SONIC_RR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SONIC_RR_BUFADR_L 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SONIC_RR_BUFADR_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SONIC_RR_BUFSIZE_L 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SONIC_RR_BUFSIZE_H 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SIZEOF_SONIC_RD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SONIC_RD_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SONIC_RD_PKTLEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SONIC_RD_PKTPTR_L 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SONIC_RD_PKTPTR_H 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SONIC_RD_SEQNO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SONIC_RD_LINK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SONIC_RD_IN_USE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SIZEOF_SONIC_TD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SONIC_TD_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SONIC_TD_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SONIC_TD_PKTSIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SONIC_TD_FRAG_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SONIC_TD_FRAG_PTR_L 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SONIC_TD_FRAG_PTR_H 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SONIC_TD_FRAG_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SONIC_TD_LINK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SIZEOF_SONIC_CD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SONIC_CD_ENTRY_POINTER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SONIC_CD_CAP0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SONIC_CD_CAP1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SONIC_CD_CAP2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SIZEOF_SONIC_CDA ((CAM_DESCRIPTORS * SIZEOF_SONIC_CD) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SONIC_CDA_CAM_ENABLE (CAM_DESCRIPTORS * SIZEOF_SONIC_CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Some tunables for the buffer areas. Power of 2 is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * the current driver uses one receive buffer for each descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * MSch: use more buffer space for the slow m68k Macs!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SONIC_NUM_RRS 16 /* number of receive resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SONIC_NUM_RDS SONIC_NUM_RRS /* number of receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SONIC_NUM_TDS 16 /* number of transmit descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SONIC_RRS_MASK (SONIC_NUM_RRS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SONIC_RDS_MASK (SONIC_NUM_RDS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SONIC_TDS_MASK (SONIC_NUM_TDS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SONIC_RBSIZE 1520 /* size of one resource buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Again, measured in bus size units! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SIZEOF_SONIC_DESC (SIZEOF_SONIC_CDA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) + (SIZEOF_SONIC_TD * SONIC_NUM_TDS) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) + (SIZEOF_SONIC_RD * SONIC_NUM_RDS) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) + (SIZEOF_SONIC_RR * SONIC_NUM_RRS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Information that need to be kept for each board. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct sonic_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Bus size. 0 == 16 bits, 1 == 32 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int dma_bitmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Register offset within the longword (independent of endianness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) and varies from one type of Macintosh SONIC to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (Aarrgh)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) void *descriptors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Crud. These areas have to be within the same 64K. Therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) we allocate a desriptors page, and point these to places within it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void *cda; /* CAM descriptor area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void *tda; /* Transmit descriptor area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void *rra; /* Receive resource area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void *rda; /* Receive descriptor area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct sk_buff* volatile rx_skb[SONIC_NUM_RRS]; /* packets to be received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct sk_buff* volatile tx_skb[SONIC_NUM_TDS]; /* packets to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int tx_len[SONIC_NUM_TDS]; /* lengths of tx DMA mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Logical DMA addresses on MIPS, bus addresses on m68k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * (so "laddr" is a bit misleading) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dma_addr_t descriptors_laddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 cda_laddr; /* logical DMA address of CDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 tda_laddr; /* logical DMA address of TDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 rra_laddr; /* logical DMA address of RRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 rda_laddr; /* logical DMA address of RDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dma_addr_t rx_laddr[SONIC_NUM_RRS]; /* logical DMA addresses of rx skbuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dma_addr_t tx_laddr[SONIC_NUM_TDS]; /* logical DMA addresses of tx skbuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int cur_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int cur_tx; /* first unacked transmit packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int eol_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int eol_tx; /* last unacked transmit packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *device; /* generic device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct net_device_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TX_TIMEOUT (3 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Index to functions, as function prototypes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int sonic_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int sonic_send_packet(struct sk_buff *skb, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static irqreturn_t sonic_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void sonic_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int sonic_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct net_device_stats *sonic_get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void sonic_multicast_list(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int sonic_init(struct net_device *dev, bool may_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void sonic_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sonic_msg_init(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int sonic_alloc_descriptors(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Internal inlines for reading/writing DMA buffers. Note that bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) size and endianness matter here, whereas they don't for registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) as far as we can tell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* OpenBSD calls this "SWO". I'd like to think that sonic_buf_put()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) is a much better name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static inline void sonic_buf_put(u16 *base, int bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int offset, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (bitmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __raw_writew(val, base + (offset * 2) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __raw_writew(val, base + (offset * 2) + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __raw_writew(val, base + (offset * 1) + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline __u16 sonic_buf_get(u16 *base, int bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (bitmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return __raw_readw(base + (offset * 2) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return __raw_readw(base + (offset * 2) + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return __raw_readw(base + (offset * 1) + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Inlines that you should actually use for reading/writing DMA buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline void sonic_cda_put(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int offset, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sonic_buf_put(lp->cda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (entry * SIZEOF_SONIC_CD) + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline __u16 sonic_cda_get(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return sonic_buf_get(lp->cda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (entry * SIZEOF_SONIC_CD) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline void sonic_set_cam_enable(struct net_device* dev, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) sonic_buf_put(lp->cda, lp->dma_bitmode, SONIC_CDA_CAM_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline __u16 sonic_get_cam_enable(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return sonic_buf_get(lp->cda, lp->dma_bitmode, SONIC_CDA_CAM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static inline void sonic_tda_put(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int offset, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) sonic_buf_put(lp->tda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) (entry * SIZEOF_SONIC_TD) + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline __u16 sonic_tda_get(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return sonic_buf_get(lp->tda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) (entry * SIZEOF_SONIC_TD) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline void sonic_rda_put(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int offset, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) sonic_buf_put(lp->rda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) (entry * SIZEOF_SONIC_RD) + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline __u16 sonic_rda_get(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return sonic_buf_get(lp->rda, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (entry * SIZEOF_SONIC_RD) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static inline void sonic_rra_put(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int offset, __u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sonic_buf_put(lp->rra, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) (entry * SIZEOF_SONIC_RR) + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline __u16 sonic_rra_get(struct net_device* dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return sonic_buf_get(lp->rra, lp->dma_bitmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (entry * SIZEOF_SONIC_RR) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static inline u16 sonic_rr_addr(struct net_device *dev, int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return lp->rra_laddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) entry * SIZEOF_SONIC_RR * SONIC_BUS_SCALE(lp->dma_bitmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline u16 sonic_rr_entry(struct net_device *dev, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct sonic_local *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return (addr - (u16)lp->rra_laddr) / (SIZEOF_SONIC_RR *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SONIC_BUS_SCALE(lp->dma_bitmode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "sonic.c:v0.92 20.9.98 tsbogend@alpha.franken.de\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif /* SONIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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