^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define VERSION "0.23"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* ns83820.c by Benjamin LaHaise with contributions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Questions/comments/discussion to linux-ns83820@kvack.org.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * $Revision: 1.34.2.23 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2001 Benjamin LaHaise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2001, 2002 Red Hat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Mmmm, chocolate vanilla mocha...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ChangeLog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * =========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 20010414 0.1 - created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 20010622 0.2 - basic rx and tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 20010711 0.3 - added duplex and link state detection support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 20010713 0.4 - zero copy, no hangs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 0.5 - 64 bit dma support (davem will hate me for this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - disable jumbo frames to avoid tx hangs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - work around tx deadlocks on my 1.02 card via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * fiddling with TXCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 20010816 0.7 - misc cleanups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 20010826 0.8 - fix critical zero copy bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0.9 - internal experiment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 20010827 0.10 - fix ia64 unaligned access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 20010906 0.11 - accept all packets with checksum errors as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * otherwise fragments get lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - fix >> 32 bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 0.12 - add statistics counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - add allmulti/promisc support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 20011009 0.13 - hotplug support, other smaller pci api cleanups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 20011204 0.13a - optical transceiver support added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * by Michael Clark <michael@metaparadigm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 20011205 0.13b - call register_netdev earlier in initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * suppress duplicate link status messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 20011204 0.15 get ppc (big endian) working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 20011218 0.16 various cleanups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 20020310 0.17 speedups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 20020610 0.18 - actually use the pci dma api for highmem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - remove pci latency register fiddling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 0.19 - better bist support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * - add ihr and reset_phy parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - gmii bus probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * - fix missed txok introduced during performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 0.20 - fix stupid RFEN thinko. i am such a smurf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 20040828 0.21 - add hardware vlan accleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * by Neil Horman <nhorman@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * - removal of dead code from Adrian Bunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * - fix half duplex collision behaviour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Driver Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * This driver was originally written for the National Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * this code will turn out to be a) clean, b) correct, and c) fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * With that in mind, I'm aiming to split the code up as much as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * reasonably possible. At present there are X major sections that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * break down into a) packet receive, b) packet transmit, c) link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * management, d) initialization and configuration. Where possible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * these code paths are designed to run in parallel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * This driver has been tested and found to work with the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * cards (in no particular order):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Cameo SOHO-GA2000T SOHO-GA2500T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * D-Link DGE-500T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * PureData PDP8023Z-TG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * SMC SMC9452TX SMC9462TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Netgear GA621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Special thanks to SMC for providing hardware to test this driver on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Reports of success or failure would be greatly appreciated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) //#define dprintk printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define dprintk(x...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/ip.h> /* for iph */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/in.h> /* for IPPROTO_... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #include <linux/rtnetlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRV_NAME "ns83820"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Global parameters. See module_param near the bottom. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int ihr = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int reset_phy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int lnksts = 0; /* CFG_LNKSTS bit polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Dprintk is used for more interesting debug events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #undef Dprintk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define Dprintk dprintk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* tunables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RX_BUF_SIZE 1500 /* 8192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #if IS_ENABLED(CONFIG_VLAN_8021Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Must not exceed ~65000. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NR_RX_DESC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NR_TX_DESC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* not tunable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MIN_TX_DESC_FREE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CFGCS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CR_TXE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CR_TXD 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * The Receive engine skips one descriptor and moves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * onto the next one!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CR_RXE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CR_RXD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CR_TXR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CR_RXR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CR_SWI 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CR_RST 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PTSCR_EEBIST_FAIL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PTSCR_EEBIST_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PTSCR_EELOAD_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PTSCR_RBIST_FAIL 0x000001b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PTSCR_RBIST_DONE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PTSCR_RBIST_EN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PTSCR_RBIST_RST 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MEAR_EEDI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MEAR_EEDO 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MEAR_EECLK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MEAR_EESEL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MEAR_MDIO 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MEAR_MDDIR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MEAR_MDC 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ISR_TXDESC3 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ISR_TXDESC2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ISR_TXDESC1 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ISR_TXDESC0 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ISR_RXDESC3 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ISR_RXDESC2 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ISR_RXDESC1 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ISR_RXDESC0 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ISR_TXRCMP 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ISR_RXRCMP 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ISR_DPERR 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ISR_SSERR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ISR_RMABT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ISR_RTABT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ISR_RXSOVR 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ISR_HIBINT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ISR_PHY 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ISR_PME 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ISR_SWI 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ISR_MIB 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ISR_TXURN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ISR_TXIDLE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ISR_TXERR 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ISR_TXDESC 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ISR_TXOK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ISR_RXORN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ISR_RXIDLE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ISR_RXEARLY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ISR_RXERR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ISR_RXDESC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ISR_RXOK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TXCFG_CSI 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TXCFG_HBI 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TXCFG_MLB 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TXCFG_ATP 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TXCFG_ECRETRY 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TXCFG_BRST_DIS 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TXCFG_MXDMA1024 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TXCFG_MXDMA512 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TXCFG_MXDMA256 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TXCFG_MXDMA128 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TXCFG_MXDMA64 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TXCFG_MXDMA32 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TXCFG_MXDMA16 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TXCFG_MXDMA8 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CFG_LNKSTS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CFG_SPDSTS 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CFG_SPDSTS1 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CFG_SPDSTS0 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CFG_DUPSTS 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CFG_TBI_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CFG_MODE_1000 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Read the Phy response and then configure the MAC accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CFG_AUTO_1000 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CFG_PINT_CTL 0x001c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CFG_PINT_DUPSTS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CFG_PINT_LNKSTS 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CFG_PINT_SPDSTS 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CFG_TMRTEST 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CFG_MRM_DIS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CFG_MWI_DIS 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CFG_T64ADDR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CFG_PCI64_DET 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CFG_DATA64_EN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CFG_M64ADDR 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CFG_PHY_RST 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CFG_PHY_DIS 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CFG_EXTSTS_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CFG_REQALG 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CFG_SB 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CFG_POW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CFG_EXD 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CFG_PESEL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CFG_BROM_DIS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CFG_EXT_125 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CFG_BEM 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EXTSTS_UDPPKT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EXTSTS_TCPPKT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EXTSTS_IPPKT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EXTSTS_VPKT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EXTSTS_VTG_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MIBC_MIBS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MIBC_ACLR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MIBC_FRZ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MIBC_WRN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PCR_PSEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PCR_PS_MCAST (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PCR_PS_DA (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PCR_STHI_8 (3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PCR_STLO_4 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PCR_FFHI_8K (3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PCR_FFLO_4K (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PCR_PAUSE_CNT 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RXCFG_AEP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RXCFG_ARP 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RXCFG_STRIPCRC 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RXCFG_RX_FD 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RXCFG_ALP 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define RXCFG_AIRL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RXCFG_MXDMA512 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RXCFG_DRTH 0x0000003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RXCFG_DRTH0 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RFCR_RFEN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RFCR_AAB 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define RFCR_AAM 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RFCR_AAU 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RFCR_APM 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define RFCR_APAT 0x07800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RFCR_APAT3 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define RFCR_APAT2 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RFCR_APAT1 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define RFCR_APAT0 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RFCR_AARP 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define RFCR_MHEN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define RFCR_UHEN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RFCR_ULM 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define VRCR_RUDPE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define VRCR_RTCPE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define VRCR_RIPE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VRCR_IPEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VRCR_DUTF 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VRCR_DVTF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define VRCR_VTREN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VRCR_VTDEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define VTCR_PPCHK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define VTCR_GCHK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define VTCR_VPPTI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define VTCR_VGTI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CFG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MEAR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PTSCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ISR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IHR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TXDP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TXDP_HI 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TXCFG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GPIOR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RXDP 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RXDP_HI 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RXCFG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PQCR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define WCSR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PCR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RFCR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RFDR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VRCR 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define VTCR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define VDR 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CCSR 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TBICR 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TBISR 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TANAR 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TANLPAR 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TANER 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TESR 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TBICR_MR_AN_ENABLE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TBICR_MR_RESTART_AN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TBISR_MR_LINK_STATUS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TBISR_MR_AN_COMPLETE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TANAR_PS2 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TANAR_PS1 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TANAR_HALF_DUP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TANAR_FULL_DUP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GPIOR_GP5_OE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define GPIOR_GP4_OE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define GPIOR_GP3_OE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define GPIOR_GP2_OE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define GPIOR_GP1_OE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define GPIOR_GP3_OUT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define GPIOR_GP1_OUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define LINK_AUTONEGOTIATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define LINK_DOWN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define LINK_UP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define HW_ADDR_LEN sizeof(dma_addr_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define desc_addr_set(desc, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ((desc)[0] = cpu_to_le32(addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (HW_ADDR_LEN == 8) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define desc_addr_get(desc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (le32_to_cpu((desc)[0]) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DESC_LINK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CMDSTS_OWN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CMDSTS_MORE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CMDSTS_INTR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CMDSTS_ERR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CMDSTS_OK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CMDSTS_RUNT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CMDSTS_LEN_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CMDSTS_DEST_MASK 0x01800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CMDSTS_DEST_SELF 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CMDSTS_DEST_MULTI 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DESC_SIZE 8 /* Should be cache line sized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct rx_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct sk_buff *skbs[NR_RX_DESC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __le32 *next_rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 next_rx, next_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __le32 *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dma_addr_t phy_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct ns83820 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct rx_info rx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct tasklet_struct rx_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned ihr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct work_struct tq_refill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* protects everything below. irqsave when using. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spinlock_t misc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 CFG_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 MEAR_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 IMR_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned linkstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spinlock_t tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u16 tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) volatile u16 tx_free_idx; /* idx of free desc chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 tx_intr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) atomic_t nr_tx_skbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sk_buff *tx_skbs[NR_TX_DESC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) char pad[16] __attribute__((aligned(16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __le32 *tx_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dma_addr_t tx_phy_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct timer_list tx_watchdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static inline struct ns83820 *PRIV(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline void kick_rx(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dprintk("kick_rx: maybe kicking\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (test_and_clear_bit(0, &dev->rx_info.idle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dprintk("actually kicking\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel(dev->rx_info.phy_descs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) (4 * DESC_SIZE * dev->rx_info.next_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev->base + RXDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dev->rx_info.next_rx == dev->rx_info.next_empty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __kick_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define start_tx_okay(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Packet Receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * The hardware supports linked lists of receive descriptors for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * which ownership is transferred back and forth by means of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * ownership bit. While the hardware does support the use of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * ring for receive descriptors, we only make use of a chain in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * an attempt to reduce bus traffic under heavy load scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * This will also make bugs a bit more obvious. The current code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * only makes use of a single rx chain; I hope to implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * priority based rx for version 1.0. Goal: even under overload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * conditions, still route realtime traffic with as low jitter as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) desc_addr_set(desc + DESC_LINK, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) desc_addr_set(desc + DESC_BUFPTR, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) desc[DESC_EXTSTS] = cpu_to_le32(extsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned next_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 cmdsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __le32 *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dma_addr_t buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) next_empty = dev->rx_info.next_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* don't overrun last rx marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (unlikely(nr_rx_empty(dev) <= 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev->rx_info.next_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev->rx_info.nr_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev->rx_info.next_rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev->rx_info.skbs[next_empty] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* update link of previous rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (likely(next_empty != dev->rx_info.next_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (unlikely(nr_rx_empty(dev) <= 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dprintk("rx_refill(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (gfp == GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) spin_lock_irqsave(&dev->rx_info.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) for (i=0; i<NR_RX_DESC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) long res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* extra 16 bytes for alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (gfp != GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spin_lock_irqsave(&dev->rx_info.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) res = ns83820_add_rx_skb(dev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (gfp != GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_unlock_irqrestore(&dev->rx_info.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (gfp == GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_unlock_irqrestore(&dev->rx_info.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return i ? 0 : -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void rx_refill_atomic(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rx_refill(ndev, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* REFILL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static inline void queue_refill(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct net_device *ndev = dev->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rx_refill(ndev, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (dev->rx_info.up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) kick_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void phy_intr(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 cfg, new_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 tanar, tanlpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int speed, fullduplex, newlinkstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (dev->CFG_cache & CFG_TBI_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 __maybe_unused tbisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* we have an optical transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tbisr = readl(dev->base + TBISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) tanar = readl(dev->base + TANAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tanlpar = readl(dev->base + TANLPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tbisr, tanar, tanlpar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (tanar & TANAR_FULL_DUP)) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* both of us are full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) writel(readl(dev->base + TXCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Light up full duplex LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev->base + GPIOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } else if (((tanlpar & TANAR_HALF_DUP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (tanar & TANAR_HALF_DUP)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ((tanlpar & TANAR_FULL_DUP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (tanar & TANAR_HALF_DUP)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ((tanlpar & TANAR_HALF_DUP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (tanar & TANAR_FULL_DUP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* one or both of us are half duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writel((readl(dev->base + TXCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Turn off full duplex LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev->base + GPIOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) speed = 4; /* 1000F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* we have a copper transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (cfg & CFG_SPDSTS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) new_cfg |= CFG_MODE_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) new_cfg &= ~CFG_MODE_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) speed = ((cfg / CFG_SPDSTS0) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fullduplex = (cfg & CFG_DUPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (fullduplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) new_cfg |= CFG_SB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel(readl(dev->base + TXCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) | TXCFG_CSI | TXCFG_HBI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel(readl(dev->base + TXCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) & ~(TXCFG_CSI | TXCFG_HBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if ((cfg & CFG_LNKSTS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ((new_cfg ^ dev->CFG_cache) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(new_cfg, dev->base + CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev->CFG_cache = new_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev->CFG_cache &= ~CFG_SPDSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev->CFG_cache |= cfg & CFG_SPDSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (newlinkstate & LINK_UP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev->linkstate != newlinkstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) speeds[speed],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fullduplex ? "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else if (newlinkstate & LINK_DOWN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev->linkstate != newlinkstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) printk(KERN_INFO "%s: link now down.\n", ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev->linkstate = newlinkstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int ns83820_setup_rx(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dprintk("ns83820_setup_rx(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev->rx_info.idle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev->rx_info.next_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev->rx_info.next_rx_desc = dev->rx_info.descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev->rx_info.next_empty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i=0; i<NR_RX_DESC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) clear_rx_desc(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writel(0, dev->base + RXDP_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel(dev->rx_info.phy_descs, dev->base + RXDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = rx_refill(ndev, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dprintk("starting receiver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* prevent the interrupt handler from stomping on us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_lock_irq(&dev->rx_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) writel(0x0001, dev->base + CCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel(0, dev->base + RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) writel(0x7fc00000, dev->base + RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(0xffc00000, dev->base + RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev->rx_info.up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) phy_intr(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Okay, let it rip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) spin_lock(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev->IMR_cache |= ISR_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev->IMR_cache |= ISR_RXRCMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) //dev->IMR_cache |= ISR_RXERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) //dev->IMR_cache |= ISR_RXOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev->IMR_cache |= ISR_RXORN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev->IMR_cache |= ISR_RXSOVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev->IMR_cache |= ISR_RXDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev->IMR_cache |= ISR_RXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev->IMR_cache |= ISR_TXDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->IMR_cache |= ISR_TXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) writel(1, dev->base + IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_unlock(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) kick_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) spin_unlock_irq(&dev->rx_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static void ns83820_cleanup_rx(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dprintk("ns83820_cleanup_rx(%p)\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* disable receive interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_lock_irqsave(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) spin_unlock_irqrestore(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* synchronize with the interrupt handler and kill it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev->rx_info.up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) synchronize_irq(dev->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* touch the pci bus... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) readl(dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* assumes the transmitter is already disabled and reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) writel(0, dev->base + RXDP_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) writel(0, dev->base + RXDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) for (i=0; i<NR_RX_DESC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct sk_buff *skb = dev->rx_info.skbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev->rx_info.skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) clear_rx_desc(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void ns83820_rx_kick(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (dev->rx_info.up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rx_refill_atomic(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) kick_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) schedule_work(&dev->tq_refill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) kick_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (dev->rx_info.idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) printk(KERN_DEBUG "%s: BAD\n", ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* rx_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void rx_irq(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct rx_info *info = &dev->rx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned next_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int rx_rc, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 cmdsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __le32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dprintk("rx_irq(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) readl(dev->base + RXDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) (long)(dev->rx_info.phy_descs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) (int)dev->rx_info.next_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (int)dev->rx_info.next_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!info->up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dprintk("walking descs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) next_rx = info->next_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) desc = info->next_rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (cmdsts != CMDSTS_OWN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dprintk("cmdsts: %08x\n", cmdsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dprintk("extsts: %08x\n", extsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) skb = info->skbs[next_rx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) info->skbs[next_rx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) info->next_rx = (next_rx + 1) % NR_RX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) clear_rx_desc(dev, next_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) len = cmdsts & CMDSTS_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* NH: As was mentioned below, this chip is kinda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * brain dead about vlan tag stripping. Frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * that are 64 bytes with a vlan header appended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * like arp frames, or pings, are flagged as Runts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * when the tag is stripped and hardware. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * also means that the OK bit in the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * is cleared when the frame comes in so we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * to do a specific length check here to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * the frame would have been ok, had we not stripped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * the tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (likely((CMDSTS_OK & cmdsts) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (likely(CMDSTS_OK & cmdsts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto netdev_mangle_me_harder_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (cmdsts & CMDSTS_DEST_MULTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ndev->stats.multicast++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ndev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ndev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) skb->protocol = eth_type_trans(skb, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if(extsts & EXTSTS_VPKT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned short tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) tag = ntohs(extsts & EXTSTS_VTG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) rx_rc = netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (NET_RX_DROP == rx_rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) netdev_mangle_me_harder_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ndev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_kfree_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) next_rx = info->next_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) desc = info->descs + (DESC_SIZE * next_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) info->next_rx = next_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (0 && !nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static void rx_action(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct ns83820 *dev = from_tasklet(dev, t, rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct net_device *ndev = dev->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rx_irq(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel(ihr, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) spin_lock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev->IMR_cache |= ISR_RXDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spin_unlock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) rx_irq(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ns83820_rx_kick(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Packet Transmit code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static inline void kick_tx(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev, dev->tx_idx, dev->tx_free_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) writel(CR_TXE, dev->base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* No spinlock needed on the transmit irq path as the interrupt handler is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * serialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void do_tx_done(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 cmdsts, tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __le32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dprintk("do_tx_done(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) tx_done_idx = dev->tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) while ((tx_done_idx != dev->tx_free_idx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (cmdsts & CMDSTS_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ndev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (cmdsts & CMDSTS_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ndev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (cmdsts & CMDSTS_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ndev->stats.tx_bytes += cmdsts & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) tx_done_idx, dev->tx_free_idx, cmdsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) skb = dev->tx_skbs[tx_done_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev->tx_skbs[tx_done_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dprintk("done(%p)\n", skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) len = cmdsts & CMDSTS_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) addr = desc_addr_get(desc + DESC_BUFPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dma_unmap_single(&dev->pci_dev->dev, addr, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) atomic_dec(&dev->nr_tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dma_unmap_page(&dev->pci_dev->dev, addr, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev->tx_done_idx = tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) desc[DESC_CMDSTS] = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Allow network stack to resume queueing packets after we've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * finished transmitting at least 1/4 of the packets in the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dprintk("start_queue(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static void ns83820_cleanup_tx(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) for (i=0; i<NR_TX_DESC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct sk_buff *skb = dev->tx_skbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev->tx_skbs[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dma_unmap_single(&dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) desc_addr_get(desc + DESC_BUFPTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_kfree_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) atomic_dec(&dev->nr_tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* transmit routine. This code relies on the network layer serializing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * its calls in, but will run happily in parallel with the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * handler. This code currently has provisions for fragmenting tx buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * while trying to track down a bug in either the zero copy code or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * the tx fifo (hence the MAX_FRAG_LEN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 free_idx, cmdsts, extsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int nr_free, nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) unsigned tx_done_idx, last_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dma_addr_t buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) skb_frag_t *frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int do_intr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) volatile __le32 *first_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dprintk("ns83820_hard_start_xmit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) nr_frags = skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (unlikely(dev->CFG_cache & CFG_LNKSTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) last_idx = free_idx = dev->tx_free_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) tx_done_idx = dev->tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) nr_free -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (nr_free <= nr_frags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dprintk("stop_queue - not enough(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Check again: we may have raced with a tx done irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (dev->tx_done_idx != tx_done_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dprintk("restart queue(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (free_idx == dev->tx_intr_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) do_intr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) nr_free -= nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (nr_free < MIN_TX_DESC_FREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dprintk("stop_queue - last entry(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) frag = skb_shinfo(skb)->frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!nr_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) frag = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) extsts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) extsts |= EXTSTS_IPPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (IPPROTO_TCP == ip_hdr(skb)->protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) extsts |= EXTSTS_TCPPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) extsts |= EXTSTS_UDPPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (skb_vlan_tag_present(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* fetch the vlan tag info out of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * ancillary data if the vlan code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * is using hw vlan acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) short tag = skb_vlan_tag_get(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) extsts |= (EXTSTS_VPKT | htons(tag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (nr_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) len -= skb->data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) (unsigned long long)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) last_idx = free_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) free_idx = (free_idx + 1) % NR_TX_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) desc_addr_set(desc + DESC_BUFPTR, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) desc[DESC_EXTSTS] = cpu_to_le32(extsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cmdsts |= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (!nr_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) skb_frag_size(frag), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) (long long)buf, (long) page_to_pfn(frag->page),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) frag->page_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) len = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) nr_frags--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dprintk("done pkt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) spin_lock_irq(&dev->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev->tx_skbs[last_idx] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev->tx_free_idx = free_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) atomic_inc(&dev->nr_tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) spin_unlock_irq(&dev->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) kick_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* Check again: we may have raced with a tx done irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static void ns83820_update_stats(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct net_device *ndev = dev->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 __iomem *base = dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* the DP83820 will freeze counters, so we need to read all of them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* somewhat overkill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spin_lock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ns83820_update_stats(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) spin_unlock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return &ndev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Let ethtool retrieve info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int ns83820_get_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u32 cfg, tbicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int fullduplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * Here's the list of available ethtool commands from other drivers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * cmd->advertising =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * ethtool_cmd_speed_set(cmd, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * cmd->duplex =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * cmd->port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * cmd->phy_address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * cmd->transceiver = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * cmd->autoneg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * cmd->maxtxpkt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * cmd->maxrxpkt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* read current configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) readl(dev->base + TANAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) tbicr = readl(dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) supported = SUPPORTED_Autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (dev->CFG_cache & CFG_TBI_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* we have optical interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) supported |= SUPPORTED_1000baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) SUPPORTED_1000baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SUPPORTED_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) cmd->base.port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* we have copper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) supported |= SUPPORTED_10baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) SUPPORTED_1000baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) SUPPORTED_MII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) cmd->base.port = PORT_MII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) switch (cfg / CFG_SPDSTS0 & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) cmd->base.speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) cmd->base.speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) cmd->base.speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* Let ethool change settings*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int ns83820_set_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 cfg, tanar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) int have_optical = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) int fullduplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* read current configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) tanar = readl(dev->base + TANAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (dev->CFG_cache & CFG_TBI_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* we have optical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) have_optical = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) fullduplex = (tanar & TANAR_FULL_DUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* we have copper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) fullduplex = cfg & CFG_DUPSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) spin_lock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) spin_lock(&dev->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Set duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (cmd->base.duplex != fullduplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (have_optical) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*set full duplex*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (cmd->base.duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* force full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) writel(readl(dev->base + TXCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Light up full duplex LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev->base + GPIOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*TODO: set half duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*we have copper*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* TODO: Set duplex for copper cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) printk(KERN_INFO "%s: Duplex set via ethtool\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Set autonegotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (cmd->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* restart auto negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev->linkstate = LINK_AUTONEGOTIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* disable auto negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) writel(0x00000000, dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) cmd->base.autoneg ? "ENABLED" : "DISABLED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) phy_intr(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) spin_unlock(&dev->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) spin_unlock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* end ethtool get/set support -df */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) strlcpy(info->driver, "ns83820", sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) strlcpy(info->version, VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static u32 ns83820_get_link(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return cfg & CFG_LNKSTS ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static const struct ethtool_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .get_drvinfo = ns83820_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .get_link = ns83820_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .get_link_ksettings = ns83820_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .set_link_ksettings = ns83820_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static inline void ns83820_disable_interrupts(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) writel(0, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) writel(0, dev->base + IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) readl(dev->base + IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* this function is called in irq context from the ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static void ns83820_mib_isr(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) spin_lock_irqsave(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ns83820_update_stats(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) spin_unlock_irqrestore(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static void ns83820_do_isr(struct net_device *ndev, u32 isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static irqreturn_t ns83820_irq(int foo, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct net_device *ndev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dprintk("ns83820_irq(%p)\n", ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev->ihr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) isr = readl(dev->base + ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dprintk("irq: %08x\n", isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ns83820_do_isr(ndev, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static void ns83820_do_isr(struct net_device *ndev, u32 isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) Dprintk("odd isr? 0x%08x\n", isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (ISR_RXIDLE & isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dev->rx_info.idle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) Dprintk("oh dear, we are idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ns83820_rx_kick(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if ((ISR_RXDESC | ISR_RXOK) & isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) prefetch(dev->rx_info.next_rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) spin_lock_irqsave(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) spin_unlock_irqrestore(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) tasklet_schedule(&dev->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) //rx_irq(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) //writel(4, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ns83820_rx_kick(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (unlikely(ISR_RXSOVR & isr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) //printk("overrun: rxsovr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ndev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (unlikely(ISR_RXORN & isr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) //printk("overrun: rxorn\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ndev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if ((ISR_RXRCMP & isr) && dev->rx_info.up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) writel(CR_RXE, dev->base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (ISR_TXIDLE & isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u32 txdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) txdp = readl(dev->base + TXDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dprintk("txdp: %08x\n", txdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) txdp -= dev->tx_phy_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev->tx_idx = txdp / (DESC_SIZE * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (dev->tx_idx >= NR_TX_DESC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* The may have been a race between a pci originated read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * and the descriptor update from the cpu. Just in case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * kick the transmitter if the hardware thinks it is on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * different descriptor than we are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (dev->tx_idx != dev->tx_free_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) kick_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Defer tx ring processing until more than a minimum amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * work has accumulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) spin_lock_irqsave(&dev->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) do_tx_done(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) spin_unlock_irqrestore(&dev->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Disable TxOk if there are no outstanding tx packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if ((dev->tx_done_idx == dev->tx_free_idx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) (dev->IMR_cache & ISR_TXOK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) spin_lock_irqsave(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev->IMR_cache &= ~ISR_TXOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) spin_unlock_irqrestore(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* The TxIdle interrupt can come in before the transmit has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * completed. Normally we reap packets off of the combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * of TxDesc and TxIdle and leave TxOk disabled (since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * occurs on every packet), but when no further irqs of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * nature are expected, we must enable TxOk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) spin_lock_irqsave(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev->IMR_cache |= ISR_TXOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) writel(dev->IMR_cache, dev->base + IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) spin_unlock_irqrestore(&dev->misc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* MIB interrupt: one of the statistics counters is about to overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (unlikely(ISR_MIB & isr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ns83820_mib_isr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* PHY: Link up/down/negotiation state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (unlikely(ISR_PHY & isr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) phy_intr(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #if 0 /* Still working on the interrupt mitigation strategy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (dev->ihr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) writel(dev->ihr, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static void ns83820_do_reset(struct ns83820 *dev, u32 which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) Dprintk("resetting chip...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) writel(which, dev->base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) } while (readl(dev->base + CR) & which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) Dprintk("okay!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static int ns83820_stop(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* FIXME: protect against interrupt handler? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) del_timer_sync(&dev->tx_watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ns83820_disable_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev->rx_info.up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) synchronize_irq(dev->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ns83820_do_reset(dev, CR_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) synchronize_irq(dev->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) spin_lock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_unlock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ns83820_cleanup_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ns83820_cleanup_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static void ns83820_tx_timeout(struct net_device *ndev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u32 tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) __le32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spin_lock_irqsave(&dev->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) tx_done_idx = dev->tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #if defined(DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) isr = readl(dev->base + ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ns83820_do_isr(ndev, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) do_tx_done(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) tx_done_idx = dev->tx_done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_unlock_irqrestore(&dev->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static void ns83820_tx_watch(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct ns83820 *dev = from_timer(dev, t, tx_watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct net_device *ndev = dev->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #if defined(DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) printk("ns83820_tx_watch: %u %u %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev->tx_done_idx != dev->tx_free_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev->tx_done_idx, dev->tx_free_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) atomic_read(&dev->nr_tx_skbs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ns83820_tx_timeout(ndev, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static int ns83820_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) u32 desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dprintk("ns83820_open\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) writel(0, dev->base + PQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = ns83820_setup_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) for (i=0; i<NR_TX_DESC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dev->tx_phy_descs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) dev->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dev->tx_done_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) desc = dev->tx_phy_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) writel(0, dev->base + TXDP_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) writel(desc, dev->base + TXDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) netif_start_queue(ndev); /* FIXME: wait for phy to come up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ns83820_stop(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) for (i=0; i<3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Read from the perfect match memory: this is loaded by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * the chip from the EEPROM via the EELOAD self test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) writel(i*2, dev->base + RFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) data = readl(dev->base + RFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) *mac++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) *mac++ = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static void ns83820_set_multicast(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u8 __iomem *rfcr = dev->base + RFCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u32 and_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u32 or_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (ndev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) or_mask |= RFCR_AAU | RFCR_AAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) and_mask &= ~(RFCR_AAU | RFCR_AAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) or_mask |= RFCR_AAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) and_mask &= ~RFCR_AAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) spin_lock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) val = (readl(rfcr) & and_mask) | or_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) writel(val & ~RFCR_RFEN, rfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) writel(val, rfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) spin_unlock_irq(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) int timed_out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) dprintk("%s: start %s\n", ndev->name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) writel(enable, dev->base + PTSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) status = readl(dev->base + PTSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (!(status & enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (status & done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (status & fail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (time_after_eq(jiffies, start + HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) timed_out = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (status & fail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ndev->name, name, status, fail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) else if (timed_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ndev->name, name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #ifdef PHY_CODE_IS_FINISHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* drive MDC low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) dev->MEAR_cache &= ~MEAR_MDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) writel(dev->MEAR_cache, dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) readl(dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* enable output, set bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) dev->MEAR_cache |= MEAR_MDDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev->MEAR_cache |= MEAR_MDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev->MEAR_cache &= ~MEAR_MDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* set the output bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) writel(dev->MEAR_cache, dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) readl(dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* drive MDC high causing the data bit to be latched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) dev->MEAR_cache |= MEAR_MDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) writel(dev->MEAR_cache, dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) readl(dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Wait again... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static int ns83820_mii_read_bit(struct ns83820 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* drive MDC low, disable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev->MEAR_cache &= ~MEAR_MDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev->MEAR_cache &= ~MEAR_MDDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) writel(dev->MEAR_cache, dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) readl(dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* drive MDC high causing the data bit to be latched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) dev->MEAR_cache |= MEAR_MDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) writel(dev->MEAR_cache, dev->base + MEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Wait again... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) unsigned data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* read some garbage so that we eventually sync up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) for (i=0; i<64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ns83820_mii_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ns83820_mii_write_bit(dev, 0); /* start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ns83820_mii_write_bit(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ns83820_mii_write_bit(dev, 1); /* opcode read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ns83820_mii_write_bit(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* write out the phy address: 5 bits, msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) for (i=0; i<5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ns83820_mii_write_bit(dev, phy & (0x10 >> i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* write out the register address, 5 bits, msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) for (i=0; i<5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ns83820_mii_write_bit(dev, reg & (0x10 >> i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ns83820_mii_read_bit(dev); /* turn around cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ns83820_mii_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* read in the register data, 16 bits msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) for (i=0; i<16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) data <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) data |= ns83820_mii_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* read some garbage so that we eventually sync up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) for (i=0; i<64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ns83820_mii_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ns83820_mii_write_bit(dev, 0); /* start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ns83820_mii_write_bit(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ns83820_mii_write_bit(dev, 0); /* opcode read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ns83820_mii_write_bit(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* write out the phy address: 5 bits, msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) for (i=0; i<5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ns83820_mii_write_bit(dev, phy & (0x10 >> i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* write out the register address, 5 bits, msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) for (i=0; i<5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ns83820_mii_write_bit(dev, reg & (0x10 >> i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ns83820_mii_read_bit(dev); /* turn around cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ns83820_mii_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* read in the register data, 16 bits msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) for (i=0; i<16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static void ns83820_probe_phy(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct ns83820 *dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) unsigned a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) for (j = 0; j < 0x16; j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ndev->name, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ns83820_mii_read_reg(dev, 1, 0 + j),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ns83820_mii_read_reg(dev, 1, 1 + j),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ns83820_mii_read_reg(dev, 1, 2 + j),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ns83820_mii_read_reg(dev, 1, 3 + j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* read firmware version: memory addr is 0x8402 and 0x8403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) a = ns83820_mii_read_reg(dev, 1, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) b = ns83820_mii_read_reg(dev, 1, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dprintk("version: 0x%04x 0x%04x\n", a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const struct net_device_ops netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .ndo_open = ns83820_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .ndo_stop = ns83820_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .ndo_start_xmit = ns83820_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .ndo_get_stats = ns83820_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .ndo_set_rx_mode = ns83820_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .ndo_tx_timeout = ns83820_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static int ns83820_init_one(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct ns83820 *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* See if we can set the dma mask early on; failure is fatal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (sizeof(dma_addr_t) == 8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) using_dac = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ndev = alloc_etherdev(sizeof(struct ns83820));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (!ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) dev = PRIV(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) spin_lock_init(&dev->rx_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) spin_lock_init(&dev->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) spin_lock_init(&dev->misc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) dev->pci_dev = pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) SET_NETDEV_DEV(ndev, &pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) INIT_WORK(&dev->tq_refill, queue_refill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) tasklet_setup(&dev->rx_tasklet, rx_action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) err = pci_enable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) pci_set_master(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) addr = pci_resource_start(pci_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dev->base = ioremap(addr, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) 4 * DESC_SIZE * NR_TX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) &dev->tx_phy_descs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) 4 * DESC_SIZE * NR_RX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) &dev->rx_info.phy_descs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) dprintk("%p: %08lx %p: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev->tx_descs, (long)dev->tx_phy_descs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dev->rx_info.descs, (long)dev->rx_info.phy_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ns83820_disable_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev->IMR_cache = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) DRV_NAME, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) pci_dev->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * FIXME: we are holding rtnl_lock() over obscenely long area only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * because some of the setup code uses dev->name. It's Wrong(tm) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * we should be using driver-specific names for all that stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * For now that will do, but we really need to come back and kill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * most of the dev_alloc_name() users later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) err = dev_alloc_name(ndev, ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pci_dev->subsystem_vendor, pci_dev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ndev->netdev_ops = &netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ndev->ethtool_ops = &ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ndev->watchdog_timeo = 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pci_set_drvdata(pci_dev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ns83820_do_reset(dev, CR_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) /* Must reset the ram bist before running it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) writel(PTSCR_RBIST_RST, dev->base + PTSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) PTSCR_EEBIST_FAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* I love config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) dev->CFG_cache = readl(dev->base + CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if ((dev->CFG_cache & CFG_PCI64_DET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /*dev->CFG_cache |= CFG_DATA64_EN;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (!(dev->CFG_cache & CFG_DATA64_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dev->CFG_cache &= ~(CFG_DATA64_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) CFG_M64ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) dev->CFG_cache |= CFG_REQALG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) dev->CFG_cache |= CFG_POW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) dev->CFG_cache |= CFG_TMRTEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* When compiled with 64 bit addressing, we must always enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * the 64 bit descriptor format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (sizeof(dma_addr_t) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) dev->CFG_cache |= CFG_M64ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (using_dac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dev->CFG_cache |= CFG_T64ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /* Big endian mode does not seem to do what the docs suggest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) dev->CFG_cache &= ~CFG_BEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* setup optical transceiver if we have one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (dev->CFG_cache & CFG_TBI_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) printk(KERN_INFO "%s: enabling optical transceiver\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* setup auto negotiation feature advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) writel(readl(dev->base + TANAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) | TANAR_HALF_DUP | TANAR_FULL_DUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) dev->base + TANAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* start auto negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dev->linkstate = LINK_AUTONEGOTIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dev->CFG_cache |= CFG_MODE_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) writel(dev->CFG_cache, dev->base + CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) dprintk("CFG: %08x\n", dev->CFG_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (reset_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) printk(KERN_INFO "%s: resetting phy\n", ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) writel(dev->CFG_cache, dev->base + CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #if 0 /* Huh? This sets the PCI latency register. Should be done via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * the PCI layer. FIXME.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (readl(dev->base + SRR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* Note! The DMA burst size interacts with packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * transmission, such that the largest packet that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) * can be transmitted is 8192 - FLTH - burst size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) * If only the transmit fifo was larger...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /* Ramit : 1024 DMA is not a good idea, it ends up banging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * some DELL and COMPAQ SMP systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) | ((1600 / 32) * 0x100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) dev->base + TXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* Flush the interrupt holdoff timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) writel(0x000, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) writel(0x100, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) writel(0x000, dev->base + IHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* Set Rx to full duplex, don't accept runt, errored, long or length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) * range errored packets. Use 512 byte DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* Ramit : 1024 DMA is not a good idea, it ends up banging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * some DELL and COMPAQ SMP systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * Turn on ALP, only we are accpeting Jumbo Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) | RXCFG_STRIPCRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) //| RXCFG_ALP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* Disable priority queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) writel(0, dev->base + PQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* Enable IP checksum validation and detetion of VLAN headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) * Note: do not set the reject options as at least the 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) * revision of the chip does not properly accept IP fragments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) * at least for UDP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) * the MAC it calculates the packetsize AFTER stripping the VLAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) * header, and if a VLAN Tagged packet of 64 bytes is received (like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) * a ping with a VLAN header) then the card, strips the 4 byte VLAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * it discrards it!. These guys......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * also turn on tag stripping if hardware acceleration is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) writel(VRCR_INIT_VALUE, dev->base + VRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /* Enable per-packet TCP/UDP/IP checksumming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * and per packet vlan tag insertion if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * vlan hardware acceleration is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define VTCR_INIT_VALUE VTCR_PPCHK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) writel(VTCR_INIT_VALUE, dev->base + VTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* Ramit : Enable async and sync pause frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /* writel(0, dev->base + PCR); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) dev->base + PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* Disable Wake On Lan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) writel(0, dev->base + WCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ns83820_getmac(dev, ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /* Yes, we support dumb IP checksum on transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ndev->features |= NETIF_F_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ndev->features |= NETIF_F_IP_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ndev->min_mtu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #ifdef NS83820_VLAN_ACCEL_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) /* We also support hardware vlan acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (using_dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) printk(KERN_INFO "%s: using 64 bit addressing.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ndev->features |= NETIF_F_HIGHDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) (unsigned)readl(dev->base + SRR) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) (unsigned)readl(dev->base + SRR) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ndev->dev_addr, addr, pci_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #ifdef PHY_CODE_IS_FINISHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ns83820_probe_phy(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) err = register_netdevice(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) goto out_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) out_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ns83820_disable_interrupts(dev); /* paranoia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) free_irq(pci_dev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) if (dev->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) iounmap(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) dev->tx_descs, dev->tx_phy_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) dev->rx_info.descs, dev->rx_info.phy_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) pci_disable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static void ns83820_remove_one(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) struct net_device *ndev = pci_get_drvdata(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) if (!ndev) /* paranoia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) ns83820_disable_interrupts(dev); /* paranoia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) free_irq(dev->pci_dev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) iounmap(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) dev->tx_descs, dev->tx_phy_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) dev->rx_info.descs, dev->rx_info.phy_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) pci_disable_device(dev->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static const struct pci_device_id ns83820_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static struct pci_driver driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .name = "ns83820",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .id_table = ns83820_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .probe = ns83820_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .remove = ns83820_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #if 0 /* FIXME: implement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .suspend = ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .resume = ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static int __init ns83820_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) return pci_register_driver(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static void __exit ns83820_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) pci_unregister_driver(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) module_param(lnksts, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) module_param(ihr, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) module_param(reset_phy, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) module_init(ns83820_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) module_exit(ns83820_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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