^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_OCELOT_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_OCELOT_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/net_tstamp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/mscc/ocelot_qsys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/mscc/ocelot_sys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <soc/mscc/ocelot_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <soc/mscc/ocelot_ana.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <soc/mscc/ocelot_ptp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <soc/mscc/ocelot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ocelot_rew.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "ocelot_qs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OCELOT_BUFFER_CELL_SZ 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OCELOT_PTP_QUEUE_SZ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct frame_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 tag_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 rew_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 timestamp; /* rew_val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ocelot_multicast {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int pgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ocelot_port_tc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool block_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long offload_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long police_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ocelot_port_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ocelot_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct phy_device *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 chip_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct phy *serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ocelot_port_tc tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct ocelot_dump_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct netlink_callback *cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MAC table entry types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * ENTRYTYPE_NORMAL is subject to aging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * ENTRYTYPE_LOCKED is not subject to aging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum macaccess_entry_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ENTRYTYPE_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ENTRYTYPE_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ENTRYTYPE_MACv4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ENTRYTYPE_MACv6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool is_static, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ocelot_mact_learn(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const unsigned char mac[ETH_ALEN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int vid, enum macaccess_entry_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ocelot_mact_forget(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const unsigned char mac[ETH_ALEN], unsigned int vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ocelot_port_lag_join(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct net_device *bond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct net_device *bond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct net_device *ocelot_port_to_netdev(struct ocelot *ocelot, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ocelot_netdev_to_port(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ocelot_probe_port(struct ocelot *ocelot, int port, struct regmap *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct phy_device *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum ocelot_tag_prefix injection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum ocelot_tag_prefix extraction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern struct notifier_block ocelot_netdevice_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern struct notifier_block ocelot_switchdev_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern struct notifier_block ocelot_switchdev_blocking_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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