^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/if_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <soc/mscc/ocelot_vcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "ocelot.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ocelot_vcap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TABLE_UPDATE_SLEEP_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TABLE_UPDATE_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct ocelot_mact_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum macaccess_entry_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return readx_poll_timeout(ocelot_mact_read_macaccess,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ocelot, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MACACCESS_CMD_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void ocelot_mact_select(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const unsigned char mac[ETH_ALEN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 macl = 0, mach = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Set the MAC address to handle and the vlan associated in a format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * understood by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mach |= vid << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mach |= mac[0] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mach |= mac[1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) macl |= mac[2] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) macl |= mac[3] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) macl |= mac[4] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) macl |= mac[5] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ocelot_mact_learn(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const unsigned char mac[ETH_ALEN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int vid, enum macaccess_entry_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 cmd = ANA_TABLES_MACACCESS_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ANA_TABLES_MACACCESS_DEST_IDX(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int mc_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (type == ENTRYTYPE_MACv4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mc_ports = (mac[1] << 8) | mac[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else if (type == ENTRYTYPE_MACv6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mc_ports = (mac[0] << 8) | mac[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mc_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (mc_ports & BIT(ocelot->num_phys_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ocelot_mact_select(ocelot, mac, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Issue a write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ocelot_mact_wait_for_completion(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) EXPORT_SYMBOL(ocelot_mact_learn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ocelot_mact_forget(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const unsigned char mac[ETH_ALEN], unsigned int vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ocelot_mact_select(ocelot, mac, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Issue a forget command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ocelot_write(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ocelot_mact_wait_for_completion(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXPORT_SYMBOL(ocelot_mact_forget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void ocelot_mact_init(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Configure the learning mode entries attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - Do not copy the frame to the CPU extraction queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * - Use the vlan and mac_cpoy for dmac lookup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ocelot_rmw(ocelot, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | ANA_AGENCTRL_LEARN_FWD_KILL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ANA_AGENCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Clear the MAC table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ANA_PORT_VCAP_S2_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ANA_PORT_VCAP_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) REW_PORT_CFG_ES0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) REW_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ANA_TABLES_VLANACCESS_CMD_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Select the VID to configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ANA_TABLES_VLANTIDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Set the vlan port members mask and issue a write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ANA_TABLES_VLANACCESS_CMD_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ANA_TABLES_VLANACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ocelot_vlant_wait_for_completion(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ocelot_port->vid != vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Always permit deleting the native VLAN (vid = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ocelot_port->vid && vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "Port already has a native VLAN: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ocelot_port->vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ocelot_port->vid = vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) REW_PORT_VLAN_CFG_PORT_VID_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REW_PORT_VLAN_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ocelot_port->vlan_aware && !ocelot_port->vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* If port is vlan-aware and tagged, drop untagged and priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * tagged frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ocelot_rmw_gix(ocelot, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ANA_PORT_DROP_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ocelot_port->vlan_aware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ocelot_port->vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Tag all frames except when VID == DEFAULT_VLAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val = REW_TAG_CFG_TAG_CFG(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Tag all frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = REW_TAG_CFG_TAG_CFG(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Port tagging disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = REW_TAG_CFG_TAG_CFG(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ocelot_rmw_gix(ocelot, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) REW_TAG_CFG_TAG_CFG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) REW_TAG_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bool vlan_aware, struct switchdev_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (switchdev_trans_ph_prepare(trans)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct ocelot_vcap_filter *filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) list_for_each_entry(filter, &block->rules, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (filter->ingress_port_mask & BIT(port) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) filter->action.vid_replace_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "Cannot change VLAN state with vlan modify rules active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ocelot_port->vlan_aware = vlan_aware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (vlan_aware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ocelot_rmw_gix(ocelot, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ANA_PORT_VLAN_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EXPORT_SYMBOL(ocelot_port_vlan_filtering);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Default vlan to clasify for untagged frames (may be zero) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ocelot_rmw_gix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ANA_PORT_VLAN_CFG_VLAN_VID_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ANA_PORT_VLAN_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ocelot_port->pvid = pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bool untagged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Make the port a member of the VLAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ocelot->vlan_mask[vid] |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Default ingress vlan classification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (pvid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ocelot_port_set_pvid(ocelot, port, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Untagged egress vlan clasification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (untagged) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = ocelot_port_set_native_vlan(ocelot, port, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EXPORT_SYMBOL(ocelot_vlan_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Stop the port from being a member of the vlan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ocelot->vlan_mask[vid] &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Ingress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ocelot_port->pvid == vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ocelot_port_set_pvid(ocelot, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Egress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ocelot_port->vid == vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ocelot_port_set_native_vlan(ocelot, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EXPORT_SYMBOL(ocelot_vlan_del);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void ocelot_vlan_init(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 port, vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Clear VLAN table, by default all ports are members of all VLANs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ANA_TABLES_VLANACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ocelot_vlant_wait_for_completion(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Configure the port VLAN memberships */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (vid = 1; vid < VLAN_N_VID; vid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ocelot->vlan_mask[vid] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Because VLAN filtering is enabled, we need VID 0 to get untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * traffic. It is added automatically if 8021q module is loaded, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * we can't rely on it since module may be not loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Set vlan ingress filter mask to all ports but the CPU port by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ANA_VLANMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (port = 0; port < ocelot->num_phys_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ocelot_port_flush(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int pause_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int err, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Disable dequeuing from the egress queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) QSYS_PORT_MODE_DEQUEUE_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) QSYS_PORT_MODE, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Disable flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Disable priority flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ocelot_fields_write(ocelot, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Wait at least the time it takes to receive a frame of maximum length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * at the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Worst-case delays for 10 kilobyte jumbo frames are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * 8 ms on a 10M port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * 800 μs on a 100M port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * 80 μs on a 1G port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * 32 μs on a 2.5G port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) usleep_range(8000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Disable half duplex backpressure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SYS_FRONT_PORT_MODE, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Flush the queues associated with the port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) REW_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Enable dequeuing from the egress queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Wait until flushing is complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 100, 2000000, false, ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Clear flushing again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Re-enable flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) EXPORT_SYMBOL(ocelot_port_flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void ocelot_adjust_link(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int speed, mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (phydev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) speed = OCELOT_SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) speed = OCELOT_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) speed = OCELOT_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case SPEED_2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) speed = OCELOT_SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) port, phydev->speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) phy_print_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!phydev->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Only full duplex supported for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mode, DEV_MAC_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Disable HDX fast control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DEV_PORT_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* SGMII only for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PCS1G_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Enable PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* No aneg on SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* No loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Enable MAC module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DEV_CLOCK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* No PFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ANA_PFC_PFC_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Core: Enable port for frame transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ocelot_fields_write(ocelot, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SYS_MAC_FC_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) EXPORT_SYMBOL(ocelot_adjust_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void ocelot_port_enable(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct phy_device *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Enable receiving frames on the port, and activate auto-learning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * MAC addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ANA_PORT_PORT_CFG_RECV_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ANA_PORT_PORT_CFG_PORTID_VAL(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) EXPORT_SYMBOL(ocelot_port_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) void ocelot_port_disable(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXPORT_SYMBOL(ocelot_port_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct sk_buff *clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_lock(&ocelot_port->ts_id_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Store timestamp ID in cb[0] of sk_buff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clone->cb[0] = ocelot_port->ts_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) skb_queue_tail(&ocelot_port->tx_skbs, clone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spin_unlock(&ocelot_port->ts_id_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Read current PTP time to get seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Read packet HW timestamp from FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Sec has incremented since the ts was registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ts->tv_sec--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) void ocelot_get_txtstamp(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int budget = OCELOT_PTP_QUEUE_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) while (budget--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct skb_shared_hwtstamps shhwtstamps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct ocelot_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct timespec64 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 val, id, txport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val = ocelot_read(ocelot, SYS_PTP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Check if a timestamp can be retrieved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Retrieve the ts ID and Tx port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Retrieve its associated skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) port = ocelot->ports[txport];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) spin_lock_irqsave(&port->tx_skbs.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (skb->cb[0] != id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __skb_unlink(skb, &port->tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) skb_match = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (WARN_ON(!skb_match))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Get the h/w timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ocelot_get_hwtimestamp(ocelot, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Set the timestamp into the skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) memset(&shhwtstamps, 0, sizeof(shhwtstamps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) skb_complete_tx_timestamp(skb_match, &shhwtstamps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Next ts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) EXPORT_SYMBOL(ocelot_get_txtstamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ocelot_fdb_add(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int pgid = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (port == ocelot->npi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pgid = PGID_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!ocelot_port->vlan_aware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* If the bridge is not VLAN aware and no VID was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * provided, set it to pvid to ensure the MAC entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * matches incoming untagged packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) vid = ocelot_port->pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* If the bridge is VLAN aware a VID must be provided as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * otherwise the learnt entry wouldn't match any frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) EXPORT_SYMBOL(ocelot_fdb_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int ocelot_fdb_del(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ocelot_mact_forget(ocelot, addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) EXPORT_SYMBOL(ocelot_fdb_del);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) bool is_static, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ocelot_dump_ctx *dump = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 portid = NETLINK_CB(dump->cb->skb).portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 seq = dump->cb->nlh->nlmsg_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct nlmsghdr *nlh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct ndmsg *ndm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (dump->idx < dump->cb->args[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) sizeof(*ndm), NLM_F_MULTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!nlh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ndm = nlmsg_data(nlh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ndm->ndm_family = AF_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ndm->ndm_pad1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ndm->ndm_pad2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ndm->ndm_flags = NTF_SELF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ndm->ndm_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ndm->ndm_ifindex = dump->dev->ifindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto nla_put_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto nla_put_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) nlmsg_end(dump->skb, nlh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dump->idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) nla_put_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) nlmsg_cancel(dump->skb, nlh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct ocelot_mact_entry *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 val, dst, macl, mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) char mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Set row and column to read from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Issue a read command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ocelot_write(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (ocelot_mact_wait_for_completion(ocelot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Read the entry flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!(val & ANA_TABLES_MACACCESS_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* If the entry read has another port configured as its destination,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * do not report it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (dst != port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Get the entry's MAC address and VLAN id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mac[0] = (mach >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mac[1] = (mach >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mac[2] = (macl >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mac[3] = (macl >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mac[4] = (macl >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mac[5] = (macl >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) entry->vid = (mach >> 16) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ether_addr_copy(entry->mac, mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ocelot_fdb_dump(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dsa_fdb_dump_cb_t *cb, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Loop through all the mac tables entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) for (i = 0; i < ocelot->num_mact_rows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct ocelot_mact_entry entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bool is_static;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = ocelot_mact_read(ocelot, port, i, j, &entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* If the entry is invalid (wrong port, invalid...),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * skip it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) is_static = (entry.type == ENTRYTYPE_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = cb(entry.mac, entry.vid, is_static, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) EXPORT_SYMBOL(ocelot_fdb_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) EXPORT_SYMBOL(ocelot_hwstamp_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct hwtstamp_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* reserved for future extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (cfg.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Tx type sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (cfg.tx_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case HWTSTAMP_TX_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case HWTSTAMP_TX_ONESTEP_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * need to update the origin time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case HWTSTAMP_TX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ocelot_port->ptp_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_lock(&ocelot->ptp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) switch (cfg.rx_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case HWTSTAMP_FILTER_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case HWTSTAMP_FILTER_PTP_V2_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case HWTSTAMP_FILTER_PTP_V2_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_unlock(&ocelot->ptp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Commit back the result & save it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mutex_unlock(&ocelot->ptp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) EXPORT_SYMBOL(ocelot_hwstamp_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (sset != ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (i = 0; i < ocelot->num_stats; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) EXPORT_SYMBOL(ocelot_get_strings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Caller must hold &ocelot->stats_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static void ocelot_update_stats(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) for (i = 0; i < ocelot->num_phys_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Configure the port to read the stats from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) for (j = 0; j < ocelot->num_stats; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int idx = i * ocelot->num_stats + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ocelot->stats_layout[j].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (val < (ocelot->stats[idx] & U32_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ocelot->stats[idx] += (u64)1 << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ocelot->stats[idx] = (ocelot->stats[idx] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ~(u64)U32_MAX) + val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void ocelot_check_stats_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct delayed_work *del_work = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct ocelot *ocelot = container_of(del_work, struct ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) stats_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_lock(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ocelot_update_stats(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_unlock(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) OCELOT_STATS_CHECK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mutex_lock(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* check and update now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ocelot_update_stats(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Copy all counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = 0; i < ocelot->num_stats; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) *data++ = ocelot->stats[port * ocelot->num_stats + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) mutex_unlock(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) EXPORT_SYMBOL(ocelot_get_ethtool_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (sset != ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ocelot->num_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) EXPORT_SYMBOL(ocelot_get_sset_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ocelot_get_ts_info(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct ethtool_ts_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) info->phc_index = ocelot->ptp_clock ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ptp_clock_index(ocelot->ptp_clock) : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (info->phc_index == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SOF_TIMESTAMPING_RX_SOFTWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SOF_TIMESTAMPING_SOFTWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SOF_TIMESTAMPING_RX_SOFTWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SOF_TIMESTAMPING_SOFTWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SOF_TIMESTAMPING_TX_HARDWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SOF_TIMESTAMPING_RX_HARDWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SOF_TIMESTAMPING_RAW_HARDWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) BIT(HWTSTAMP_TX_ONESTEP_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) EXPORT_SYMBOL(ocelot_get_ts_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int p, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (!(BIT(port) & ocelot->bridge_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case BR_STATE_FORWARDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ocelot->bridge_fwd_mask |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case BR_STATE_LEARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ocelot->bridge_fwd_mask &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Apply FWD mask. The loop is needed to add/remove the current port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * a source for the other ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) for (p = 0; p < ocelot->num_phys_ports; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ocelot->bridge_fwd_mask & BIT(p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) for (i = 0; i < ocelot->num_phys_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned long bond_mask = ocelot->lags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!bond_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (bond_mask & BIT(p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mask &= ~bond_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ocelot_write_rix(ocelot, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ANA_PGID_PGID, PGID_SRC + p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ocelot_write_rix(ocelot, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ANA_PGID_PGID, PGID_SRC + p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Setting AGE_PERIOD to zero effectively disables automatic aging,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * which is clearly not what our intention is. So avoid that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!age_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) age_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) EXPORT_SYMBOL(ocelot_set_ageing_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) const unsigned char *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct ocelot_multicast *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) list_for_each_entry(mc, &ocelot->multicast, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ENTRYTYPE_MACv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (addr[0] == 0x33 && addr[1] == 0x33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ENTRYTYPE_MACv6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ENTRYTYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int ocelot_mdb_get_pgid(struct ocelot *ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) enum macaccess_entry_type entry_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int pgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * destination mask table (PGID), the destination set is programmed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * part of the entry MAC address.", and the DEST_IDX is set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (entry_type == ENTRYTYPE_MACv4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) entry_type == ENTRYTYPE_MACv6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct ocelot_multicast *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) bool used = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) list_for_each_entry(mc, &ocelot->multicast, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (mc->pgid == pgid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) used = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return pgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void ocelot_encode_ports_to_mdb(unsigned char *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct ocelot_multicast *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) enum macaccess_entry_type entry_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) memcpy(addr, mc->addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (entry_type == ENTRYTYPE_MACv4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) addr[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) addr[1] = mc->ports >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) addr[2] = mc->ports & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) } else if (entry_type == ENTRYTYPE_MACv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) addr[0] = mc->ports >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) addr[1] = mc->ports & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) const struct switchdev_obj_port_mdb *mdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) enum macaccess_entry_type entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) unsigned char addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct ocelot_multicast *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u16 vid = mdb->vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) bool new = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (port == ocelot->npi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) port = ocelot->num_phys_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) vid = ocelot_port->pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) entry_type = ocelot_classify_mdb(mdb->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!mc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int pgid = ocelot_mdb_get_pgid(ocelot, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (pgid < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "No more PGIDs available for mdb %pM vid %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mdb->addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) memcpy(mc->addr, mdb->addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mc->vid = vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) mc->pgid = pgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) list_add_tail(&mc->list, &ocelot->multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) new = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ocelot_encode_ports_to_mdb(addr, mc, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ocelot_mact_forget(ocelot, addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mc->ports |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ocelot_encode_ports_to_mdb(addr, mc, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) EXPORT_SYMBOL(ocelot_port_mdb_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) const struct switchdev_obj_port_mdb *mdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) enum macaccess_entry_type entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned char addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct ocelot_multicast *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u16 vid = mdb->vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (port == ocelot->npi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) port = ocelot->num_phys_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) vid = ocelot_port->pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) entry_type = ocelot_classify_mdb(mdb->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ocelot_encode_ports_to_mdb(addr, mc, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ocelot_mact_forget(ocelot, addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mc->ports &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!mc->ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) list_del(&mc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) devm_kfree(ocelot->dev, mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ocelot_encode_ports_to_mdb(addr, mc, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) EXPORT_SYMBOL(ocelot_port_mdb_del);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct net_device *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!ocelot->bridge_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ocelot->hw_bridge_dev = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (ocelot->hw_bridge_dev != bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* This is adding the port to a second bridge, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ocelot->bridge_mask |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) EXPORT_SYMBOL(ocelot_port_bridge_join);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct net_device *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct switchdev_trans trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ocelot->bridge_mask &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!ocelot->bridge_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ocelot->hw_bridge_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) trans.ph_prepare = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) trans.ph_prepare = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ocelot_port_set_pvid(ocelot, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ocelot_port_set_native_vlan(ocelot, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) EXPORT_SYMBOL(ocelot_port_bridge_leave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) int i, port, lag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Reset destination and aggregation PGIDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) for_each_unicast_dest_pgid(ocelot, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) for_each_aggr_pgid(ocelot, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ANA_PGID_PGID, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Now, set PGIDs for each LAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned long bond_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int aggr_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u8 aggr_idx[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) bond_mask = ocelot->lags[lag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!bond_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) // Destination mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ocelot_write_rix(ocelot, bond_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ANA_PGID_PGID, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) aggr_idx[aggr_count] = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) aggr_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) for_each_aggr_pgid(ocelot, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u32 ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ac &= ~bond_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ac |= BIT(aggr_idx[i % aggr_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) unsigned long bond_mask = ocelot->lags[lag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) unsigned int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Use lag port as logical port for port i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ocelot_write_gix(ocelot, port_cfg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ANA_PORT_PORT_CFG_PORTID_VAL(lag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ANA_PORT_PORT_CFG, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int ocelot_port_lag_join(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct net_device *bond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u32 bond_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int lag, lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) for_each_netdev_in_bond_rcu(bond, ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct ocelot_port_private *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) bond_mask |= BIT(priv->chip_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) lp = __ffs(bond_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* If the new port is the lowest one, use it as the logical port from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * now on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (port == lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) lag = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ocelot->lags[port] = bond_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) bond_mask &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (bond_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) lp = __ffs(bond_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ocelot->lags[lp] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) lag = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ocelot->lags[lp] |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ocelot_setup_lag(ocelot, lag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ocelot_set_aggr_pgids(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) EXPORT_SYMBOL(ocelot_port_lag_join);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct net_device *bond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) u32 port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Remove port from any lag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) for (i = 0; i < ocelot->num_phys_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ocelot->lags[i] &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* if it was the logical port of the lag, move the lag config to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * next port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ocelot->lags[port]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int n = __ffs(ocelot->lags[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ocelot->lags[n] = ocelot->lags[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ocelot->lags[port] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ocelot_setup_lag(ocelot, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ocelot_set_aggr_pgids(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) EXPORT_SYMBOL(ocelot_port_lag_leave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * In the special case that it's the NPI port that we're configuring, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * length of the tag and optional prefix needs to be accounted for privately,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * in order to be able to sustain communication at the requested @sdu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int pause_start, pause_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int atop, atop_tot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (port == ocelot->npi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) maxlen += OCELOT_TAG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) maxlen += OCELOT_SHORT_PREFIX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) maxlen += OCELOT_LONG_PREFIX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* Set Pause watermark hysteresis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pause_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) pause_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Tail dropping watermarks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) OCELOT_BUFFER_CELL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) EXPORT_SYMBOL(ocelot_port_set_maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (port == ocelot->npi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) max_mtu -= OCELOT_TAG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) max_mtu -= OCELOT_SHORT_PREFIX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) max_mtu -= OCELOT_LONG_PREFIX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return max_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) EXPORT_SYMBOL(ocelot_get_max_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) void ocelot_init_port(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) skb_queue_head_init(&ocelot_port->tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) spin_lock_init(&ocelot_port->ts_id_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Basic L2 initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Set MAC IFG Gaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) DEV_MAC_IFG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Load seed (0) and set MAC HDX late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) DEV_MAC_HDX_CFG_SEED_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) DEV_MAC_HDX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) DEV_MAC_HDX_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Set Max Length and maximum tags allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) DEV_MAC_TAGS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Set SMAC of Pause frame (00:00:00:00:00:00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Enable transmission of pause frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Drop frames with multicast source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ANA_PORT_DROP_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* Set default VLAN and tag type to 8021Q. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) REW_PORT_VLAN_CFG_PORT_TPID_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) REW_PORT_VLAN_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* Enable vcap lookups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ocelot_vcap_enable(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) EXPORT_SYMBOL(ocelot_init_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Configure and enable the CPU port module, which is a set of queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * accessible through register MMIO, frame DMA or Ethernet (in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * NPI mode is used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void ocelot_cpu_port_init(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int cpu = ocelot->num_phys_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* The unicast destination PGID for the CPU port module is unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Instead set up a multicast destination PGID for traffic copied to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * the CPU. Whitelisted MAC addresses like the port netdevice MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * addresses will be copied to the CPU via this PGID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ANA_PORT_PORT_CFG, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* Enable CPU port module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* CPU port Injection/Extraction configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ocelot->xtr_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ocelot->inj_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* Configure the CPU port to be VLAN aware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ANA_PORT_VLAN_CFG, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int ocelot_init(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) char queue_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (ocelot->ops->reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = ocelot->ops->reset(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) dev_err(ocelot->dev, "Switch reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (!ocelot->lags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ocelot->stats = devm_kcalloc(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ocelot->num_phys_ports * ocelot->num_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) sizeof(u64), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!ocelot->stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mutex_init(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) mutex_init(&ocelot->ptp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) spin_lock_init(&ocelot->ptp_clock_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) snprintf(queue_name, sizeof(queue_name), "%s-stats",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev_name(ocelot->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ocelot->stats_queue = create_singlethread_workqueue(queue_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (!ocelot->stats_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) INIT_LIST_HEAD(&ocelot->multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ocelot_mact_init(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ocelot_vlan_init(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ocelot_vcap_init(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ocelot_cpu_port_init(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) for (port = 0; port < ocelot->num_phys_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Clear all counters (5 groups) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) SYS_STAT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* Only use S-Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Aggregation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ANA_AGGR_CFG_AC_DMAC_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* Set MAC age time to default value. The entry is aged after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * 2*AGE_PERIOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ocelot_write(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ANA_AUTOAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* Disable learning for frames discarded by VLAN ingress filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Setup flooding PGIDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) for (i = 0; i < ocelot->num_flooding_pgids; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ANA_FLOODING_FLD_UNICAST(PGID_UC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ANA_FLOODING, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ANA_FLOODING_IPMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) for (port = 0; port < ocelot->num_phys_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* Transmit the frame to the local port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* Do not forward BPDU frames to the front ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ocelot_write_gix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ANA_PORT_CPU_FWD_BPDU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* Ensure bridging is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* Allow broadcast MAC frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ocelot_write_rix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ANA_PGID_PGID, PGID_MC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* Allow manual injection via DEVCPU_QS registers, and byte swap these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * registers endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) ANA_CPUQ_CFG_CPUQ_LRN(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ANA_CPUQ_CFG_CPUQ_IGMP(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ANA_CPUQ_8021_CFG, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) OCELOT_STATS_CHECK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) EXPORT_SYMBOL(ocelot_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) void ocelot_deinit(struct ocelot *ocelot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) cancel_delayed_work(&ocelot->stats_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) destroy_workqueue(ocelot->stats_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) mutex_destroy(&ocelot->stats_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) EXPORT_SYMBOL(ocelot_deinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) void ocelot_deinit_port(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) skb_queue_purge(&ocelot_port->tx_skbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) EXPORT_SYMBOL(ocelot_deinit_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MODULE_LICENSE("Dual MIT/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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