Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Register map access API - ENCX24J600 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2015 Gridpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Jon Ringle <jringle@gridpoint.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "encx24j600_hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static int encx24j600_switch_bank(struct encx24j600_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 				  int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int bank_opcode = BANK_SELECT(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ret = spi_write(ctx->spi, &bank_opcode, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		ctx->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			   const void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 				     { .tx_buf = buf, .len = len }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return spi_sync(ctx->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void regmap_lock_mutex(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	mutex_lock(&ctx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void regmap_unlock_mutex(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mutex_unlock(&ctx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				      size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 banked_reg = reg & ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u8 cmd = RCRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 tx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (reg < 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		cmd = RCRCODE | banked_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		if ((banked_reg < 0x16) && (ctx->bank != bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			ret = encx24j600_switch_bank(ctx, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		/* Translate registers that are more effecient using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		 * 3-byte SPI commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		case EGPRDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			cmd = RGPRDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		case EGPWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			cmd = RGPWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		case ERXRDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			cmd = RRXRDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		case ERXWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			cmd = RRXWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		case EUDARDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			cmd = RUDARDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		case EUDAWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			cmd = RUDAWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		case EGPDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		case ERXDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		case EUDADATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	tx_buf[i++] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (cmd == RCRU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		tx_buf[i++] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					u8 reg, u8 *val, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					u8 unbanked_cmd, u8 banked_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u8 banked_reg = reg & ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 cmd = unbanked_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				     { .tx_buf = &reg, .len = sizeof(reg), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				     { .tx_buf = val, .len = len }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (reg < 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		cmd = banked_code | banked_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if ((banked_reg < 0x16) && (ctx->bank != bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			ret = encx24j600_switch_bank(ctx, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		/* Translate registers that are more effecient using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		 * 3-byte SPI commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		case EGPRDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			cmd = WGPRDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		case EGPWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			cmd = WGPWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		case ERXRDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			cmd = WRXRDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		case ERXWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			cmd = WRXWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		case EUDARDPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			cmd = WUDARDPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		case EUDAWRPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			cmd = WUDAWRPT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		case EGPDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		case ERXDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		case EUDADATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (cmd == unbanked_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		t[1].tx_buf = &reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	spi_message_add_tail(&t[2], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return spi_sync(ctx->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				       size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					  u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					  u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					     unsigned int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					     unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	unsigned int set_mask = mask & val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned int clr_mask = mask & ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (set_mask & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	set_mask = (set_mask & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if ((set_mask & 0xff) && (ret == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if ((clr_mask & 0xff) && (ret == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	clr_mask = (clr_mask & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if ((clr_mask & 0xff) && (ret == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (reg < 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return encx24j600_cmdn(ctx, reg, data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* SPI 1-byte command. Ignore data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return spi_write(ctx->spi, &reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (reg == RBSEL && count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return spi_write_then_read(ctx->spi, &reg, sizeof(reg), data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int regmap_encx24j600_write(void *context, const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				   size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u8 *dout = (u8 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u8 reg = dout[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	++dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	--len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (reg > 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return regmap_encx24j600_spi_write(context, reg, dout, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (len > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return regmap_encx24j600_sfr_write(context, reg, dout, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int regmap_encx24j600_read(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				  const void *reg_buf, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				  void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u8 reg = *(const u8 *)reg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (reg_size != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (reg > 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return regmap_encx24j600_spi_read(context, reg, val, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (val_size > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return regmap_encx24j600_sfr_read(context, reg, val, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if ((reg < 0x36) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	    ((reg >= 0x40) && (reg < 0x4c)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	    ((reg >= 0x52) && (reg < 0x56)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	    ((reg >= 0x60) && (reg < 0x66)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	    ((reg >= 0x68) && (reg < 0x80)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	    ((reg >= 0x86) && (reg < 0x92)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	    (reg == 0xc8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if ((reg < 0x12) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	    ((reg >= 0x14) && (reg < 0x1a)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	    ((reg >= 0x1c) && (reg < 0x36)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	    ((reg >= 0x40) && (reg < 0x4c)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	    ((reg >= 0x52) && (reg < 0x56)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	    ((reg >= 0x60) && (reg < 0x68)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	    ((reg >= 0x6c) && (reg < 0x80)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	    ((reg >= 0x86) && (reg < 0x92)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	    ((reg >= 0xc0) && (reg < 0xc8)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	    ((reg >= 0xca) && (reg < 0xf0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	case ERXHEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	case EDMACS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case ETXSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	case ETXWIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	case ECON1:	/* Can be modified via single byte cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	case ECON2:	/* Can be modified via single byte cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	case ESTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	case EIR:	/* Can be modified via single byte cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	case MIRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case MISTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* single byte cmds are precious */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (((reg >= 0xc0) && (reg < 0xc8)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	    ((reg >= 0xca) && (reg < 0xf0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 					  unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	unsigned int mistat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	reg = MIREGADR_VAL | (reg & PHREG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ret = regmap_write(ctx->regmap, MIREGADR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ret = regmap_write(ctx->regmap, MICMD, MIIRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	usleep_range(26, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	       (mistat & BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ret = regmap_write(ctx->regmap, MICMD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ret = regmap_read(ctx->regmap, MIRD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		pr_err("%s: error %d reading reg %02x\n", __func__, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		       reg & PHREG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 					   unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	struct encx24j600_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	unsigned int mistat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	reg = MIREGADR_VAL | (reg & PHREG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ret = regmap_write(ctx->regmap, MIREGADR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	ret = regmap_write(ctx->regmap, MIWR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	usleep_range(26, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	       (mistat & BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		       reg & PHREG_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	case PHCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	case PHSTAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	case PHANA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	case PHANLPA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case PHANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	case PHCON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	case PHSTAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	case PHSTAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	case PHCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	case PHCON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	case PHANA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	case PHSTAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	case PHSTAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	case PHSTAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	case PHANLPA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	case PHANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	case PHSTAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	case PHSTAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	case PHSTAT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	case PHANLPA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	case PHANE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	case PHCON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct regmap_config regcfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.name = "reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	.max_register = 0xee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.readable_reg = encx24j600_regmap_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.writeable_reg = encx24j600_regmap_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.volatile_reg = encx24j600_regmap_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.precious_reg = encx24j600_regmap_precious,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.lock = regmap_lock_mutex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.unlock = regmap_unlock_mutex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct regmap_bus regmap_encx24j600 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	.write = regmap_encx24j600_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	.read = regmap_encx24j600_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.reg_update_bits = regmap_encx24j600_reg_update_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct regmap_config phycfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	.name = "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	.max_register = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	.readable_reg = encx24j600_phymap_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	.writeable_reg = encx24j600_phymap_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	.volatile_reg = encx24j600_phymap_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct regmap_bus phymap_encx24j600 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	.reg_write = regmap_encx24j600_phy_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	.reg_read = regmap_encx24j600_phy_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int devm_regmap_init_encx24j600(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 				struct encx24j600_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	mutex_init(&ctx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	regcfg.lock_arg = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	ctx->regmap = devm_regmap_init(dev, &regmap_encx24j600, ctx, &regcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (IS_ERR(ctx->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		return PTR_ERR(ctx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	if (IS_ERR(ctx->phymap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		return PTR_ERR(ctx->phymap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_LICENSE("GPL");