^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microchip ENC28J60 ethernet driver (MAC + PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Eurek srl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on enc28j60.c written by David Anders for 2.4 kernel version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tcp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "enc28j60_hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_NAME "enc28j60"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRV_VERSION "1.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_OPLEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ENC28J60_MSG_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Buffer size required for the largest SPI transfer (i.e., reading a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * frame).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TX_TIMEOUT (4 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Max TX retries in case of collision as suggested by errata datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX_TX_RETRYCOUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RXFILTER_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RXFILTER_MULTI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RXFILTER_PROMISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Driver local data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct enc28j60_net {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct work_struct tx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct work_struct irq_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct work_struct setrx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct work_struct restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 bank; /* current register bank selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 next_pk_ptr; /* next packet pointer within FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 max_pk_counter; /* statistics: max packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 tx_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool hw_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int rxfilter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* use ethtool to change the level for any given device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } debug = { -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * SPI read buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Wait for the SPI transfer and copy received data to destination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 *rx_buf = priv->spi_transfer_buf + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 *tx_buf = priv->spi_transfer_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct spi_transfer tx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .tx_buf = tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .len = SPI_OPLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_transfer rx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .rx_buf = rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tx_buf[0] = ENC28J60_READ_BUF_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spi_message_add_tail(&tx, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spi_message_add_tail(&rx, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = spi_sync(priv->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) memcpy(data, rx_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = msg.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret && netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * SPI write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) memcpy(&priv->spi_transfer_buf[1], data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret && netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * basic SPI read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 tx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 rx_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int slen = SPI_OPLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* do dummy read if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (addr & SPRD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) slen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tx_buf[0] = op | (addr & ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = rx_buf[slen - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * basic SPI write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) priv->spi_transfer_buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret && netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void enc28j60_soft_reset(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Errata workaround #1, CLKRDY check is unreliable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * delay at least 1 ms instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) udelay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * select the current register bank if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 b = (addr & BANK_MASK) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * are present in all banks, no need to switch bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (addr >= EIE && addr <= ECON1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Clear or set each bank selection bit as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (b & ECON1_BSEL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ECON1_BSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ECON1_BSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (b & ECON1_BSEL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ECON1_BSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ECON1_BSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) priv->bank = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Register access routines through the SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Every register access comes in two flavours:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * atomically more than one register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Some registers can be accessed through the bit field clear and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * bit field set to avoid a read modify write cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Register bit field Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enc28j60_set_bank(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) nolock_reg_bfset(priv, addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Register bit field Clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enc28j60_set_bank(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) nolock_reg_bfclr(priv, addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Register byte read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int nolock_regb_read(struct enc28j60_net *priv, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enc28j60_set_bank(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int locked_regb_read(struct enc28j60_net *priv, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = nolock_regb_read(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Register word read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int nolock_regw_read(struct enc28j60_net *priv, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int rl, rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enc28j60_set_bank(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return (rh << 8) | rl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int locked_regw_read(struct enc28j60_net *priv, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = nolock_regw_read(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Register byte write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) enc28j60_set_bank(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) nolock_regb_write(priv, address, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Register word write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) enc28j60_set_bank(priv, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (u8) (data >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) nolock_regw_write(priv, address, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * Buffer memory read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Select the starting address and execute a SPI buffer read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) nolock_regw_write(priv, ERDPTL, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #ifdef CONFIG_ENC28J60_WRITEVERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (netif_msg_drv(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) reg = nolock_regw_read(priv, ERDPTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (reg != addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "%s() error writing ERDPT (0x%04x - 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __func__, reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spi_read_buf(priv, len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Write packet to enc28j60 TX buffer memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Set the write pointer to start of transmit buffer area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #ifdef CONFIG_ENC28J60_WRITEVERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (netif_msg_drv(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reg = nolock_regw_read(priv, EWRPTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (reg != TXSTART_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "%s() ERWPT:0x%04x != 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__, reg, TXSTART_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Set the TXND pointer to correspond to the packet size given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* write per-packet control byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "%s() after control byte ERWPT:0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __func__, nolock_regw_read(priv, EWRPTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* copy the packet into the transmit buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) spi_write_buf(priv, len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "%s() after write packet ERWPT:0x%04x, len=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __func__, nolock_regw_read(priv, EWRPTL), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long timeout = jiffies + msecs_to_jiffies(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* 20 msec timeout read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) while ((nolock_regb_read(priv, reg) & mask) != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_dbg(dev, "reg %02x ready timeout!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Wait until the PHY operation is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int wait_phy_ready(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * PHY register read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * PHY registers are not accessed directly, but through the MII.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* set the PHY register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) nolock_regb_write(priv, MIREGADR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* start the register read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) nolock_regb_write(priv, MICMD, MICMD_MIIRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* wait until the PHY read completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) wait_phy_ready(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* quit reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) nolock_regb_write(priv, MICMD, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* return the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = nolock_regw_read(priv, MIRDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* set the PHY register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) nolock_regb_write(priv, MIREGADR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* write the PHY data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) nolock_regw_write(priv, MIWRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* wait until the PHY write completes and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = wait_phy_ready(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Program the hardware MAC address from dev->dev_addr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int enc28j60_set_hw_macaddr(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!priv->hw_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_info(dev, "%s: Setting MAC address to %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ndev->name, ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* NOTE: MAC address in ENC28J60 is byte-backward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "%s() Hardware must be disabled to set Mac address\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Store the new hardware address in dev->dev_addr, and update the MAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct sockaddr *address = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!is_valid_ether_addr(address->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ether_addr_copy(dev->dev_addr, address->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return enc28j60_set_hw_macaddr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Debug routine to dump useful register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) " %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "HwRevID: 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "MAC : MACON1 MACON3 MACON4\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) " 0x%02x 0x%02x 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) " 0x%04x 0x%04x 0x%04x 0x%04x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "0x%02x 0x%02x 0x%04x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msg, nolock_regb_read(priv, EREVID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) nolock_regw_read(priv, ERXWRPTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) nolock_regw_read(priv, ERXRDPTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) nolock_regb_read(priv, ERXFCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) nolock_regb_read(priv, EPKTCNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) nolock_regw_read(priv, ETXNDL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) nolock_regb_read(priv, MACLCON1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) nolock_regb_read(priv, MACLCON2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) nolock_regb_read(priv, MAPHSUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u16 erxrdpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) erxrdpt = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) erxrdpt = next_packet_ptr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return erxrdpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Calculate wrap around when reading beyond the end of the RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static u16 rx_packet_start(u16 ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ptr + RSV_SIZE > RXEND_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ptr + RSV_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 erxrdpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (start > 0x1FFF || end > 0x1FFF || start > end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_err(dev, "%s(%d, %d) RXFIFO bad parameters!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) __func__, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* set receive buffer start + end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) priv->next_pk_ptr = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) nolock_regw_write(priv, ERXSTL, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) nolock_regw_write(priv, ERXRDPTL, erxrdpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) nolock_regw_write(priv, ERXNDL, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (start > 0x1FFF || end > 0x1FFF || start > end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(dev, "%s(%d, %d) TXFIFO bad parameters!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __func__, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* set transmit buffer start + end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) nolock_regw_write(priv, ETXSTL, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) nolock_regw_write(priv, ETXNDL, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Low power mode shrinks power consumption about 100x, so we'd like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * the chip to be in that mode whenever it's inactive. (However, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * can't stay in low power mode during suspend with WOL active.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(dev, "%s power...\n", is_low ? "low" : "high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (is_low) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) poll_ready(priv, ECON1, ECON1_TXRTS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* ECON2_VRPS was set during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* caller sets ECON1_RXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int enc28j60_hw_init(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_printk(KERN_DEBUG, dev, "%s() - %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) priv->full_duplex ? "FullDuplex" : "HalfDuplex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* first reset the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) enc28j60_soft_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Clear ECON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) priv->bank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) priv->hw_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) priv->tx_retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) priv->max_pk_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) priv->rxfilter = RXFILTER_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* enable address auto increment and voltage regulator powersave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Check the RevID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * damaged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg = locked_regb_read(priv, EREVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_info(dev, "chip RevID: 0x%02x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (reg == 0x00 || reg == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_printk(KERN_DEBUG, dev, "%s() Invalid RevId %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* default filter mode: (unicast OR broadcast) AND crc valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) locked_regb_write(priv, ERXFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* enable MAC receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) locked_regb_write(priv, MACON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* enable automatic padding and CRC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (priv->full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) locked_regb_write(priv, MACON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MACON3_PADCFG0 | MACON3_TXCRCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) MACON3_FRMLNEN | MACON3_FULDPX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* set inter-frame gap (non-back-to-back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) locked_regb_write(priv, MAIPGL, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* set inter-frame gap (back-to-back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) locked_regb_write(priv, MABBIPG, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) locked_regb_write(priv, MACON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MACON3_PADCFG0 | MACON3_TXCRCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MACON3_FRMLNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* set inter-frame gap (non-back-to-back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) locked_regw_write(priv, MAIPGL, 0x0C12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* set inter-frame gap (back-to-back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) locked_regb_write(priv, MABBIPG, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * MACLCON1 (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * MACLCON2 (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * Set the maximum packet size which the controller will accept.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Configure LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (priv->full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!enc28j60_phy_write(priv, PHCON2, 0x00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!enc28j60_phy_write(priv, PHCON1, 0x00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) enc28j60_dump_regs(priv, "Hw initialized.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void enc28j60_hw_enable(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_printk(KERN_DEBUG, dev, "%s() enabling interrupts.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* enable receive logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) priv->hw_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void enc28j60_hw_disable(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* disable interrupts and packet reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) nolock_regb_write(priv, EIE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) priv->hw_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!priv->hw_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* link is in low power mode now; duplex setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * will take effect on next enc28j60_hw_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) priv->full_duplex = (duplex == DUPLEX_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (netif_msg_link(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) netdev_warn(ndev, "unsupported link setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (netif_msg_link(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) netdev_warn(ndev, "Warning: hw must be disabled to set link mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Read the Transmit Status Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int endptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) endptr = locked_regw_read(priv, ETXNDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_printk(KERN_DEBUG, dev, "reading TSV at addr:0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) endptr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 tsv[TSV_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_printk(KERN_DEBUG, dev, "%s - TSV:\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) tmp1 = tsv[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) tmp1 <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) tmp1 |= tsv[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) tmp2 = tsv[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tmp2 <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) tmp2 |= tsv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) tmp1, tsv[2] & 0x0f, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TSV_GETBIT(tsv, TSV_TXDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) TSV_GETBIT(tsv, TSV_TXCRCERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "Multicast: %d, Broadcast: %d, PacketDefer: %d, ExDefer: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TSV_GETBIT(tsv, TSV_TXMULTICAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TSV_GETBIT(tsv, TSV_TXBROADCAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TSV_GETBIT(tsv, TSV_TXEXDEFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "ExCollision: %d, LateCollision: %d, Giant: %d, Underrun: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "ControlFrame: %d, PauseFrame: %d, BackPressApp: %d, VLanTagFrame: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Receive Status vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u16 pk_ptr, int len, u16 sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_printk(KERN_DEBUG, dev, "%s - NextPk: 0x%04x - RSV:\n", msg, pk_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_printk(KERN_DEBUG, dev, "ByteCount: %d, DribbleNibble: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) len, RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "RxOK: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RSV_GETBIT(sts, RSV_RXOK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RSV_GETBIT(sts, RSV_CRCERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RSV_GETBIT(sts, RSV_LENCHECKERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) RSV_GETBIT(sts, RSV_RXMULTICAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) RSV_GETBIT(sts, RSV_RXBROADCAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) RSV_GETBIT(sts, RSV_CARRIEREV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) RSV_GETBIT(sts, RSV_RXTYPEVLAN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static void dump_packet(const char *msg, int len, const char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) data, len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Hardware receive function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Read the buffer memory, update the FIFO pointer to free the buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * check the status vector and decrement the packet counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void enc28j60_hw_rx(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct sk_buff *skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u16 erxrdpt, next_packet, rxstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u8 rsv[RSV_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (netif_msg_rx_status(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) netdev_printk(KERN_DEBUG, ndev, "RX pk_addr:0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) priv->next_pk_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (netif_msg_rx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) netdev_err(ndev, "%s() Invalid packet address!! 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) __func__, priv->next_pk_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* packet address corrupted: reset RX logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ndev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Read next packet pointer and rx status vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) next_packet = rsv[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) next_packet <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) next_packet |= rsv[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) len = rsv[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) len <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) len |= rsv[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) rxstat = rsv[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rxstat <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rxstat |= rsv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (netif_msg_rx_status(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (netif_msg_rx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) netdev_err(ndev, "Rx Error (%04x)\n", rxstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ndev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (RSV_GETBIT(rxstat, RSV_CRCERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ndev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ndev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (len > MAX_FRAMELEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ndev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (netif_msg_rx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) netdev_err(ndev, "out of memory for Rx'd frame\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ndev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) skb_reserve(skb, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* copy the packet from the receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) enc28j60_mem_read(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rx_packet_start(priv->next_pk_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) len, skb_put(skb, len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (netif_msg_pktdata(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dump_packet(__func__, skb->len, skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) skb->protocol = eth_type_trans(skb, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ndev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ndev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * Move the RX read pointer to the start of the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * received packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * This frees the memory we just read out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT:0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) __func__, erxrdpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) nolock_regw_write(priv, ERXRDPTL, erxrdpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #ifdef CONFIG_ENC28J60_WRITEVERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (netif_msg_drv(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) reg = nolock_regw_read(priv, ERXRDPTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (reg != erxrdpt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "%s() ERXRDPT verify error (0x%04x - 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __func__, reg, erxrdpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) priv->next_pk_ptr = next_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* we are done with this packet, decrement the packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Calculate free space in RxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct net_device *ndev = priv->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int epkcnt, erxst, erxnd, erxwr, erxrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int free_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) epkcnt = nolock_regb_read(priv, EPKTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (epkcnt >= 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) free_space = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) erxst = nolock_regw_read(priv, ERXSTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) erxnd = nolock_regw_read(priv, ERXNDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) erxwr = nolock_regw_read(priv, ERXWRPTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) erxrd = nolock_regw_read(priv, ERXRDPTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (erxwr > erxrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) free_space = (erxnd - erxst) - (erxwr - erxrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) else if (erxwr == erxrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) free_space = (erxnd - erxst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) free_space = erxrd - erxwr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (netif_msg_rx_status(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) netdev_printk(KERN_DEBUG, ndev, "%s() free_space = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __func__, free_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return free_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Access the PHY to determine link status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void enc28j60_check_link_status(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) reg = enc28j60_phy_read(priv, PHSTAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (netif_msg_hw(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) "%s() PHSTAT1: %04x, PHSTAT2: %04x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) enc28j60_phy_read(priv, PHSTAT1), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) duplex = reg & PHSTAT2_DPXSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (reg & PHSTAT2_LSTAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) netif_carrier_on(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (netif_msg_ifup(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) netdev_info(ndev, "link up - %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) duplex ? "Full duplex" : "Half duplex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (netif_msg_ifdown(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) netdev_info(ndev, "link down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) netif_carrier_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static void enc28j60_tx_clear(struct net_device *ndev, bool err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ndev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ndev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (priv->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ndev->stats.tx_bytes += priv->tx_skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_kfree_skb(priv->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * RX handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * Ignore PKTIF because is unreliable! (Look at the errata datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * Check EPKTCNT is the suggested workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * We don't need to clear interrupt flag, automatically done when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * enc28j60_hw_rx() decrements the packet counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * Returns how many packet processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int enc28j60_rx_interrupt(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int pk_counter, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pk_counter = locked_regb_read(priv, EPKTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (pk_counter && netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) netdev_printk(KERN_DEBUG, ndev, "intRX, pk_cnt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pk_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (pk_counter > priv->max_pk_counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) priv->max_pk_counter = pk_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) netdev_printk(KERN_DEBUG, ndev, "RX max_pk_cnt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) priv->max_pk_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = pk_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) while (pk_counter-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) enc28j60_hw_rx(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static void enc28j60_irq_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct enc28j60_net *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) container_of(work, struct enc28j60_net, irq_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct net_device *ndev = priv->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int intflags, loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* disable further interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) locked_reg_bfclr(priv, EIE, EIE_INTIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) intflags = locked_regb_read(priv, EIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* DMA interrupt handler (not currently used) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if ((intflags & EIR_DMAIF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) netdev_printk(KERN_DEBUG, ndev, "intDMA(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) locked_reg_bfclr(priv, EIR, EIR_DMAIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* LINK changed handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if ((intflags & EIR_LINKIF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) netdev_printk(KERN_DEBUG, ndev, "intLINK(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) enc28j60_check_link_status(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* read PHIR to clear the flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) enc28j60_phy_read(priv, PHIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* TX complete handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (((intflags & EIR_TXIF) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ((intflags & EIR_TXERIF) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) bool err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) netdev_printk(KERN_DEBUG, ndev, "intTX(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) priv->tx_retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (netif_msg_tx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) netdev_err(ndev, "Tx Error (aborted)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) err = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (netif_msg_tx_done(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u8 tsv[TSV_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) enc28j60_read_tsv(priv, tsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) enc28j60_dump_tsv(priv, "Tx Done", tsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) enc28j60_tx_clear(ndev, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) locked_reg_bfclr(priv, EIR, EIR_TXIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* TX Error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if ((intflags & EIR_TXERIF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 tsv[TSV_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) netdev_printk(KERN_DEBUG, ndev, "intTXErr(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) enc28j60_read_tsv(priv, tsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (netif_msg_tx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) enc28j60_dump_tsv(priv, "Tx Error", tsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Reset TX logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* Transmit Late collision check for retransmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (netif_msg_tx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) netdev_printk(KERN_DEBUG, ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "LateCollision TXErr (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) priv->tx_retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) locked_reg_bfset(priv, ECON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ECON1_TXRTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) enc28j60_tx_clear(ndev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) enc28j60_tx_clear(ndev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* RX Error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if ((intflags & EIR_RXERIF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (netif_msg_intr(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) netdev_printk(KERN_DEBUG, ndev, "intRXErr(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Check free FIFO space to flag RX overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (enc28j60_get_free_rxfifo(priv) <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (netif_msg_rx_err(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) netdev_printk(KERN_DEBUG, ndev, "RX Overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ndev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) locked_reg_bfclr(priv, EIR, EIR_RXERIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* RX handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (enc28j60_rx_interrupt(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) } while (loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* re-enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) locked_reg_bfset(priv, EIE, EIE_INTIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Hardware transmit function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * Fill the buffer memory and send the contents of the transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * onto the network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static void enc28j60_hw_tx(struct enc28j60_net *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct net_device *ndev = priv->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) BUG_ON(!priv->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (netif_msg_tx_queued(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) netdev_printk(KERN_DEBUG, ndev, "Tx Packet Len:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) priv->tx_skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (netif_msg_pktdata(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dump_packet(__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) priv->tx_skb->len, priv->tx_skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #ifdef CONFIG_ENC28J60_WRITEVERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* readback and verify written data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (netif_msg_drv(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int test_len, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) u8 test_buf[64]; /* limit the test to the first 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int okflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) test_len = priv->tx_skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (test_len > sizeof(test_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) test_len = sizeof(test_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* + 1 to skip control byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) okflag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) for (k = 0; k < test_len; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (priv->tx_skb->data[k] != test_buf[k]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_printk(KERN_DEBUG, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "Error, %d location differ: 0x%02x-0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) k, priv->tx_skb->data[k], test_buf[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) okflag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!okflag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_printk(KERN_DEBUG, dev, "Tx write buffer, verify ERROR!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* set TX request flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* If some error occurs while trying to transmit this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * packet, you should return '1' from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * In such a case you _may not_ do anything to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * SKB, it is still owned by the network queueing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * layer when an error is returned. This means you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * may not modify any SKB fields, you may not free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * the SKB, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Remember the skb for deferred processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) priv->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) schedule_work(&priv->tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static void enc28j60_tx_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct enc28j60_net *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) container_of(work, struct enc28j60_net, tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* actual delivery of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) enc28j60_hw_tx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static irqreturn_t enc28j60_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct enc28j60_net *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * Can't do anything in interrupt context because we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * block (spi_sync() is blocking) so fire of the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * handling workqueue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * Remember that we access enc28j60 registers through SPI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * via spi_sync() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) schedule_work(&priv->irq_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static void enc28j60_tx_timeout(struct net_device *ndev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct enc28j60_net *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (netif_msg_timer(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) netdev_err(ndev, "tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ndev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* can't restart safely under softirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) schedule_work(&priv->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * Open/initialize the board. This is called (in the current kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * sometime after booting when the 'ifconfig' program is run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * This routine should set everything up anew at each open, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * registers that "should" only need to be set once at boot, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * there is non-reboot way to recover if something goes wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int enc28j60_net_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (netif_msg_ifup(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) netdev_err(dev, "invalid MAC address %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* Reset the hardware here (and take it out of low power mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) enc28j60_lowpower(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) enc28j60_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (!enc28j60_hw_init(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (netif_msg_ifup(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) netdev_err(dev, "hw_reset() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* Update the MAC address (in case user has changed it) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) enc28j60_set_hw_macaddr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) enc28j60_hw_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* check link status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) enc28j60_check_link_status(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* We are now ready to accept transmit requests from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * the queueing layer of the networking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* The inverse routine to net_open(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int enc28j60_net_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) enc28j60_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) enc28j60_lowpower(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Set or clear the multicast filter for this adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * num_addrs == -1 Promiscuous mode, receive all packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * num_addrs == 0 Normal mode, filter out multicast packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * num_addrs > 0 Multicast mode, receive normal and MC packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static void enc28j60_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int oldfilter = priv->rxfilter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (netif_msg_link(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) netdev_info(dev, "promiscuous mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) priv->rxfilter = RXFILTER_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (netif_msg_link(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) netdev_info(dev, "%smulticast mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) (dev->flags & IFF_ALLMULTI) ? "all-" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) priv->rxfilter = RXFILTER_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (netif_msg_link(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) netdev_info(dev, "normal mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) priv->rxfilter = RXFILTER_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (oldfilter != priv->rxfilter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) schedule_work(&priv->setrx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static void enc28j60_setrx_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct enc28j60_net *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) container_of(work, struct enc28j60_net, setrx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct device *dev = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (priv->rxfilter == RXFILTER_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_printk(KERN_DEBUG, dev, "promiscuous mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) locked_regb_write(priv, ERXFCON, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) } else if (priv->rxfilter == RXFILTER_MULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_printk(KERN_DEBUG, dev, "multicast mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) locked_regb_write(priv, ERXFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ERXFCON_UCEN | ERXFCON_CRCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ERXFCON_BCEN | ERXFCON_MCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (netif_msg_drv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dev_printk(KERN_DEBUG, dev, "normal mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) locked_regb_write(priv, ERXFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ERXFCON_UCEN | ERXFCON_CRCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ERXFCON_BCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static void enc28j60_restart_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct enc28j60_net *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) container_of(work, struct enc28j60_net, restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct net_device *ndev = priv->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) enc28j60_net_close(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ret = enc28j60_net_open(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) netdev_info(ndev, "could not restart %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_close(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* ......................... ETHTOOL SUPPORT ........................... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) strlcpy(info->bus_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) dev_name(dev->dev.parent), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) enc28j60_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ethtool_link_ksettings_zero_link_mode(cmd, supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) cmd->base.speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) cmd->base.port = PORT_TP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) cmd->base.autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) enc28j60_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return enc28j60_setlink(dev, cmd->base.autoneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) cmd->base.speed, cmd->base.duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static u32 enc28j60_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return priv->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) priv->msg_enable = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct ethtool_ops enc28j60_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .get_drvinfo = enc28j60_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .get_msglevel = enc28j60_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .set_msglevel = enc28j60_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .get_link_ksettings = enc28j60_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .set_link_ksettings = enc28j60_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int enc28j60_chipset_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct enc28j60_net *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return enc28j60_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const struct net_device_ops enc28j60_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .ndo_open = enc28j60_net_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .ndo_stop = enc28j60_net_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .ndo_start_xmit = enc28j60_send_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .ndo_set_rx_mode = enc28j60_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .ndo_set_mac_address = enc28j60_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .ndo_tx_timeout = enc28j60_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int enc28j60_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) unsigned char macaddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct enc28j60_net *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (netif_msg_drv(&debug))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) dev_info(&spi->dev, "Ethernet driver %s loaded\n", DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev = alloc_etherdev(sizeof(struct enc28j60_net));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) goto error_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) priv->netdev = dev; /* priv to netdev reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) priv->spi = spi; /* priv to spi reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) spi_set_drvdata(spi, priv); /* spi to priv reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) SET_NETDEV_DEV(dev, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!enc28j60_chipset_init(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (netif_msg_probe(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_info(&spi->dev, "chip not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto error_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (device_get_mac_address(&spi->dev, macaddr, sizeof(macaddr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ether_addr_copy(dev->dev_addr, macaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) enc28j60_set_hw_macaddr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* Board setup must set the relevant edge trigger type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * level triggers won't currently work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (netif_msg_probe(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dev_err(&spi->dev, "request irq %d failed (ret = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) spi->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) goto error_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev->if_port = IF_PORT_10BASET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev->irq = spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev->netdev_ops = &enc28j60_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev->watchdog_timeo = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev->ethtool_ops = &enc28j60_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) enc28j60_lowpower(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ret = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (netif_msg_probe(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_err(&spi->dev, "register netdev failed (ret = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) goto error_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) error_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) error_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) error_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static int enc28j60_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct enc28j60_net *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) unregister_netdev(priv->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) free_netdev(priv->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static const struct of_device_id enc28j60_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) { .compatible = "microchip,enc28j60" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) MODULE_DEVICE_TABLE(of, enc28j60_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static struct spi_driver enc28j60_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .of_match_table = enc28j60_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .probe = enc28j60_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .remove = enc28j60_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) module_spi_driver(enc28j60_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) module_param_named(debug, debug.msg_enable, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) MODULE_PARM_DESC(debug, "Debug verbosity level in amount of bits set (0=none, ..., 31=all)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) MODULE_ALIAS("spi:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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