^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/net/ethernet/micrel/ks8851.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * KS8851 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __KS8851_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __KS8851_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/eeprom_93cx6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define KS_CCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CCR_LE (1 << 10) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CCR_EEPROM (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CCR_SPI (1 << 8) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CCR_8BIT (1 << 7) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CCR_16BIT (1 << 6) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CCR_32BIT (1 << 5) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CCR_SHARED (1 << 4) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCR_48PIN (1 << 1) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCR_32PIN (1 << 0) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MAC address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define KS_MAR(_m) (0x14 - (_m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define KS_MARL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define KS_MARM 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define KS_MARH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KS_OBCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OBCR_ODS_16mA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KS_EEPCR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EEPCR_EESRWA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EEPCR_EESA (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EEPCR_EESB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EEPCR_EEDO (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EEPCR_EESCK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EEPCR_EECS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KS_MBIR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MBIR_TXMBF (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MBIR_TXMBFA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MBIR_RXMBF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MBIR_RXMBFA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define KS_GRR 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GRR_QMU (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GRR_GSR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KS_WFCR 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WFCR_MPRXE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WFCR_WF3E (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WFCR_WF2E (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WFCR_WF1E (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WFCR_WF0E (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define KS_WF0CRC0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define KS_WF0CRC1 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define KS_WF0BM0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define KS_WF0BM1 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KS_WF0BM2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KS_WF0BM3 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KS_WF1CRC0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KS_WF1CRC1 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KS_WF1BM0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KS_WF1BM1 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define KS_WF1BM2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define KS_WF1BM3 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define KS_WF2CRC0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define KS_WF2CRC1 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define KS_WF2BM0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define KS_WF2BM1 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define KS_WF2BM2 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define KS_WF2BM3 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define KS_WF3CRC0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define KS_WF3CRC1 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define KS_WF3BM0 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define KS_WF3BM1 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define KS_WF3BM2 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define KS_WF3BM3 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define KS_TXCR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TXCR_TCGICMP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TXCR_TCGUDP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TXCR_TCGTCP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TXCR_TCGIP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TXCR_FTXQ (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TXCR_TXFCE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TXCR_TXPE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TXCR_TXCRC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TXCR_TXE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define KS_TXSR 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TXSR_TXLC (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TXSR_TXMC (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TXSR_TXFID_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TXSR_TXFID_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define KS_RXCR1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RXCR1_FRXQ (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RXCR1_RXUDPFCC (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RXCR1_RXTCPFCC (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RXCR1_RXIPFCC (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RXCR1_RXPAFMA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RXCR1_RXFCE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RXCR1_RXEFE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RXCR1_RXMAFMA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RXCR1_RXBE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RXCR1_RXME (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RXCR1_RXUE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RXCR1_RXAE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RXCR1_RXINVF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RXCR1_RXE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define KS_RXCR2 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RXCR2_SRDBL_MASK (0x7 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RXCR2_SRDBL_SHIFT (5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RXCR2_SRDBL_4B (0x0 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RXCR2_SRDBL_8B (0x1 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RXCR2_SRDBL_16B (0x2 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RXCR2_SRDBL_32B (0x3 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RXCR2_SRDBL_FRAME (0x4 << 5) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RXCR2_IUFFP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RXCR2_RXIUFCEZ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RXCR2_UDPLFE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RXCR2_RXICMPFCC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RXCR2_RXSAF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define KS_TXMIR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define KS_RXFHSR 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RXFSHR_RXFV (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RXFSHR_RXICMPFCS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RXFSHR_RXIPFCS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RXFSHR_RXTCPFCS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RXFSHR_RXUDPFCS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RXFSHR_RXBF (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RXFSHR_RXMF (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RXFSHR_RXUF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RXFSHR_RXMR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RXFSHR_RXFT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RXFSHR_RXFTL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RXFSHR_RXRF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RXFSHR_RXCE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define KS_RXFHBCR 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RXFHBCR_CNT_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define KS_TXQCR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TXQCR_AETFE (1 << 2) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TXQCR_TXQMAM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TXQCR_METFE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define KS_RXQCR 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RXQCR_RXDTTS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RXQCR_RXDBCTS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RXQCR_RXFCTS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RXQCR_RXIPHTOE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RXQCR_RXDTTE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RXQCR_RXDBCTE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RXQCR_RXFCTE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RXQCR_ADRFE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RXQCR_SDA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RXQCR_RRXEF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define KS_TXFDPR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TXFDPR_TXFPAI (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TXFDPR_TXFP_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TXFDPR_TXFP_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define KS_RXFDPR 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RXFDPR_RXFPAI (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RXFDPR_WST (1 << 12) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RXFDPR_EMS (1 << 11) /* KSZ8851-16MLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RXFDPR_RXFP_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RXFDPR_RXFP_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define KS_RXDTTR 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define KS_RXDBCTR 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define KS_IER 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define KS_ISR 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IRQ_LCI (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IRQ_TXI (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IRQ_RXI (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IRQ_RXOI (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IRQ_TXPSI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IRQ_RXPSI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IRQ_TXSAI (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IRQ_RXWFDI (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IRQ_RXMPDI (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IRQ_LDI (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IRQ_EDI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IRQ_SPIBEI (1 << 1) /* KSZ8851SNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IRQ_DEDI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define KS_RXFCTR 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define KS_RXFC 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RXFCTR_RXFC_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RXFCTR_RXFC_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RXFCTR_RXFCT_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RXFCTR_RXFCT_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define KS_TXNTFSR 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define KS_MAHTR0 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define KS_MAHTR1 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define KS_MAHTR2 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define KS_MAHTR3 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define KS_FCLWR 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define KS_FCHWR 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define KS_FCOWR 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define KS_CIDER 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CIDER_ID 0x8870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CIDER_REV_MASK (0x7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CIDER_REV_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define KS_CGCR 0xC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define KS_IACR 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IACR_RDEN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IACR_TSEL_MASK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IACR_TSEL_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IACR_TSEL_MIB (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IACR_ADDR_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IACR_ADDR_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define KS_IADLR 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define KS_IAHDR 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define KS_PMECR 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PMECR_PME_DELAY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PMECR_PME_POL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PMECR_WOL_WAKEUP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PMECR_WOL_MAGICPKT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PMECR_WOL_LINKUP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PMECR_WOL_ENERGY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PMECR_AUTO_WAKE_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PMECR_WAKEUP_NORMAL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PMECR_WKEVT_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PMECR_WKEVT_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PMECR_WKEVT_ENERGY (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PMECR_WKEVT_LINK (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PMECR_WKEVT_FRAME (0x8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PMECR_PM_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PMECR_PM_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PMECR_PM_NORMAL (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PMECR_PM_ENERGY (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PMECR_PM_SOFTDOWN (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PMECR_PM_POWERSAVE (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Standard MII PHY data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define KS_P1MBCR 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define KS_P1MBSR 0xE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define KS_PHY1ILR 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define KS_PHY1IHR 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define KS_P1ANAR 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define KS_P1ANLPR 0xEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define KS_P1SCLMD 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define KS_P1CR 0xF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define P1CR_LEDOFF (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define P1CR_TXIDS (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define P1CR_RESTARTAN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define P1CR_DISAUTOMDIX (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define P1CR_FORCEMDIX (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define P1CR_AUTONEGEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define P1CR_FORCE100 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define P1CR_FORCEFDX (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define P1CR_ADV_FLOW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define P1CR_ADV_100BT_FDX (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define P1CR_ADV_100BT_HDX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define P1CR_ADV_10BT_FDX (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define P1CR_ADV_10BT_HDX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define KS_P1SR 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define P1SR_HP_MDIX (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define P1SR_REV_POL (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define P1SR_OP_100M (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define P1SR_OP_FDX (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define P1SR_OP_MDI (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define P1SR_AN_DONE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define P1SR_LINK_GOOD (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define P1SR_PNTR_FLOW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define P1SR_PNTR_100BT_FDX (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define P1SR_PNTR_100BT_HDX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define P1SR_PNTR_10BT_FDX (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define P1SR_PNTR_10BT_HDX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* TX Frame control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TXFR_TXIC (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TXFR_TXFID_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TXFR_TXFID_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * struct ks8851_rxctrl - KS8851 driver rx control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @mchash: Multicast hash-table data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @rxcr1: KS_RXCR1 register setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @rxcr2: KS_RXCR2 register setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Representation of the settings needs to control the receive filtering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * such as the multicast hash-filter and the receive register settings. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * is used to make the job of working out if the receive settings change and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * then issuing the new settings to the worker that will send the necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ks8851_rxctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 mchash[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 rxcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 rxcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * union ks8851_tx_hdr - tx header data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @txb: The header as bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @txw: The header as 16bit, little-endian words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * A dual representation of the tx header data to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * access to individual bytes, and to allow 16bit accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * with 16bit alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) union ks8851_tx_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 txb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __le16 txw[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * struct ks8851_net - KS8851 driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @netdev: The network device we're bound to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * @statelock: Lock on this structure for tx list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @mii: The MII state information for the mii calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @rxctrl: RX settings for @rxctrl_work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @rxctrl_work: Work queue for updating RX mode and multicast lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @txq: Queue of packets for transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @txh: Space for generating packet TX header in DMA-able data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @rxd: Space for receiving SPI data, in DMA-able space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @txd: Space for transmitting SPI data, in DMA-able space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @msg_enable: The message flags controlling driver output (see ethtool).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @fid: Incrementing frame id tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @rc_ier: Cached copy of KS_IER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @rc_ccr: Cached copy of KS_CCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @rc_rxqcr: Cached copy of KS_RXQCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @eeprom: 93CX6 EEPROM state for accessing on-board EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @vdd_reg: Optional regulator supplying the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @vdd_io: Optional digital power supply for IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @gpio: Optional reset_n gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @lock: Bus access lock callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @unlock: Bus access unlock callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @rdreg16: 16bit register read callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @wrreg16: 16bit register write callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @rdfifo: FIFO read callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @wrfifo: FIFO write callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @start_xmit: start_xmit() implementation callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @rx_skb: rx_skb() implementation callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @flush_tx_work: flush_tx_work() implementation callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * The @statelock is used to protect information in the structure which may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * need to be accessed via several sources, such as the network driver layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * or one of the work queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * We align the buffers we may use for rx/tx to ensure that if the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * wants to DMA map them, it will not have any problems with data the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * modifies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct ks8851_net {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spinlock_t statelock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) union ks8851_tx_hdr txh ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 rxd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 txd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 msg_enable ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u16 tx_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 rc_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u16 rc_rxqcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u16 rc_ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct mii_if_info mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct ks8851_rxctrl rxctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct work_struct rxctrl_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct sk_buff_head txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct eeprom_93cx6 eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct regulator *vdd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct regulator *vdd_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void (*lock)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void (*unlock)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int (*rdreg16)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void (*wrreg16)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int reg, unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void (*rdfifo)(struct ks8851_net *ks, u8 *buff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void (*wrfifo)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct sk_buff *txp, bool irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) netdev_tx_t (*start_xmit)(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void (*rx_skb)(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void (*flush_tx_work)(struct ks8851_net *ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int ks8851_probe_common(struct net_device *netdev, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int msg_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ks8851_remove_common(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int ks8851_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ks8851_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static __maybe_unused SIMPLE_DEV_PM_OPS(ks8851_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ks8851_suspend, ks8851_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * ks8851_done_tx - update and then free skbuff after transmitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @ks: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @txb: The buffer transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void __maybe_unused ks8851_done_tx(struct ks8851_net *ks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sk_buff *txb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct net_device *dev = ks->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev->stats.tx_bytes += txb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_kfree_skb(txb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif /* __KS8851_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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