^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for the new Marvell Yukon 2 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _SKY2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _SKY2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* PCI config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) PCI_DEV_REG1 = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) PCI_DEV_REG2 = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PCI_DEV_STATUS = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PCI_DEV_REG3 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PCI_DEV_REG4 = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PCI_DEV_REG5 = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PCI_CFG_REG_0 = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PCI_CFG_REG_1 = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PSM_CONFIG_REG0 = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PSM_CONFIG_REG1 = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PSM_CONFIG_REG2 = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PSM_CONFIG_REG3 = 0x164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PSM_CONFIG_REG4 = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PCI_LDO_CTRL = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Yukon-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum pci_dev_reg_1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum pci_dev_reg_2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum pci_dev_reg_3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) P_CLK_COR_REGS_D0_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) P_CLK_COR_LNK1_D0_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) P_CLK_MAC_LNK1_D0_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) P_CLK_PCI_MST_ARB_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) P_CLK_COR_COMMON_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) P_CLK_COR_LNK1_BMU_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum pci_dev_reg_4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* (Link Training & Status State Machine) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) P_PEX_LTSSM_L1_STAT = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) P_PEX_LTSSM_DET_STAT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* (Active State Power Management) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum pci_dev_reg_5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Bit 31..27: for A3 & later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Bit 26..16: Release Clock on Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Bit 10.. 0: Mask for Gate Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) P_REL_INT_FIFO_N_EMPTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) P_REL_PCIE_EXIT_L1_ST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) P_REL_PCIE_RX_EX_IDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) P_GAT_GPHY_N_REC_PACKET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) P_GAT_INT_FIFO_EMPTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) P_GAT_PCIE_ENTER_L1_ST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) P_GAT_PCIE_RX_EL_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum pci_cfg_reg1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Bit 23..21: Release Clock on Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Bit 20..18: Gate Clock on Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) P_CF1_REL_LDR_NOT_FIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) P_CF1_REL_VMAIN_AVLBL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) P_CF1_REL_PCIE_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) P_CF1_GAT_LDR_NOT_FIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) P_CF1_GAT_PCIE_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) P_CF1_PRST_PHY_CLKREQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) P_CF1_ENA_CFG_LDR_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) P_CF1_ENA_TXBMU_RD_IDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) P_CF1_ENA_TXBMU_WR_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Yukon-Optima */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31, /* AC Present Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PSM_CONFIG_REG1_MUX_PHY_LINK = 1<<27, /* PHY Energy Detect Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23, /* AC Present Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Yukon-Supreme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PSM_CONFIG_REG1_GPHY_ENERGY_STS = 1<<31, /* GPHY Energy Detect Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PSM_CONFIG_REG1_UART_MODE_MSK = 3<<29, /* UART_Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PSM_CONFIG_REG1_VAUX_ONE = 1<<26, /* Tie internal Vaux to 1'b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PSM_CONFIG_REG1_UART_FC_RI_VAL = 1<<25, /* Default value for UART_RI_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PSM_CONFIG_REG1_UART_FC_DCD_VAL = 1<<24, /* Default value for UART_DCD_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PSM_CONFIG_REG1_UART_FC_DSR_VAL = 1<<23, /* Default value for UART_DSR_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PSM_CONFIG_REG1_UART_FC_CTS_VAL = 1<<22, /* Default value for UART_CTS_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PSM_CONFIG_REG1_UART_RST = 1<<19, /* UART_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PSM_CONFIG_REG1_PSM_PCIE_L1_POL = 1<<18, /* PCIE L1 Event Polarity for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PSM_CONFIG_REG1_TIMER_STAT = 1<<17, /* PSM Timer Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PSM_CONFIG_REG1_GPHY_INT = 1<<16, /* GPHY INT Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PSM_CONFIG_REG1_DO_PWDN = 1<<8, /* Do Power Down, Start PSM Scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* PHY Link Detect Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PSM_CONFIG_REG4_DEBUG_TIMER = 1<<1, /* Debug Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum csr_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) B0_RAP = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) B0_CTST = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) B0_POWER_CTRL = 0x0007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) B0_ISRC = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) B0_IMSK = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) B0_HWE_ISRC = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) B0_HWE_IMSK = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Special ISR registers (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) B0_Y2_SP_ISRC2 = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) B0_Y2_SP_ISRC3 = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) B0_Y2_SP_EISR = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) B0_Y2_SP_LISR = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) B0_Y2_SP_ICR = 0x002c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) B2_MAC_1 = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) B2_MAC_2 = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) B2_MAC_3 = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) B2_CONN_TYP = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) B2_PMD_TYP = 0x0119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) B2_MAC_CFG = 0x011a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) B2_CHIP_ID = 0x011b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) B2_E_0 = 0x011c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) B2_Y2_CLK_GATE = 0x011d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) B2_Y2_HW_RES = 0x011e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) B2_E_3 = 0x011f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) B2_Y2_CLK_CTRL = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) B2_TI_INI = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) B2_TI_VAL = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) B2_TI_CTRL = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) B2_TI_TEST = 0x0139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) B2_TST_CTRL1 = 0x0158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) B2_TST_CTRL2 = 0x0159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) B2_GP_IO = 0x015c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) B2_I2C_CTRL = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) B2_I2C_DATA = 0x0164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) B2_I2C_IRQ = 0x0168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) B2_I2C_SW = 0x016c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) Y2_PEX_PHY_DATA = 0x0170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) Y2_PEX_PHY_ADDR = 0x0172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) B3_RAM_ADDR = 0x0180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) B3_RAM_DATA_LO = 0x0184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) B3_RAM_DATA_HI = 0x0188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* RAM Interface Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * not usable in SW. Please notice these are NOT real timeouts, these are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * the number of qWords transferred continuously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RAM_BUFFER(port, reg) (reg | (port <<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) B3_RI_WTO_R1 = 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) B3_RI_WTO_XA1 = 0x0191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) B3_RI_WTO_XS1 = 0x0192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) B3_RI_RTO_R1 = 0x0193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) B3_RI_RTO_XA1 = 0x0194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) B3_RI_RTO_XS1 = 0x0195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) B3_RI_WTO_R2 = 0x0196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) B3_RI_WTO_XA2 = 0x0197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) B3_RI_WTO_XS2 = 0x0198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) B3_RI_RTO_R2 = 0x0199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) B3_RI_RTO_XA2 = 0x019a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) B3_RI_RTO_XS2 = 0x019b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) B3_RI_TO_VAL = 0x019c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) B3_RI_CTRL = 0x01a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) B3_RI_TEST = 0x01a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) B3_MA_TOINI_RX1 = 0x01b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) B3_MA_TOINI_RX2 = 0x01b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) B3_MA_TOINI_TX1 = 0x01b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) B3_MA_TOINI_TX2 = 0x01b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) B3_MA_TOVAL_RX1 = 0x01b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) B3_MA_TOVAL_RX2 = 0x01b5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) B3_MA_TOVAL_TX1 = 0x01b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) B3_MA_TOVAL_TX2 = 0x01b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) B3_MA_TO_CTRL = 0x01b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) B3_MA_TO_TEST = 0x01ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) B3_MA_RCINI_RX1 = 0x01c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) B3_MA_RCINI_RX2 = 0x01c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) B3_MA_RCINI_TX1 = 0x01c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) B3_MA_RCINI_TX2 = 0x01c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) B3_MA_RCVAL_RX1 = 0x01c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) B3_MA_RCVAL_RX2 = 0x01c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) B3_MA_RCVAL_TX1 = 0x01c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) B3_MA_RCVAL_TX2 = 0x01c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) B3_MA_RC_CTRL = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) B3_MA_RC_TEST = 0x01ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) B3_PA_TOINI_RX1 = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) B3_PA_TOINI_RX2 = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) B3_PA_TOINI_TX1 = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) B3_PA_TOINI_TX2 = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) B3_PA_TOVAL_RX1 = 0x01e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) B3_PA_TOVAL_RX2 = 0x01e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) B3_PA_TOVAL_TX1 = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) B3_PA_TOVAL_TX2 = 0x01ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) B3_PA_CTRL = 0x01f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) B3_PA_TEST = 0x01f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) Y2_CFG_SPC = 0x1c00, /* PCI config space region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* B0_CTST 24 bit Control/Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CS_STOP_DONE = 1<<5, /* Stop Master is finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CS_MRST_CLR = 1<<3, /* Clear Master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CS_MRST_SET = 1<<2, /* Set Master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CS_RST_CLR = 1<<1, /* Clear Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) CS_RST_SET = 1, /* Set Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PC_VAUX_ON = 1<<3, /* Switch VAUX On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PC_VCC_ON = 1<<1, /* Switch VCC On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PC_VCC_OFF = 1<<0, /* Switch VCC Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) Y2_IS_CPU_TO = 1<<28, /* CPU Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) Y2_IS_ERROR = Y2_IS_HW_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) IS_ERR_MSK = 0x00003fff,/* All Error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) IS_IRQ_STAT = 1<<10, /* IRQ status exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Hardware error interrupt mask for Yukon 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DPT_START = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DPT_STOP = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* B2_TST_CTRL1 8 bit Test Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* B2_GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GLB_GPIO_TEST_SEL_BASE = 1<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Bit 3.. 2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* B2_CHIP_ID 8 bit Chip Identification Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) enum yukon_xl_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CHIP_REV_YU_XL_A0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CHIP_REV_YU_XL_A1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CHIP_REV_YU_XL_A2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) CHIP_REV_YU_XL_A3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) enum yukon_ec_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) enum yukon_ec_u_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CHIP_REV_YU_EC_U_A0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CHIP_REV_YU_EC_U_A1 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) CHIP_REV_YU_EC_U_B0 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) CHIP_REV_YU_EC_U_B1 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum yukon_fe_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CHIP_REV_YU_FE_A1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CHIP_REV_YU_FE_A2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) enum yukon_fe_p_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CHIP_REV_YU_FE2_A0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) enum yukon_ex_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) CHIP_REV_YU_EX_A0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CHIP_REV_YU_EX_B0 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) enum yukon_supr_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CHIP_REV_YU_SU_A0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CHIP_REV_YU_SU_B0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CHIP_REV_YU_SU_B1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) enum yukon_prm_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CHIP_REV_YU_PRM_Z1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CHIP_REV_YU_PRM_A0 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* B2_TI_CTRL 8 bit Timer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) TIM_START = 1<<2, /* Start Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) TIM_STOP = 1<<1, /* Stop Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* B2_TI_TEST 8 Bit Timer Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) TIM_T_ON = 1<<2, /* Test mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) TIM_T_OFF = 1<<1, /* Test mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) TIM_T_STEP = 1<<0, /* Test step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PEX_DB_ACCESS = 1<<30, /* Access to debug register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Bit 31..19: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* RAM Interface Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* B3_RI_CTRL 16 bit RAM Interface Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SK_RI_TO_53 36 /* RAM interface timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Port related registers FIFO, and Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SK_REG(port,reg) (((port)<<7)+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* TXA_CTRL 8 bit Tx Arbiter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TXA_START_RC = 1<<3, /* Start sync Rate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Bank 4 - 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RSS_KEY = 0x0220, /* RSS Key setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RSS_CFG = 0x0248, /* RSS Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) HASH_TCP_IPV6_EX_CTRL = 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) HASH_IPV6_EX_CTRL = 1<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) HASH_TCP_IPV6_CTRL = 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) HASH_IPV6_CTRL = 1<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) HASH_TCP_IPV4_CTRL = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) HASH_IPV4_CTRL = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) HASH_ALL = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Queue Register Offsets, use Q_ADDR() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) B8_Q_REGS = 0x0400, /* base of Queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) Q_D = 0x00, /* 8*32 bit Current Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) Q_DONE = 0x24, /* 16 bit Done Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) Q_BC = 0x30, /* 32 bit Current Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) Q_TEST = 0x38, /* 32 bit Test/Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Yukon-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) Q_WM = 0x40, /* 16 bit FIFO Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) Q_AL = 0x42, /* 8 bit FIFO Alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) Q_RL = 0x4a, /* 8 bit FIFO Read Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) Q_WL = 0x4e, /* 8 bit FIFO Write Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Q_TEST 32 bit Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Hardware testbits not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) Y2_B8_PREF_REGS = 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PREF_UNIT_MASK_IDX = 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* RAM Buffer Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) RB_END = 0x04,/* 32 bit RAM Buffer End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Receive and Transmit Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) Q_R1 = 0x0000, /* Receive Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) Q_R2 = 0x0080, /* Receive Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Different PHY Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PHY_ADDR_MARV = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Receive GMAC FIFO (YUKON and Yukon-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Q_BC 32 bit Current Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* BMU Control Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Q_CSR 32 bit BMU Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Rx BMU Control / Status Registers (Yukon-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) BMU_IDLE = 1<<31, /* BMU Idle State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) BMU_START = 1<<8, /* Start Rx/Tx Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) BMU_FIFO_RST = 1<<4, /* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) BMU_OP_ON = 1<<3, /* BMU Operational On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) BMU_OP_OFF = 1<<2, /* BMU Operational Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) BMU_RST_SET = 1<<0, /* Set BMU Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) BMU_FIFO_ENA | BMU_OP_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) BMU_WM_DEFAULT = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) BMU_WM_PEX = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Tx BMU Control / Status Registers (Yukon-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Bit 31: same as for Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* TBMU_TEST 0x06B8 Transmit BMU Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) TBMU_TEST_TEST_RSPTR_ON = 1<<22, /* Testmode Shadow Read Ptr On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) TBMU_TEST_TEST_RSPTR_OFF = 1<<21, /* Testmode Shadow Read Ptr Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) TBMU_TEST_TESTSTEP_RSPTR = 1<<20, /* Teststep Shadow Read Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) TBMU_TEST_TEST_RPTR_ON = 1<<18, /* Testmode Read Ptr On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) TBMU_TEST_TEST_RPTR_OFF = 1<<17, /* Testmode Read Ptr Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) TBMU_TEST_TESTSTEP_RPTR = 1<<16, /* Teststep Read Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) TBMU_TEST_TEST_WSPTR_ON = 1<<14, /* Testmode Shadow Write Ptr On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) TBMU_TEST_TEST_WSPTR_OFF = 1<<13, /* Testmode Shadow Write Ptr Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) TBMU_TEST_TESTSTEP_WSPTR = 1<<12, /* Teststep Shadow Write Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) TBMU_TEST_TEST_WPTR_ON = 1<<10, /* Testmode Write Ptr On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) TBMU_TEST_TEST_WPTR_OFF = 1<<9, /* Testmode Write Ptr Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) TBMU_TEST_TESTSTEP_WPTR = 1<<8, /* Teststep Write Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) TBMU_TEST_TEST_REQ_NB_ON = 1<<6, /* Testmode Req Nbytes/Addr On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) TBMU_TEST_TEST_REQ_NB_OFF = 1<<5, /* Testmode Req Nbytes/Addr Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) TBMU_TEST_TESTSTEP_REQ_NB = 1<<4, /* Teststep Req Nbytes/Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) TBMU_TEST_TEST_DONE_IDX_ON = 1<<2, /* Testmode Done Index On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) TBMU_TEST_TEST_DONE_IDX_OFF = 1<<1, /* Testmode Done Index Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TBMU_TEST_TESTSTEP_DONE_IDX = 1<<0, /* Teststep Done Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* RB_START 32 bit RAM Buffer Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* RB_END 32 bit RAM Buffer End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* RB_WP 32 bit RAM Buffer Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* RB_RP 32 bit RAM Buffer Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* RB_PC 32 bit RAM Buffer Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* RB_LEV 32 bit RAM Buffer Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* RB_TST2 8 bit RAM Buffer Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* RB_TST1 8 bit RAM Buffer Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* RB_CTRL 8 bit RAM Buffer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Transmit GMAC FIFO (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* Threshold values for Yukon-EC Ultra and Extreme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Descriptor Poll Timer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Time Stamp Timer Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Polling Unit Registers (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* ASF Subsystem Registers (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Status BMU Registers (Yukon-2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* FIFO Control/Status Registers (Yukon-2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Level and ISR Timer Registers (Yukon-2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) LINKLED_OFF = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) LINKLED_ON = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) LINKLED_LINKSYNC_OFF = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) LINKLED_LINKSYNC_ON = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) LINKLED_BLINK_OFF = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) LINKLED_BLINK_ON = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* GMAC and GPHY Control Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* WOL Pattern Length Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* WOL Pattern Counter Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define WOL_REGS(port, x) (x + (port)*0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * Marvel-PHY Registers, indirect addressed over GMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Marvel-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* different Marvell PHY Ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PHY_BCOM_ID1_A1 = 0x6041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PHY_BCOM_ID1_B2 = 0x6043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PHY_BCOM_ID1_C0 = 0x6044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PHY_BCOM_ID1_C5 = 0x6047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Advertisement register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PHY_AN_100HALF | PHY_AN_100FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Bit 9..8: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /** Marvell-Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PHY_M_AN_RF = 1<<13, /* Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* special defines for FIBER (88E1011S only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PHY_M_PS_JABBER = 1<<0, /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PHY_M_IS_AN_PR = 1<<12, /* Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PHY_M_IS_JABBER = 1<<0, /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) | PHY_M_IS_DUP_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* !!! Errata in spec. (1 = disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* 00=1x; 01=2x; 10=3x; 11=4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* 00=dis; 01=1x; 10=2x; 11=3x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* 000=1x; 001=2x; 010=3x; 011=4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* 01X=0; 110=2.5; 111=25 (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* !!! Errata in spec. (1 = disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* 100=5x; 101=6x; 110=7x; 111=8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) MAC_TX_CLK_0_MHZ = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) MAC_TX_CLK_2_5_MHZ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) MAC_TX_CLK_25_MHZ = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PULS_NO_STR = 0,/* no pulse stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PULS_21MS = 1,/* 21 ms to 42 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PULS_42MS = 2,/* 42 ms to 84 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PULS_84MS = 3,/* 84 ms to 170 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) PULS_170MS = 4,/* 170 ms to 340 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PULS_340MS = 5,/* 340 ms to 670 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PULS_670MS = 6,/* 670 ms to 1.3 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) PULS_1300MS = 7,/* 1.3 s to 2.7 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) BLINK_42MS = 0,/* 42 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) BLINK_84MS = 1,/* 84 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) BLINK_170MS = 2,/* 170 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) BLINK_340MS = 3,/* 340 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) BLINK_670MS = 4,/* 670 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) enum led_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) MO_LED_NORM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) MO_LED_BLINK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MO_LED_OFF = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) MO_LED_ON = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /* Bit 15..12: reserved (used internally) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) LED_PAR_CTRL_COLX = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) LED_PAR_CTRL_ERROR = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) LED_PAR_CTRL_DUPLEX = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) LED_PAR_CTRL_DP_COL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) LED_PAR_CTRL_SPEED = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) LED_PAR_CTRL_LINK = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) LED_PAR_CTRL_TX = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) LED_PAR_CTRL_RX = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) LED_PAR_CTRL_ACT = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) LED_PAR_CTRL_LNK_RX = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) LED_PAR_CTRL_LNK_AC = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) LED_PAR_CTRL_ACT_BL = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) LED_PAR_CTRL_TX_BL = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) LED_PAR_CTRL_RX_BL = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) LED_PAR_CTRL_COL_BL = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) LED_PAR_CTRL_INACT = 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) PHY_M_MAC_MD_COPPER = 5,/* Copper only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* GMAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* Source Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* Multicast Address Hash Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* Interrupt Source Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Interrupt Mask Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* Serial Management Interface (SMI) Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* MIB Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * MIB Counters base address definitions (low word) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * use offset 4 for access to high word (32 bit r/o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* GMAC Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define TX_COL_DEF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* GM_RX_CTRL 16 bit r/w Receive Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) TX_JAM_LEN_DEF = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) TX_JAM_IPG_DEF = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) TX_IPG_JAM_DEF = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) TX_BOF_LIM_DEF = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) GM_SMOD_LIMIT_4 = 1<<10, /* 4 consecutive Tx trials */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) GM_SMOD_VLAN_ENA = 1<<9, /* Enable VLAN (Max. Frame Len) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) GM_SMOD_JUMBO_ENA = 1<<8, /* Enable Jumbo (Max. Frame Len) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define DATA_BLIND_DEF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define IPG_DATA_DEF_1000 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define IPG_DATA_DEF_10_100 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /* Receive Frame Status Encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) GMR_FS_VLAN = 1<<13, /* VLAN Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) GMR_FS_JABBER = 1<<12, /* Jabber Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) GMR_FS_MC = 1<<10, /* Multicast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) GMR_FS_BC = 1<<9, /* Broadcast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) GMR_FS_MII_ERR = 1<<5, /* MII Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) GMR_FS_FRAGMENT = 1<<3, /* Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) GMR_FS_MII_ERR | GMR_FS_BAD_FC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) GMR_FS_UN_SIZE | GMR_FS_JABBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) RX_GCLKMAC_ENA = 1<<31, /* RX MAC Clock Gating Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) RX_GCLKMAC_OFF = 1<<30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) RX_STFW_DIS = 1<<29, /* RX Store and Forward Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) RX_STFW_ENA = 1<<28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) RX_TRUNC_ON = 1<<27, /* enable packet truncation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) RX_MACSEC_FLUSH_ON = 1<<23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) RX_MACSEC_FLUSH_OFF = 1<<22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) RX_MACSEC_ASF_FLUSH_ON = 1<<21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) GMF_OPER_ON = 1<<3, /* Operational Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) RX_IPV6_SA_MOB_ENA = 1<<9, /* IPv6 SA Mobility Support Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) RX_IPV6_SA_MOB_DIS = 1<<8, /* IPv6 SA Mobility Support Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) RX_IPV6_DA_MOB_ENA = 1<<7, /* IPv6 DA Mobility Support Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) RX_IPV6_DA_MOB_DIS = 1<<6, /* IPv6 DA Mobility Support Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) RX_PTR_SYNCDLY_ENA = 1<<5, /* Pointers Delay Synch Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) RX_PTR_SYNCDLY_DIS = 1<<4, /* Pointers Delay Synch Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) RX_ASF_NEWFLAG_ENA = 1<<3, /* RX ASF Flag New Logic Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) RX_ASF_NEWFLAG_DIS = 1<<2, /* RX ASF Flag New Logic Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) TX_STFW_DIS = 1<<31,/* Disable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) TX_STFW_ENA = 1<<30,/* Enable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) TX_PCI_JUM_ENA = 1<<23,/* PCI Jumbo Mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) TX_PCI_JUM_DIS = 1<<22,/* PCI Jumbo Mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* HCU_CCSR CPU Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* Clock Stretching Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) HCU_CCSR_CS_TO = 1<<25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) HCU_CCSR_SET_SYNC_CPU = 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* Microcontroller State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) HCU_CCSR_UC_STATE_MSK = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) HCU_CCSR_UC_STATE_BASE = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) HCU_CCSR_ASF_RESET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) HCU_CCSR_ASF_HALTED = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) HCU_CCSR_ASF_RUNNING = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* HCU_HCSR Host Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) GMC_SET_RST = 1<<15,/* MAC SEC RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) GMC_PAUSE_ON = 1<<3, /* Pause On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) GMC_PAUSE_OFF = 1<<2, /* Pause Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) GMC_RST_SET = 1<<0, /* Set GMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) GPC_SPEED = 3<<27, /* PHY speed (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) GPC_LINK = 1<<26, /* Link up (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) GPC_DUPLEX = 1<<25, /* Duplex (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) GPC_TSTMODE = 1<<22, /* Test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) GPC_REG18 = 1<<21, /* Reg18 Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) GPC_REG12SEL = 3<<19, /* Reg12 power setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) GPC_REG18SEL = 3<<17, /* Reg18 power setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) GPC_LEDMUX = 3<<14, /* LED Mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) GPC_INTPOL = 1<<13, /* Interrupt polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) GPC_DETECT = 1<<12, /* Energy detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) GPC_SLAVE = 1<<10, /* Slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) GPC_PAUSE = 1<<9, /* Pause enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) GPC_LEDCTL = 3<<6, /* GPHY Leds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) GPC_RST_SET = 1<<0, /* Set GPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define GMAC_DEF_MSK (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) enum { /* Bits 15.. 2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) WOL_CTL_LINK_CHG_OCC = 1<<15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) WOL_CTL_MAGIC_PKT_OCC = 1<<14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) WOL_CTL_PATTERN_OCC = 1<<13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) WOL_CTL_CLEAR_RESULT = 1<<12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* Control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) UDPTCP = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) CALSUM = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) WR_SUM = 1<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) INIT_SUM= 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) LOCK_SUM= 1<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) INS_VLAN= 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) EOP = 1<<7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) HW_OWNER = 1<<7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) OP_TCPWRITE = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) OP_TCPSTART = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) OP_TCPINIT = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) OP_TCPLCK = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) OP_TCPCHKSUM = OP_TCPSTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) OP_ADDR64 = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) OP_VLAN = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) OP_LRGLEN = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) OP_MSS = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) OP_MSSVLAN = OP_MSS | OP_VLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) OP_BUFFER = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) OP_PACKET = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) OP_LARGESEND = 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) OP_LSOV2 = 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /* YUKON-2 STATUS opcodes defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) OP_RXSTAT = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) OP_RXTIMESTAMP = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) OP_RXVLAN = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) OP_RXCHKS = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) OP_RSS_HASH = 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) OP_TXINDEXLE = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) OP_MACSEC = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) OP_PUTIDX = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) enum status_css {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) CSS_ISUDP = 1<<6, /* packet is a UDP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) CSS_ISTCP = 1<<5, /* packet is a TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) CSS_LINK_BIT = 1<<0, /* port number (legacy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* Yukon 2 hardware interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) struct sky2_tx_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) __le16 length; /* also vlan tag or checksum start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct sky2_rx_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) __le16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) struct sky2_status_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) __le32 status; /* also checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) __le16 length; /* also vlan tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) u8 css;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct tx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define TX_MAP_SINGLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define TX_MAP_PAGE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) DEFINE_DMA_UNMAP_ADDR(mapaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) DEFINE_DMA_UNMAP_LEN(maplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct rx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) dma_addr_t data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) DEFINE_DMA_UNMAP_LEN(data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) enum flow_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) FC_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) FC_TX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) FC_RX = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) FC_BOTH = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct sky2_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct u64_stats_sync syncp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) u64 packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) u64 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct sky2_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) struct sky2_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) unsigned port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) spinlock_t phy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct tx_ring_info *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) struct sky2_tx_le *tx_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct sky2_stats tx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) u16 tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) u16 tx_cons; /* next le to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) u16 tx_prod; /* next le to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) u16 tx_next; /* debug only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) u16 tx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) u16 tx_last_mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) u32 tx_last_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) u32 tx_tcpsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct sky2_rx_le *rx_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct sky2_stats rx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) u16 rx_next; /* next re to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) u16 rx_put; /* next le index to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) u16 rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) u16 rx_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) u16 rx_nfrags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) unsigned long last_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) unsigned long last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) u32 mac_rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) u8 mac_lev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) u8 fifo_rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) u8 fifo_lev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) } check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) dma_addr_t rx_le_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) dma_addr_t tx_le_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) u16 advertising; /* ADVERTISED_ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) u16 speed; /* SPEED_1000, SPEED_100, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) u8 wol; /* WAKE_ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define SKY2_FLAG_AUTO_SPEED 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define SKY2_FLAG_AUTO_PAUSE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) enum flow_control flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) enum flow_control flow_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #ifdef CONFIG_SKY2_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) struct sky2_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) struct net_device *dev[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define SKY2_HW_USE_MSI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define SKY2_HW_FIBRE_PHY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define SKY2_HW_GIGABIT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define SKY2_HW_NEWER_PHY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define SKY2_HW_RAM_BUFFER 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) #define SKY2_HW_RSS_BROKEN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define SKY2_HW_VLAN_BROKEN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define SKY2_HW_RSS_CHKSUM 0x00000400 /* RSS requires chksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define SKY2_HW_IRQ_SETUP 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) u8 chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) u8 pmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) u8 ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct sky2_status_le *st_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) u32 st_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) u32 st_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dma_addr_t st_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) struct timer_list watchdog_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) struct work_struct restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) wait_queue_head_t msi_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) char irq_name[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static inline int sky2_is_copper(const struct sky2_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) return !(hw->flags & SKY2_HW_FIBRE_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* Register accessor for memory mapped device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return readl(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return readw(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return readb(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) writel(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) writew(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) writeb(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* Yukon PHY related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define SK_GMAC_REG(port,reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #define GM_PHY_RETRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) return sky2_read16(hw, SK_GMAC_REG(port,reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) unsigned base = SK_GMAC_REG(port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) return (u32) sky2_read16(hw, base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) | (u32) sky2_read16(hw, base+4) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) unsigned base = SK_GMAC_REG(port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) return (u64) sky2_read16(hw, base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) | (u64) sky2_read16(hw, base+4) << 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) | (u64) sky2_read16(hw, base+8) << 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) | (u64) sky2_read16(hw, base+12) << 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* There is no way to atomically read32 bit values from PHY, so retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) val = gma_read32(hw, port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) } while (gma_read32(hw, port, reg) != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) val = gma_read64(hw, port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) } while (gma_read64(hw, port, reg) != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) sky2_write16(hw, SK_GMAC_REG(port,r), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) const u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* PCI config space access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) return sky2_read32(hw, Y2_CFG_SPC + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) return sky2_read16(hw, Y2_CFG_SPC + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) sky2_write32(hw, Y2_CFG_SPC + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) sky2_write16(hw, Y2_CFG_SPC + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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