^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for the new Marvell Yukon / SysKonnect driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _SKGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _SKGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* PCI config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PCI_DEV_REG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PCI_PHY_COMA 0x8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PCI_VIO 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCI_DEV_REG2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum csr_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) B0_RAP = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) B0_CTST = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) B0_LED = 0x0006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) B0_POWER_CTRL = 0x0007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) B0_ISRC = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) B0_IMSK = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) B0_HWE_ISRC = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) B0_HWE_IMSK = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) B0_SP_ISRC = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) B0_XM1_IMSK = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) B0_XM1_ISRC = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) B0_XM1_PHY_ADDR = 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) B0_XM1_PHY_DATA = 0x0034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) B0_XM2_IMSK = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) B0_XM2_ISRC = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) B0_XM2_PHY_ADDR = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) B0_XM2_PHY_DATA = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) B0_R1_CSR = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) B0_R2_CSR = 0x0064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) B0_XS1_CSR = 0x0068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) B0_XA1_CSR = 0x006c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) B0_XS2_CSR = 0x0070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) B0_XA2_CSR = 0x0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) B2_MAC_1 = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) B2_MAC_2 = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) B2_MAC_3 = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) B2_CONN_TYP = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) B2_PMD_TYP = 0x0119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) B2_MAC_CFG = 0x011a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) B2_CHIP_ID = 0x011b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) B2_E_0 = 0x011c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) B2_E_1 = 0x011d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) B2_E_2 = 0x011e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) B2_E_3 = 0x011f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) B2_FAR = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) B2_FDP = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) B2_LD_CTRL = 0x0128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) B2_LD_TEST = 0x0129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) B2_TI_INI = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) B2_TI_VAL = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) B2_TI_CTRL = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) B2_TI_TEST = 0x0139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) B2_IRQM_INI = 0x0140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) B2_IRQM_VAL = 0x0144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) B2_IRQM_CTRL = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) B2_IRQM_TEST = 0x0149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) B2_IRQM_MSK = 0x014c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) B2_IRQM_HWE_MSK = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) B2_TST_CTRL1 = 0x0158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) B2_TST_CTRL2 = 0x0159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) B2_GP_IO = 0x015c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) B2_I2C_CTRL = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) B2_I2C_DATA = 0x0164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) B2_I2C_IRQ = 0x0168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) B2_I2C_SW = 0x016c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) B2_BSC_INI = 0x0170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) B2_BSC_VAL = 0x0174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) B2_BSC_CTRL = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) B2_BSC_STAT = 0x0179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) B2_BSC_TST = 0x017a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) B3_RAM_ADDR = 0x0180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) B3_RAM_DATA_LO = 0x0184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) B3_RAM_DATA_HI = 0x0188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) B3_RI_WTO_R1 = 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) B3_RI_WTO_XA1 = 0x0191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) B3_RI_WTO_XS1 = 0x0192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) B3_RI_RTO_R1 = 0x0193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) B3_RI_RTO_XA1 = 0x0194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) B3_RI_RTO_XS1 = 0x0195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) B3_RI_WTO_R2 = 0x0196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) B3_RI_WTO_XA2 = 0x0197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) B3_RI_WTO_XS2 = 0x0198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) B3_RI_RTO_R2 = 0x0199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) B3_RI_RTO_XA2 = 0x019a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) B3_RI_RTO_XS2 = 0x019b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) B3_RI_TO_VAL = 0x019c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) B3_RI_CTRL = 0x01a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) B3_RI_TEST = 0x01a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) B3_MA_TOINI_RX1 = 0x01b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) B3_MA_TOINI_RX2 = 0x01b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) B3_MA_TOINI_TX1 = 0x01b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) B3_MA_TOINI_TX2 = 0x01b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) B3_MA_TOVAL_RX1 = 0x01b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) B3_MA_TOVAL_RX2 = 0x01b5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) B3_MA_TOVAL_TX1 = 0x01b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) B3_MA_TOVAL_TX2 = 0x01b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) B3_MA_TO_CTRL = 0x01b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) B3_MA_TO_TEST = 0x01ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) B3_MA_RCINI_RX1 = 0x01c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) B3_MA_RCINI_RX2 = 0x01c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) B3_MA_RCINI_TX1 = 0x01c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) B3_MA_RCINI_TX2 = 0x01c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) B3_MA_RCVAL_RX1 = 0x01c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) B3_MA_RCVAL_RX2 = 0x01c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) B3_MA_RCVAL_TX1 = 0x01c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) B3_MA_RCVAL_TX2 = 0x01c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) B3_MA_RC_CTRL = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) B3_MA_RC_TEST = 0x01ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) B3_PA_TOINI_RX1 = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) B3_PA_TOINI_RX2 = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) B3_PA_TOINI_TX1 = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) B3_PA_TOINI_TX2 = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) B3_PA_TOVAL_RX1 = 0x01e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) B3_PA_TOVAL_RX2 = 0x01e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) B3_PA_TOVAL_TX1 = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) B3_PA_TOVAL_TX2 = 0x01ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) B3_PA_CTRL = 0x01f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) B3_PA_TEST = 0x01f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* B0_CTST 16 bit Control/Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CS_STOP_DONE = 1<<5, /* Stop Master is finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CS_MRST_CLR = 1<<3, /* Clear Master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CS_MRST_SET = 1<<2, /* Set Master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CS_RST_CLR = 1<<1, /* Clear Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CS_RST_SET = 1, /* Set Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* B0_LED 8 Bit LED register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Bit 7.. 2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LED_STAT_ON = 1<<1, /* Status LED on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) LED_STAT_OFF = 1, /* Status LED off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PC_VAUX_ON = 1<<3, /* Switch VAUX On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PC_VCC_ON = 1<<1, /* Switch VCC On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PC_VCC_OFF = 1<<0, /* Switch VCC Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IS_HW_ERR = 1<<31, /* Interrupt HW Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Bit 30: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IS_IRQ_SW = 1<<24, /* SW forced IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* IRQ from PHY (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IS_TIMINT = 1<<22, /* IRQ from Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Receive Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IS_R1_F = 1<<16, /* Q_R1 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Receive Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IS_R2_F = 1<<13, /* Q_R2 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Synchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Asynchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Synchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Asynchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IS_IRQ_STAT = 1<<10, /* IRQ status exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) | IS_RAM_RD_PAR | IS_RAM_WR_PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) | IS_M1_PAR_ERR | IS_M2_PAR_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* B2_TST_CTRL1 8 bit Test Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Bit 3.. 2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* B2_CHIP_ID 8 bit Chip Identification Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* B2_TI_CTRL 8 bit Timer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) TIM_START = 1<<2, /* Start Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TIM_STOP = 1<<1, /* Stop Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* B2_TI_TEST 8 Bit Timer Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) TIM_T_ON = 1<<2, /* Test mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) TIM_T_OFF = 1<<1, /* Test mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TIM_T_STEP = 1<<0, /* Test step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* B2_GP_IO 32 bit General Purpose I/O Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GP_IO_9 = 1<<9, /* IO_9 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) GP_IO_8 = 1<<8, /* IO_8 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GP_IO_7 = 1<<7, /* IO_7 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GP_IO_6 = 1<<6, /* IO_6 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) GP_IO_5 = 1<<5, /* IO_5 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) GP_IO_4 = 1<<4, /* IO_4 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) GP_IO_3 = 1<<3, /* IO_3 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) GP_IO_2 = 1<<2, /* IO_2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GP_IO_1 = 1<<1, /* IO_1 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) GP_IO_0 = 1<<0, /* IO_0 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Descriptor Bit Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* TxCtrl Transmit Buffer Control Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* RxCtrl Receive Buffer Control Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) BMU_STF = 1<<30, /* Start of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) BMU_EOF = 1<<29, /* End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* TxCtrl specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* RxCtrl specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Bit 23..16: BMU Check Opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) BMU_CHECK = 0x55<<16, /* Default BMU check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BSC_START = 1<<1, /* Start Blink Source Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) BSC_STOP = 1<<0, /* Stop Blink Source Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* B2_BSC_STAT 8 bit Blink Source Counter Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BSC_T_ON = 1<<2, /* Test mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BSC_T_OFF = 1<<1, /* Test mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BSC_T_STEP = 1<<0, /* Test step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Bit 31..19: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* RAM Interface Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* B3_RI_CTRL 16 bit RAM Iface Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* MAC Arbiter Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SK_PKT_TO_MAX 0xffff /* Maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SK_RI_TO_53 36 /* RAM interface timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Packet Arbiter Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* TXA_CTRL 8 bit Tx Arbiter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) TXA_START_RC = 1<<3, /* Start sync Rate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Bank 4 - 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Queue Register Offsets, use Q_ADDR() to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) B8_Q_REGS = 0x0400, /* base of Queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) Q_D = 0x00, /* 8*32 bit Current Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) Q_BC = 0x30, /* 32 bit Current Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) Q_F = 0x38, /* 32 bit Flag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) Q_T1 = 0x3c, /* 32 bit Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) Q_T2 = 0x40, /* 32 bit Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) Q_T3 = 0x44, /* 32 bit Test Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* RAM Buffer Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RB_END = 0x04,/* 32 bit RAM Buffer End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Receive and Transmit Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) Q_R1 = 0x0000, /* Receive Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) Q_R2 = 0x0080, /* Receive Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Different MAC Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SK_MAC_XMAC = 0, /* Xaqti XMAC II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SK_MAC_GMAC = 1, /* Marvell GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Different PHY Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SK_PHY_XMAC = 0,/* integrated in XMAC II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SK_PHY_NAT = 3,/* National DP83891 [not supported] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* PHY addresses (bits 12..8 of PHY address reg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PHY_ADDR_XMAC = 0<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PHY_ADDR_BCOM = 1<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* GPHY address (bits 15..11 of SMI control reg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PHY_ADDR_MARV = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MFF_PC_INC = 1<<0, /* Packet Counter Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MFF_WP_INC = 1<<4, /* Write Pointer Increm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Link LED Counter Registers (GENESIS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) LED_START = 1<<2, /* Start Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) LED_STOP = 1<<1, /* Stop Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) LED_T_ON = 1<<2, /* LED Counter Test mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) LED_T_STEP = 1<<0, /* LED Counter Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* LNK_LED_REG 8 bit Link LED Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) LED_BLK_ON = 1<<5, /* Link LED Blinking On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) LED_REG_ON = 1<<1, /* switch LED on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) LED_REG_OFF = 1<<0, /* switch LED off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Receive GMAC FIFO (YUKON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* TXA_TEST 8 bit Tx Arbiter Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* TXA_STAT 8 bit Tx Arbiter Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Q_BC 32 bit Current Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* BMU Control Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Q_CSR 32 bit BMU Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) CSR_HPI_RUN = 1<<17, /* Release HPI SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) CSR_START = 1<<4, /* Start Rx/Tx Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CSR_TRANS_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) CSR_TRANS_RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Q_F 32 bit Flag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) F_WM_REACHED = 1<<25, /* Watermark reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* RB_START 32 bit RAM Buffer Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* RB_END 32 bit RAM Buffer End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* RB_WP 32 bit RAM Buffer Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* RB_RP 32 bit RAM Buffer Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* RB_PC 32 bit RAM Buffer Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* RB_LEV 32 bit RAM Buffer Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* RB_TST2 8 bit RAM Buffer Test Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* RB_TST1 8 bit RAM Buffer Test Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* RB_CTRL 8 bit RAM Buffer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Counter and Timer constants, for a host clock of 62.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* 215 ms at 78.12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define SK_FACT_62 100 /* is given in percent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Transmit GMAC FIFO (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Descriptor Poll Timer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Time Stamp Timer Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) LINKLED_OFF = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) LINKLED_ON = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) LINKLED_LINKSYNC_OFF = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) LINKLED_LINKSYNC_ON = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) LINKLED_BLINK_OFF = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) LINKLED_BLINK_ON = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* GMAC and GPHY Control Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* WOL Pattern Length Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* WOL Pattern Counter Registers (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define WOL_REGS(port, x) (x + (port)*0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * Receive Frame Status Encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) XMR_FS_LEN_SHIFT = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * XMR_FS_ERR will be set if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * XMR_FS_ERR unless the corresponding bit in the Receive Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Register is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ,* XMAC-PHY Registers, indirect addressed over the XMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * Broadcom-PHY Registers, indirect addressed over XMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Broadcom-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Marvel-PHY Registers, indirect addressed over GMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Marvel-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* different Broadcom PHY Ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PHY_BCOM_ID1_A1 = 0x6041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PHY_BCOM_ID1_B2 = 0x6043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PHY_BCOM_ID1_C0 = 0x6044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PHY_BCOM_ID1_C5 = 0x6047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* different Marvell PHY Ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Advertisement register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PHY_AN_100HALF | PHY_AN_100FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Xmac Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Broadcom-Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Bit 9..8: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Bit 11: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Bit 9.. 8: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Bit 6: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Bit 4: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PHY_B_DEF_MSK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /** Marvell-Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PHY_M_AN_RF = 1<<13, /* Remote Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* special defines for FIBER (88E1011S only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PHY_M_PS_JABBER = 1<<0, /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PHY_M_IS_AN_PR = 1<<12, /* Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PHY_M_IS_JABBER = 1<<0, /* Jabber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* !!! Errata in spec. (1 = disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* 100=5x; 101=6x; 110=7x; 111=8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) MAC_TX_CLK_0_MHZ = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MAC_TX_CLK_2_5_MHZ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MAC_TX_CLK_25_MHZ = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PULS_NO_STR = 0, /* no pulse stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PULS_21MS = 1, /* 21 ms to 42 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PULS_42MS = 2, /* 42 ms to 84 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PULS_84MS = 3, /* 84 ms to 170 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PULS_170MS = 4, /* 170 ms to 340 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PULS_340MS = 5, /* 340 ms to 670 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PULS_670MS = 6, /* 670 ms to 1.3 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PULS_1300MS = 7, /* 1.3 s to 2.7 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) BLINK_42MS = 0, /* 42 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) BLINK_84MS = 1, /* 84 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) BLINK_170MS = 2, /* 170 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) BLINK_340MS = 3, /* 340 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) BLINK_670MS = 4, /* 670 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Bit 13..12: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) MO_LED_NORM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MO_LED_BLINK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) MO_LED_OFF = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) MO_LED_ON = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* Bit 9.. 4: reserved (88E1011 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* (88E1111 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) CABD_STAT_NORMAL= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) CABD_STAT_SHORT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) CABD_STAT_OPEN = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) CABD_STAT_FAIL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* for 10/100 Fast Ethernet PHY (88E3082 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* Bit 15..12: reserved (used internally) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) LED_PAR_CTRL_COLX = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) LED_PAR_CTRL_ERROR = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) LED_PAR_CTRL_DUPLEX = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) LED_PAR_CTRL_DP_COL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) LED_PAR_CTRL_SPEED = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) LED_PAR_CTRL_LINK = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) LED_PAR_CTRL_TX = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) LED_PAR_CTRL_RX = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) LED_PAR_CTRL_ACT = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) LED_PAR_CTRL_LNK_RX = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) LED_PAR_CTRL_LNK_AC = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) LED_PAR_CTRL_ACT_BL = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) LED_PAR_CTRL_TX_BL = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) LED_PAR_CTRL_RX_BL = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) LED_PAR_CTRL_COL_BL = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) LED_PAR_CTRL_INACT = 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* GMAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Source Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* Multicast Address Hash Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Interrupt Source Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* Interrupt Mask Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Serial Management Interface (SMI) Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* MIB Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * MIB Counters base address definitions (low word) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * use offset 4 for access to high word (32 bit r/o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* GM_MIB_CNT_BASE + 40: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* GM_MIB_CNT_BASE + 168: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* GM_MIB_CNT_BASE + 184: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* GMAC Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define TX_COL_DEF 0x04 /* late collision after 64 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* GM_RX_CTRL 16 bit r/w Receive Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) TX_JAM_LEN_DEF = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) TX_JAM_IPG_DEF = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) TX_IPG_JAM_DEF = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define DATA_BLIND_DEF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define IPG_DATA_DEF 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* Receive Frame Status Encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) GMR_FS_LEN_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) GMR_FS_JABBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* Rx GMAC FIFO Flush Mask (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) GMF_OPER_ON = 1<<3, /* Operational Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) GMC_PAUSE_ON = 1<<3, /* Pause On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) GMC_PAUSE_OFF = 1<<2, /* Pause Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) GMC_RST_SET = 1<<0, /* Set GMAC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) GPC_ANEG_0 = 1<<19, /* ANEG[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) GPC_ANEG_3 = 1<<16, /* ANEG[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) GPC_ANEG_2 = 1<<15, /* ANEG[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) GPC_ANEG_1 = 1<<14, /* ANEG[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* Bits 7..2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) GPC_RST_SET = 1<<0, /* Set GPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* forced speed and duplex mode (don't mix with other ANEG bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define GPC_FRC10MBIT_HALF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define GPC_FRC10MBIT_FULL GPC_ANEG_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define GPC_FRC100MBIT_HALF GPC_ANEG_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* auto-negotiation with limited advertised speeds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* mix only with master/slave settings (for copper) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define GPC_ADV_1000_HALF GPC_ANEG_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define GPC_ADV_1000_FULL GPC_ANEG_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* master/slave settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* only for copper with 1000 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define GPC_FORCE_MASTER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define GPC_FORCE_SLAVE GPC_ANEG_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define GPC_PREF_MASTER GPC_ANEG_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* Bits 15.. 2: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) WOL_CTL_LINK_CHG_OCC = 1<<15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) WOL_CTL_MAGIC_PKT_OCC = 1<<14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) WOL_CTL_PATTERN_OCC = 1<<13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) WOL_CTL_CLEAR_RESULT = 1<<12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define WOL_CTL_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) (WOL_CTL_DIS_PME_ON_LINK_CHG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) WOL_CTL_DIS_PME_ON_PATTERN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) WOL_CTL_DIS_LINK_CHG_UNIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) WOL_CTL_DIS_PATTERN_UNIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) WOL_CTL_DIS_MAGIC_PKT_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define WOL_CTL_PATT_ENA(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* XMAC II registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) XM_SA = 0x0108, /* NA reg r/w Station Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* XM_MMU_CMD 16 bit r/w MMU Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* XM_TX_CMD 16 bit r/w Transmit Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) /* XM_RX_CMD 16 bit r/w Receive Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* inrange error packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* jumbo packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) /* XM_IMSK 16 bit r/w Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* XM_ISRC 16 bit r/o Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) XM_IMSK_DISABLE = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /* XM_HW_CFG 16 bit r/w Hardware Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* XM_TX_THR 16 bit r/w Tx Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /* XM_HT_THR 16 bit r/w Host Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* XM_RX_THR 16 bit r/w Rx Request Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* XM_DEV_ID 32 bit r/o Device ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* XM_MODE 32 bit r/w Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /* extern generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* intern generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* intern generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* intern generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) struct skge_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) u32 next_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) u32 dma_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) u32 dma_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) u16 csum2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) u16 csum1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) u16 csum2_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) u16 csum1_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct skge_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) u32 next_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) u32 dma_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) u32 dma_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) u32 csum_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) u16 csum_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) u16 csum_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) u32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct skge_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) struct skge_element *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) void *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) DEFINE_DMA_UNMAP_ADDR(mapaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) DEFINE_DMA_UNMAP_LEN(maplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) struct skge_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) struct skge_element *to_clean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) struct skge_element *to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) struct skge_element *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) struct skge_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) spinlock_t hw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) struct net_device *dev[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) u8 chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) u8 copper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) u8 ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) u8 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) u32 ram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) u32 ram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) u16 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) spinlock_t phy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) struct tasklet_struct phy_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) char irq_name[]; /* skge@pci:000:04:00.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) enum pause_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) FLOW_MODE_NONE = 1, /* No Flow-Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * just the remote station may send PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) enum pause_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) FLOW_STAT_INDETERMINATED=0, /* indeterminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) FLOW_STAT_NONE, /* No Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) struct skge_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) struct skge_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) struct skge_ring tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) struct skge_ring rx_ring ____cacheline_aligned_in_smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) unsigned int rx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) struct timer_list link_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) enum pause_control flow_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) enum pause_status flow_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) u8 blink_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) u8 wol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) u16 speed; /* SPEED_1000, SPEED_100, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) void *mem; /* PCI memory for rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) unsigned long mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #ifdef CONFIG_SKGE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /* Register accessor for memory mapped device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static inline u32 skge_read32(const struct skge_hw *hw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return readl(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static inline u16 skge_read16(const struct skge_hw *hw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return readw(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static inline u8 skge_read8(const struct skge_hw *hw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) return readb(hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) writel(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) writew(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) writeb(val, hw->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) /* MAC Related Registers inside the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) #define SK_XMAC_REG(port, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) v = skge_read16(hw, SK_XMAC_REG(port, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return skge_read16(hw, SK_XMAC_REG(port,reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) skge_write16(hw, SK_XMAC_REG(port,r), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) const u8 *hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) const u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define SK_GMAC_REG(port,reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return skge_read16(hw, SK_GMAC_REG(port,reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) skge_write16(hw, SK_GMAC_REG(port,r), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) const u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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