^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * New driver for Marvell Yukon chipset and SysKonnect Gigabit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ethernet adapters. Based on earlier sk98lin, e100 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * FreeBSD if_sk drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver intentionally does not support all the features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * of the original driver such as link fail-over and link management because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * those should be done at higher levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "skge.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRV_NAME "skge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRV_VERSION "1.14"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DEFAULT_TX_RING_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEFAULT_RX_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX_TX_RING_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_RX_RING_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RX_COPY_THRESHOLD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RX_BUF_SIZE 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_RETRIES 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ETH_JUMBO_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TX_WATCHDOG (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NAPI_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BLINK_MS 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LINK_HZ HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SKGE_EEPROM_MAGIC 0x9933aabb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NETIF_MSG_LINK | NETIF_MSG_IFUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) NETIF_MSG_IFDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int debug = -1; /* defaults above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct pci_device_id skge_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_SKGE_GENESIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_DEVICE_TABLE(pci, skge_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int skge_up(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int skge_down(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void skge_phy_reset(struct skge_port *skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void skge_tx_clean(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void genesis_get_stats(struct skge_port *skge, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void yukon_get_stats(struct skge_port *skge, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void yukon_init(struct skge_hw *hw, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void genesis_mac_init(struct skge_hw *hw, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void genesis_link_up(struct skge_port *skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void skge_set_multicast(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static irqreturn_t skge_intr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Avoid conditionals by using array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const int txqaddr[] = { Q_XA1, Q_XA2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const int rxqaddr[] = { Q_R1, Q_R2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline bool is_genesis(const struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_SKGE_GENESIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return hw->chip_id == CHIP_ID_GENESIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int skge_get_regs_len(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Returns copy of whole control register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Note: skip RAM address register because accessing it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * cause bus hangs!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const void __iomem *io = skge->hw->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regs->version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) memset(p, 0, regs->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) memcpy_fromio(p, io, B3_RAM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (regs->len > B3_RI_WTO_R1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regs->len - B3_RI_WTO_R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Wake on Lan only supported on Yukon chips with rev 1 or above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static u32 wol_supported(const struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return WAKE_MAGIC | WAKE_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void skge_wol_init(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) skge_write16(hw, B0_CTST, CS_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Turn on Vaux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) skge_write8(hw, B0_POWER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* WA code for COMA mode -- clear PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (hw->chip_id == CHIP_ID_YUKON_LITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 reg = skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg |= GP_DIR_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg &= ~GP_IO_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) skge_write32(hw, B2_GP_IO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) skge_write32(hw, SK_REG(port, GPHY_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GPC_DIS_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GPC_ANEG_1 | GPC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) skge_write32(hw, SK_REG(port, GPHY_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GPC_DIS_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GPC_ANEG_1 | GPC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Force to 10/100 skge_reset will re-enable on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (PHY_AN_100FULL | PHY_AN_100HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* no 1000 HD/FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gm_phy_write(hw, port, PHY_MARV_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PHY_CT_RE_CFG | PHY_CT_DUP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Set GMAC to no flow control and auto update for speed/duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) gma_write16(hw, port, GM_GP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Set WOL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) skge->netdev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Turn on appropriate WOL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (skge->wol & WAKE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (skge->wol & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* block receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wol->supported = wol_supported(skge->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wol->wolopts = skge->wol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if ((wol->wolopts & ~wol_supported(hw)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) !device_can_wakeup(&hw->pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) skge->wol = wol->wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Determine supported/advertised modes based on hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u32 skge_supported_modes(const struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (hw->copper) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) supported = (SUPPORTED_10baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SUPPORTED_10baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SUPPORTED_100baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SUPPORTED_100baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SUPPORTED_1000baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SUPPORTED_1000baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SUPPORTED_Autoneg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SUPPORTED_TP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) supported &= ~(SUPPORTED_10baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SUPPORTED_10baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SUPPORTED_100baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SUPPORTED_100baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else if (hw->chip_id == CHIP_ID_YUKON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) supported &= ~SUPPORTED_1000baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) supported = (SUPPORTED_1000baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SUPPORTED_1000baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SUPPORTED_FIBRE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SUPPORTED_Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int skge_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 supported, advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) supported = skge_supported_modes(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (hw->copper) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmd->base.port = PORT_TP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cmd->base.phy_address = hw->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cmd->base.port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) advertising = skge->advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) cmd->base.autoneg = skge->autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cmd->base.speed = skge->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cmd->base.duplex = skge->duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int skge_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 supported = skge_supported_modes(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ethtool_convert_link_mode_to_legacy_u32(&advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cmd->link_modes.advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (cmd->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) advertising = supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) skge->duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) skge->speed = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 speed = cmd->base.speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (cmd->base.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) setting = SUPPORTED_1000baseT_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else if (cmd->base.duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) setting = SUPPORTED_1000baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (cmd->base.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) setting = SUPPORTED_100baseT_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else if (cmd->base.duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) setting = SUPPORTED_100baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (cmd->base.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) setting = SUPPORTED_10baseT_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else if (cmd->base.duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) setting = SUPPORTED_10baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if ((setting & supported) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) skge->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) skge->duplex = cmd->base.duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) skge->autoneg = cmd->base.autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) skge->advertising = advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) skge_down(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err = skge_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void skge_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) strlcpy(info->bus_info, pci_name(skge->hw->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct skge_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) char name[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u16 xmac_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u16 gma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) } skge_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int skge_get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (sset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ARRAY_SIZE(skge_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void skge_get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (is_genesis(skge->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) genesis_get_stats(skge, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) yukon_get_stats(skge, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Use hardware MIB variables for critical path statistics and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * transmit feedback not reported at interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Other errors are accounted for in interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct net_device_stats *skge_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u64 data[ARRAY_SIZE(skge_stats)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (is_genesis(skge->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) genesis_get_stats(skge, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) yukon_get_stats(skge, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev->stats.tx_bytes = data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev->stats.rx_bytes = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev->stats.tx_packets = data[2] + data[4] + data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev->stats.rx_packets = data[3] + data[5] + data[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev->stats.multicast = data[3] + data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->stats.collisions = data[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->stats.tx_aborted_errors = data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) switch (stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) memcpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) skge_stats[i].name, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void skge_get_ring_param(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct ethtool_ringparam *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) p->rx_max_pending = MAX_RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) p->tx_max_pending = MAX_TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) p->rx_pending = skge->rx_ring.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) p->tx_pending = skge->tx_ring.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int skge_set_ring_param(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ethtool_ringparam *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) skge->rx_ring.count = p->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) skge->tx_ring.count = p->tx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) skge_down(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = skge_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static u32 skge_get_msglevel(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct skge_port *skge = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return skge->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void skge_set_msglevel(struct net_device *netdev, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct skge_port *skge = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) skge->msg_enable = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int skge_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) skge_phy_reset(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void skge_get_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ethtool_pauseparam *ecmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) (skge->flow_control == FLOW_MODE_SYM_OR_REM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ecmd->tx_pause = (ecmd->rx_pause ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) (skge->flow_control == FLOW_MODE_LOC_SEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int skge_set_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct ethtool_pauseparam *ecmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct ethtool_pauseparam old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) skge_get_pauseparam(dev, &old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ecmd->autoneg != old.autoneg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ecmd->rx_pause && ecmd->tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) skge->flow_control = FLOW_MODE_SYMMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else if (ecmd->rx_pause && !ecmd->tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) skge->flow_control = FLOW_MODE_SYM_OR_REM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else if (!ecmd->rx_pause && ecmd->tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) skge->flow_control = FLOW_MODE_LOC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) skge->flow_control = FLOW_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) skge_down(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) err = skge_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Chip internal frequency for clock calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static inline u32 hwkhz(const struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return is_genesis(hw) ? 53125 : 78125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Chip HZ to microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return (ticks * 1000) / hwkhz(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Microseconds to chip HZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return hwkhz(hw) * usec / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int skge_get_coalesce(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct ethtool_coalesce *ecmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ecmd->rx_coalesce_usecs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ecmd->tx_coalesce_usecs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 msk = skge_read32(hw, B2_IRQM_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (msk & rxirqmask[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ecmd->rx_coalesce_usecs = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (msk & txirqmask[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ecmd->tx_coalesce_usecs = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Note: interrupt timer is per board, but can turn on/off per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int skge_set_coalesce(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct ethtool_coalesce *ecmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 msk = skge_read32(hw, B2_IRQM_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 delay = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ecmd->rx_coalesce_usecs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) msk &= ~rxirqmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else if (ecmd->rx_coalesce_usecs < 25 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ecmd->rx_coalesce_usecs > 33333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) msk |= rxirqmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) delay = ecmd->rx_coalesce_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ecmd->tx_coalesce_usecs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) msk &= ~txirqmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else if (ecmd->tx_coalesce_usecs < 25 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ecmd->tx_coalesce_usecs > 33333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) msk |= txirqmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) delay = min(delay, ecmd->rx_coalesce_usecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) skge_write32(hw, B2_IRQM_MSK, msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (msk == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) skge_write32(hw, B2_IRQM_CTRL, TIM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void skge_led(struct skge_port *skge, enum led_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (is_genesis(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case LED_MODE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (hw->phy_type == SK_PHY_BCOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case LED_MODE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case LED_MODE_TST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (hw->phy_type == SK_PHY_BCOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case LED_MODE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) gm_phy_write(hw, port, PHY_MARV_LED_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PHY_M_LED_MO_DUP(MO_LED_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PHY_M_LED_MO_10(MO_LED_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PHY_M_LED_MO_100(MO_LED_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PHY_M_LED_MO_1000(MO_LED_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PHY_M_LED_MO_RX(MO_LED_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case LED_MODE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PHY_M_LED_PULS_DUR(PULS_170MS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PHY_M_LED_BLINK_RT(BLINK_84MS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PHY_M_LEDC_TX_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PHY_M_LEDC_DP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) gm_phy_write(hw, port, PHY_MARV_LED_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PHY_M_LED_MO_RX(MO_LED_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) (skge->speed == SPEED_100 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PHY_M_LED_MO_100(MO_LED_ON) : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case LED_MODE_TST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) gm_phy_write(hw, port, PHY_MARV_LED_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PHY_M_LED_MO_DUP(MO_LED_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PHY_M_LED_MO_10(MO_LED_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PHY_M_LED_MO_100(MO_LED_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PHY_M_LED_MO_1000(MO_LED_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PHY_M_LED_MO_RX(MO_LED_ON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* blink LED's for finding board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int skge_set_phys_id(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) enum ethtool_phys_id_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case ETHTOOL_ID_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 2; /* cycle on/off twice per second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case ETHTOOL_ID_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) skge_led(skge, LED_MODE_TST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case ETHTOOL_ID_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) skge_led(skge, LED_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case ETHTOOL_ID_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* back to regular LED state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int skge_get_eeprom_len(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } while (!(offset & PCI_VPD_ADDR_F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) offset | PCI_VPD_ADDR_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } while (offset & PCI_VPD_ADDR_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct pci_dev *pdev = skge->hw->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int length = eeprom->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u16 offset = eeprom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) eeprom->magic = SKGE_EEPROM_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) while (length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 val = skge_vpd_read(pdev, cap, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int n = min_t(int, length, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) memcpy(data, &val, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) length -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) data += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) offset += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct pci_dev *pdev = skge->hw->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int length = eeprom->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u16 offset = eeprom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (eeprom->magic != SKGE_EEPROM_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) while (length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int n = min_t(int, length, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (n < sizeof(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) val = skge_vpd_read(pdev, cap, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) memcpy(&val, data, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) skge_vpd_write(pdev, cap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) length -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) data += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) offset += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct ethtool_ops skge_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .get_drvinfo = skge_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .get_regs_len = skge_get_regs_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .get_regs = skge_get_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .get_wol = skge_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .set_wol = skge_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .get_msglevel = skge_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .set_msglevel = skge_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .nway_reset = skge_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .get_eeprom_len = skge_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .get_eeprom = skge_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .set_eeprom = skge_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .get_ringparam = skge_get_ring_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .set_ringparam = skge_set_ring_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .get_pauseparam = skge_get_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .set_pauseparam = skge_set_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .get_coalesce = skge_get_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .set_coalesce = skge_set_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .get_strings = skge_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .set_phys_id = skge_set_phys_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .get_sset_count = skge_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .get_ethtool_stats = skge_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .get_link_ksettings = skge_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .set_link_ksettings = skge_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Allocate ring elements and chain them together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * One-to-one association of board descriptors with ring elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct skge_tx_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!ring->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) e->desc = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (i == ring->count - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) e->next = ring->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) d->next_offset = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) e->next = e + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) d->next_offset = base + (i+1) * sizeof(*d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ring->to_use = ring->to_clean = ring->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Allocate and setup a new buffer for receiving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct sk_buff *skb, unsigned int bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct skge_rx_desc *rd = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dma_addr_t map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (dma_mapping_error(&skge->hw->pdev->dev, map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) rd->dma_lo = lower_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) rd->dma_hi = upper_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) e->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) rd->csum1_start = ETH_HLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rd->csum2_start = ETH_HLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) rd->csum1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) rd->csum2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dma_unmap_addr_set(e, mapaddr, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dma_unmap_len_set(e, maplen, bufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Resume receiving using existing skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Note: DMA address is not changed by chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * MTU not changed while receiver active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct skge_rx_desc *rd = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rd->csum2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) rd->csum2_start = ETH_HLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Free all buffers in receive ring, assumes receiver stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void skge_rx_clean(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct skge_ring *ring = &skge->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) e = ring->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct skge_rx_desc *rd = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) rd->control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (e->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dma_unmap_single(&hw->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dma_unmap_len(e, maplen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_kfree_skb(e->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) e->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) } while ((e = e->next) != ring->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* Allocate buffers for receive ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * For receive: to_clean is next received frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int skge_rx_fill(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct skge_ring *ring = &skge->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) e = ring->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) skb_reserve(skb, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } while ((e = e->next) != ring->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ring->to_clean = ring->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const char *skge_pause(enum pause_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case FLOW_STAT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case FLOW_STAT_REM_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return "rx only";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case FLOW_STAT_LOC_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return "tx_only";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return "both";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return "indeterminated";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static void skge_link_up(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) netif_carrier_on(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) netif_wake_queue(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) netif_info(skge, link, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "Link is up at %d Mbps, %s duplex, flow control %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) skge->speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) skge->duplex == DUPLEX_FULL ? "full" : "half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) skge_pause(skge->flow_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void skge_link_down(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) netif_carrier_off(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) netif_stop_queue(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) netif_info(skge, link, skge->netdev, "Link is down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static void xm_link_down(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) skge_link_down(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *val = xm_read16(hw, port, XM_PHY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (hw->phy_type == SK_PHY_XMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) for (i = 0; i < PHY_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) *val = xm_read16(hw, port, XM_PHY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u16 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (__xm_phy_read(hw, port, reg, &v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) for (i = 0; i < PHY_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) xm_write16(hw, port, XM_PHY_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) for (i = 0; i < PHY_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static void genesis_init(struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* set blink source counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) skge_write8(hw, B2_BSC_CTRL, BSC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* configure mac arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* configure mac arbiter timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) skge_write8(hw, B3_MA_RCINI_RX1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) skge_write8(hw, B3_MA_RCINI_RX2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) skge_write8(hw, B3_MA_RCINI_TX1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) skge_write8(hw, B3_MA_RCINI_TX2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* configure packet arbiter timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static void genesis_reset(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static const u8 zero[8] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* reset the statistics module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* disable Broadcom PHY IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (hw->phy_type == SK_PHY_BCOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) xm_outhash(hw, port, XM_HSM, zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Flush TX and RX fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) reg = xm_read32(hw, port, XM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* Convert mode to MII values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const u16 phy_pause_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [FLOW_MODE_NONE] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* special defines for FIBER (88E1011S only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static const u16 fiber_pause_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Check status of Broadcom phy link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static void bcom_check_link(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* read twice because of latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) xm_phy_read(hw, port, PHY_BCOM_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) status = xm_phy_read(hw, port, PHY_BCOM_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if ((status & PHY_ST_LSYNC) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) xm_link_down(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u16 lpa, aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!(status & PHY_ST_AN_OVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (lpa & PHY_B_AN_RF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) netdev_notice(dev, "remote fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Check Duplex mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) switch (aux & PHY_B_AS_AN_RES_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case PHY_B_RES_1000FD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) skge->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case PHY_B_RES_1000HD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) skge->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) netdev_notice(dev, "duplex mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* We are using IEEE 802.3z/D5.0 Table 37-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) switch (aux & PHY_B_AS_PAUSE_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case PHY_B_AS_PAUSE_MSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) skge->flow_status = FLOW_STAT_SYMMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) case PHY_B_AS_PRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) skge->flow_status = FLOW_STAT_REM_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case PHY_B_AS_PRT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) skge->flow_status = FLOW_STAT_LOC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) skge->flow_status = FLOW_STAT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) skge->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (!netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) genesis_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * Phy on for 100 or 10Mbit operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static void bcom_phy_init(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) u16 id1, r, ext, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* magic workaround patterns for Broadcom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) } A1hack[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }, C0hack[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* read Id from external PHY (all have the same address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Optimize MDIO transfer by suppressing preamble. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) r = xm_read16(hw, port, XM_MMU_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) r |= XM_MMU_NO_PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) xm_write16(hw, port, XM_MMU_CMD, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) switch (id1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case PHY_BCOM_ID1_C0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * Workaround BCOM Errata for the C0 type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Write magic patterns to reserved registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) for (i = 0; i < ARRAY_SIZE(C0hack); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) xm_phy_write(hw, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) C0hack[i].reg, C0hack[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) case PHY_BCOM_ID1_A1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Workaround BCOM Errata for the A1 type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Write magic patterns to reserved registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) for (i = 0; i < ARRAY_SIZE(A1hack); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) xm_phy_write(hw, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) A1hack[i].reg, A1hack[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * Workaround BCOM Errata (#10523) for all BCom PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * Disable Power Management after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) r |= PHY_B_AC_DIS_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) xm_read16(hw, port, XM_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ext = PHY_B_PEC_EN_LTR; /* enable tx led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ctl = PHY_CT_SP1000; /* always 1000mbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * Workaround BCOM Errata #1 for the C5 type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * 1000Base-T Link Acquisition Failure in Slave Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u16 adv = PHY_B_1000C_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (skge->advertising & ADVERTISED_1000baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) adv |= PHY_B_1000C_AHD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (skge->advertising & ADVERTISED_1000baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) adv |= PHY_B_1000C_AFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (skge->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ctl |= PHY_CT_DUP_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* Force to slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* Set autonegotiation pause parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* Handle Jumbo frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (hw->dev[port]->mtu > ETH_DATA_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ext |= PHY_B_PEC_HIGH_LA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* Use link status change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static void xm_phy_init(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u16 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (skge->advertising & ADVERTISED_1000baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ctrl |= PHY_X_AN_HD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (skge->advertising & ADVERTISED_1000baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ctrl |= PHY_X_AN_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ctrl |= fiber_pause_map[skge->flow_control];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* Restart Auto-negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Set DuplexMode in Config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (skge->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ctrl |= PHY_CT_DUP_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Do NOT enable Auto-negotiation here. This would hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * the link down because no IDLEs are transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Poll PHY for status changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) mod_timer(&skge->link_timer, jiffies + LINK_HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int xm_check_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* read twice because of latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) xm_phy_read(hw, port, PHY_XMAC_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) status = xm_phy_read(hw, port, PHY_XMAC_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if ((status & PHY_ST_LSYNC) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) xm_link_down(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u16 lpa, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!(status & PHY_ST_AN_OVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (lpa & PHY_B_AN_RF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) netdev_notice(dev, "remote fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* Check Duplex mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case PHY_X_RS_FD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) skge->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case PHY_X_RS_HD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) skge->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) netdev_notice(dev, "duplex mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* We are using IEEE 802.3z/D5.0 Table 37-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) (lpa & PHY_X_P_SYM_MD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) skge->flow_status = FLOW_STAT_SYMMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* Enable PAUSE receive, disable PAUSE transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) skge->flow_status = FLOW_STAT_REM_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* Disable PAUSE receive, enable PAUSE transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) skge->flow_status = FLOW_STAT_LOC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) skge->flow_status = FLOW_STAT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) skge->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (!netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) genesis_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* Poll to check for link coming up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * Since internal PHY is wired to a level triggered pin, can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * get an interrupt when carrier is detected, need to poll for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * link coming up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static void xm_link_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct skge_port *skge = from_timer(skge, t, link_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct net_device *dev = skge->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) spin_lock_irqsave(&hw->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * Verify that the link by checking GPIO register three times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * This pin has the signal from the link_sync pin connected to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) goto link_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* Re-enable interrupt to detect link down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (xm_check_link(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) u16 msk = xm_read16(hw, port, XM_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) msk &= ~XM_IS_INP_ASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) xm_write16(hw, port, XM_IMSK, msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) xm_read16(hw, port, XM_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) link_down:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) mod_timer(&skge->link_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) round_jiffies(jiffies + LINK_HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) spin_unlock_irqrestore(&hw->phy_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static void genesis_mac_init(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static const u8 zero[6] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MFF_SET_MAC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) goto reset_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) netdev_warn(dev, "genesis reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) reset_ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* Unreset the XMAC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Perform additional initialization for external PHYs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * namely for the 1000baseTX cards that use the XMAC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * GMII mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (hw->phy_type != SK_PHY_XMAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* Take external Phy out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) r = skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) r |= GP_DIR_0|GP_IO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) r |= GP_DIR_2|GP_IO_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) skge_write32(hw, B2_GP_IO, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Enable GMII interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) switch (hw->phy_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) case SK_PHY_XMAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) xm_phy_init(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case SK_PHY_BCOM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) bcom_phy_init(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) bcom_check_link(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* Set Station Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) xm_outaddr(hw, port, XM_SA, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* We don't use match addresses so clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) for (i = 1; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) xm_outaddr(hw, port, XM_EXM(i), zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* Clear MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) xm_write16(hw, port, XM_STAT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) XM_SC_CLR_RXC | XM_SC_CLR_TXC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* Clear two times according to Errata #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) xm_write16(hw, port, XM_STAT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) XM_SC_CLR_RXC | XM_SC_CLR_TXC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* configure Rx High Water Mark (XM_RX_HI_WM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) xm_write16(hw, port, XM_RX_HI_WM, 1450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* We don't need the FCS appended to the packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (jumbo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) r |= XM_RX_BIG_PK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (skge->duplex == DUPLEX_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * If in manual half duplex mode the other side might be in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * full duplex mode, so ignore if a carrier extension is not seen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * on frames received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) r |= XM_RX_DIS_CEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) xm_write16(hw, port, XM_RX_CMD, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* We want short frames padded to 60 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* Increase threshold for jumbo frames on dual port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (hw->ports > 1 && jumbo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) xm_write16(hw, port, XM_TX_THR, 1020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) xm_write16(hw, port, XM_TX_THR, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * Enable the reception of all error frames. This is is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * a necessary evil due to the design of the XMAC. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * XMAC's receive FIFO is only 8K in size, however jumbo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * frames can be up to 9000 bytes in length. When bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * frame filtering is enabled, the XMAC's RX FIFO operates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * in 'store and forward' mode. For this to work, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * entire frame has to fit into the FIFO, but that means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * that jumbo frames larger than 8192 bytes will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * truncated. Disabling all bad frame filtering causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * the RX FIFO to operate in streaming mode, in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * case the XMAC will start transferring frames out of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * RX FIFO as soon as the FIFO threshold is reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * - Enable all bits excepting 'Octets Rx OK Low CntOv'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * and 'Octets Rx OK Hi Cnt Ov'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * - Enable all bits excepting 'Octets Tx OK Low CntOv'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * and 'Octets Tx OK Hi Cnt Ov'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Configure MAC arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* configure timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) skge_write8(hw, B3_MA_TOINI_RX1, 72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) skge_write8(hw, B3_MA_TOINI_RX2, 72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) skge_write8(hw, B3_MA_TOINI_TX1, 72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) skge_write8(hw, B3_MA_TOINI_TX2, 72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) skge_write8(hw, B3_MA_RCINI_RX1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) skge_write8(hw, B3_MA_RCINI_RX2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) skge_write8(hw, B3_MA_RCINI_TX1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) skge_write8(hw, B3_MA_RCINI_TX2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* Configure Rx MAC FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* Configure Tx MAC FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (jumbo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* Enable frame flushing if jumbo frames used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* enable timeout timers if normal frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) skge_write16(hw, B3_PA_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static void genesis_stop(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) unsigned retries = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Disable Tx and Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) cmd = xm_read16(hw, port, XM_MMU_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) xm_write16(hw, port, XM_MMU_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) genesis_reset(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* Clear Tx packet arbiter timeout IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) skge_write16(hw, B3_PA_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* Reset the MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) } while (--retries > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* For external PHYs there must be special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (hw->phy_type != SK_PHY_XMAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) u32 reg = skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (port == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) reg |= GP_DIR_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) reg &= ~GP_IO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) reg |= GP_DIR_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) reg &= ~GP_IO_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) skge_write32(hw, B2_GP_IO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) xm_write16(hw, port, XM_MMU_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) xm_read16(hw, port, XM_MMU_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) xm_read16(hw, port, XM_MMU_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static void genesis_get_stats(struct skge_port *skge, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) unsigned long timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) xm_write16(hw, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* wait for update to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) while (xm_read16(hw, port, XM_STAT_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* special case for 64 bit octet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) | xm_read32(hw, port, XM_TXO_OK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) | xm_read32(hw, port, XM_RXO_OK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static void genesis_mac_intr(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u16 status = xm_read16(hw, port, XM_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) "mac interrupt status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) xm_link_down(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) mod_timer(&skge->link_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (status & XM_IS_TXF_UR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) xm_write32(hw, port, XM_MODE, XM_MD_FTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ++dev->stats.tx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static void genesis_link_up(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) u16 cmd, msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) cmd = xm_read16(hw, port, XM_MMU_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * enabling pause frame reception is required for 1000BT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * because the XMAC is not reset if the link is going down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (skge->flow_status == FLOW_STAT_NONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) skge->flow_status == FLOW_STAT_LOC_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* Disable Pause Frame Reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) cmd |= XM_MMU_IGN_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* Enable Pause Frame Reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) cmd &= ~XM_MMU_IGN_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) xm_write16(hw, port, XM_MMU_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) mode = xm_read32(hw, port, XM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) skge->flow_status == FLOW_STAT_LOC_SEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * Configure Pause Frame Generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * Use internal and external Pause Frame Generation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * Sending pause frames is edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * Send a Pause frame with the maximum pause time if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * internal oder external FIFO full condition occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * Send a zero pause time frame to re-start transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* XM_PAUSE_DA = '010000C28001' (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* XM_MAC_PTIME = 0xffff (maximum) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* remember this value is defined in big endian (!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) mode |= XM_PAUSE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * disable pause frame generation is required for 1000BT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * because the XMAC is not reset if the link is going down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* Disable Pause Mode in Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) mode &= ~XM_PAUSE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) xm_write32(hw, port, XM_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* Turn on detection of Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) msk = xm_read16(hw, port, XM_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) msk &= ~XM_IS_TXF_UR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) xm_write16(hw, port, XM_IMSK, msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) xm_read16(hw, port, XM_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* get MMU Command Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) cmd = xm_read16(hw, port, XM_MMU_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) cmd |= XM_MMU_GMII_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * Workaround BCOM Errata (#10523) for all BCom Phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * Enable Power Management after link up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (hw->phy_type == SK_PHY_BCOM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) & ~PHY_B_AC_DIS_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* enable Rx/Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) xm_write16(hw, port, XM_MMU_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) skge_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static inline void bcom_phy_intr(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) u16 isrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "phy interrupt status 0x%x\n", isrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (isrc & PHY_B_IS_PSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) pr_err("%s: uncorrectable pair swap error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) hw->dev[port]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* Workaround BCom Errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * enable and disable loopback mode if "NO HCD" occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (isrc & PHY_B_IS_NO_HDCL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) xm_phy_write(hw, port, PHY_BCOM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ctrl | PHY_CT_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) xm_phy_write(hw, port, PHY_BCOM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ctrl & ~PHY_CT_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) bcom_check_link(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) gma_write16(hw, port, GM_SMI_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) gma_write16(hw, port, GM_SMI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) for (i = 0; i < PHY_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) gma_write16(hw, port, GM_SMI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) GM_SMI_CT_PHY_AD(hw->phy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) for (i = 0; i < PHY_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) goto ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) *val = gma_read16(hw, port, GM_SMI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) u16 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (__gm_phy_read(hw, port, reg, &v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Marvell Phy Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static void yukon_init(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct skge_port *skge = netdev_priv(hw->dev[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) u16 ctrl, ct1000, adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) PHY_M_EC_MAC_S_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (skge->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ctrl &= ~PHY_CT_ANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ctrl |= PHY_CT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ct1000 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) adv = PHY_AN_CSMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (skge->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (hw->copper) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (skge->advertising & ADVERTISED_1000baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ct1000 |= PHY_M_1000C_AFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (skge->advertising & ADVERTISED_1000baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ct1000 |= PHY_M_1000C_AHD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (skge->advertising & ADVERTISED_100baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) adv |= PHY_M_AN_100_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (skge->advertising & ADVERTISED_100baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) adv |= PHY_M_AN_100_HD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (skge->advertising & ADVERTISED_10baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) adv |= PHY_M_AN_10_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (skge->advertising & ADVERTISED_10baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) adv |= PHY_M_AN_10_HD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* Set Flow-control capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) adv |= phy_pause_map[skge->flow_control];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (skge->advertising & ADVERTISED_1000baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) adv |= PHY_M_AN_1000X_AFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (skge->advertising & ADVERTISED_1000baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) adv |= PHY_M_AN_1000X_AHD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) adv |= fiber_pause_map[skge->flow_control];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* Restart Auto-negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* forced speed/duplex settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ct1000 = PHY_M_1000C_MSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (skge->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ctrl |= PHY_CT_DUP_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) switch (skge->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ctrl |= PHY_CT_SP1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ctrl |= PHY_CT_SP100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ctrl |= PHY_CT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* Enable phy interrupt on autonegotiation complete (or link up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (skge->autoneg == AUTONEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static void yukon_reset(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) gma_write16(hw, port, GM_MC_ADDR_H2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) gma_write16(hw, port, GM_MC_ADDR_H3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) gma_write16(hw, port, GM_MC_ADDR_H4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) gma_write16(hw, port, GM_RX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) gma_read16(hw, port, GM_RX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static int is_yukon_lite_a0(struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (hw->chip_id != CHIP_ID_YUKON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) reg = skge_read32(hw, B2_FAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) skge_write8(hw, B2_FAR + 3, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ret = (skge_read8(hw, B2_FAR + 3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) skge_write32(hw, B2_FAR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static void yukon_mac_init(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) struct skge_port *skge = netdev_priv(hw->dev[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) const u8 *addr = hw->dev[port]->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* WA code for COMA mode -- set PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (hw->chip_id == CHIP_ID_YUKON_LITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) reg = skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) reg |= GP_DIR_9 | GP_IO_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) skge_write32(hw, B2_GP_IO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* hard reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /* WA code for COMA mode -- clear PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (hw->chip_id == CHIP_ID_YUKON_LITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) reg = skge_read32(hw, B2_GP_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) reg |= GP_DIR_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) reg &= ~GP_IO_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) skge_write32(hw, B2_GP_IO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* Set hardware config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* Clear GMC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (skge->autoneg == AUTONEG_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) reg = GM_GPCR_AU_ALL_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) gma_write16(hw, port, GM_GP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) gma_read16(hw, port, GM_GP_CTRL) | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) switch (skge->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) reg &= ~GM_GPCR_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) reg |= GM_GPCR_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) reg &= ~GM_GPCR_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) reg |= GM_GPCR_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (skge->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) reg |= GM_GPCR_DUP_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) switch (skge->flow_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) case FLOW_MODE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) case FLOW_MODE_LOC_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* disable Rx flow-control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) case FLOW_MODE_SYMMETRIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) case FLOW_MODE_SYM_OR_REM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* enable Tx & Rx flow-control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) gma_write16(hw, port, GM_GP_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) yukon_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /* MIB clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) reg = gma_read16(hw, port, GM_PHY_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) for (i = 0; i < GM_MIB_CNT_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) gma_write16(hw, port, GM_PHY_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* transmit control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* receive control reg: unicast + multicast + no FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) gma_write16(hw, port, GM_RX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) /* transmit flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* transmit parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) gma_write16(hw, port, GM_TX_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* configure the Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) | GM_SMOD_VLAN_ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) | IPG_DATA_VAL(IPG_DATA_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (hw->dev[port]->mtu > ETH_DATA_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) reg |= GM_SMOD_JUMBO_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) gma_write16(hw, port, GM_SERIAL_MODE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* physical address: used for pause frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* virtual address for data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* enable interrupt mask for counter overflows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* Initialize Mac Fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* Configure Rx MAC FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (is_yukon_lite_a0(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) reg &= ~GMF_RX_F_FL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) * because Pause Packet Truncation in GMAC is not working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) * we have to increase the Flush Threshold to 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * in order to flush pause packets in Rx FIFO on Yukon-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /* Configure Tx MAC FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) /* Go into power down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static void yukon_suspend(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ctrl |= PHY_M_PC_POL_R_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ctrl |= PHY_CT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) /* switch IEEE compatible power down mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ctrl |= PHY_CT_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static void yukon_stop(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) yukon_reset(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) gma_write16(hw, port, GM_GP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) gma_read16(hw, port, GM_GP_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) gma_read16(hw, port, GM_GP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) yukon_suspend(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* set GPHY Control reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static void yukon_get_stats(struct skge_port *skge, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) | gma_read32(hw, port, GM_TXO_OK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) | gma_read32(hw, port, GM_RXO_OK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) data[i] = gma_read32(hw, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) skge_stats[i].gma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static void yukon_mac_intr(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "mac interrupt status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (status & GM_IS_RX_FF_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ++dev->stats.rx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (status & GM_IS_TX_FF_UR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ++dev->stats.tx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) switch (aux & PHY_M_PS_SPEED_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) case PHY_M_PS_SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) case PHY_M_PS_SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) return SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) return SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static void yukon_link_up(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) /* Enable Transmit FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) reg = gma_read16(hw, port, GM_GP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) reg |= GM_GPCR_DUP_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) /* enable Rx/Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) gma_write16(hw, port, GM_GP_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) skge_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static void yukon_link_down(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ctrl = gma_read16(hw, port, GM_GP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) gma_write16(hw, port, GM_GP_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (skge->flow_status == FLOW_STAT_REM_SEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ctrl |= PHY_M_AN_ASP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /* restore Asymmetric Pause bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) skge_link_down(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) yukon_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static void yukon_phy_intr(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) const char *reason = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) u16 istatus, phystat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (istatus & PHY_M_IS_AN_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) & PHY_M_AN_RF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) reason = "remote fault";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) reason = "master/slave fault";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (!(phystat & PHY_M_PS_SPDUP_RES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) reason = "speed/duplex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) ? DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) skge->speed = yukon_speed(hw, phystat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* We are using IEEE 802.3z/D5.0 Table 37-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) switch (phystat & PHY_M_PS_PAUSE_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) case PHY_M_PS_PAUSE_MSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) skge->flow_status = FLOW_STAT_SYMMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) case PHY_M_PS_RX_P_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) skge->flow_status = FLOW_STAT_REM_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) case PHY_M_PS_TX_P_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) skge->flow_status = FLOW_STAT_LOC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) skge->flow_status = FLOW_STAT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (skge->flow_status == FLOW_STAT_NONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) yukon_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (istatus & PHY_M_IS_LSP_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) skge->speed = yukon_speed(hw, phystat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (istatus & PHY_M_IS_DUP_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (istatus & PHY_M_IS_LST_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (phystat & PHY_M_PS_LINK_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) yukon_link_up(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) yukon_link_down(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* XXX restart autonegotiation? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) static void skge_phy_reset(struct skge_port *skge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) netif_stop_queue(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) netif_carrier_off(skge->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (is_genesis(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) genesis_reset(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) genesis_mac_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) yukon_reset(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) yukon_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) skge_set_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /* Basic MII support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) struct mii_ioctl_data *data = if_mii(ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) int err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) return -ENODEV; /* Phy still in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) case SIOCGMIIPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) data->phy_id = hw->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) case SIOCGMIIREG: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) data->val_out = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) case SIOCSMIIREG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) data->val_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) data->val_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) start /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) len /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) end = start + len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) skge_write32(hw, RB_ADDR(q, RB_START), start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) skge_write32(hw, RB_ADDR(q, RB_WP), start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) skge_write32(hw, RB_ADDR(q, RB_RP), start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) skge_write32(hw, RB_ADDR(q, RB_END), end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (q == Q_R1 || q == Q_R2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /* Set thresholds on receive queue's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) start + (2*len)/3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) start + (len/3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* Enable store & forward on Tx queue's because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) * Tx FIFO is only 4K on Genesis and 1K on Yukon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /* Setup Bus Memory Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static void skge_qset(struct skge_port *skge, u16 q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) const struct skge_element *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) u32 watermark = 0x600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) u64 base = skge->dma + (e->desc - skge->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) /* optimization to reduce window on 32bit/33mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) watermark /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) skge_write32(hw, Q_ADDR(q, Q_F), watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) static int skge_up(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) u32 chunk, ram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) size_t rx_size, tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) if (!is_valid_ether_addr(dev->dev_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) netif_info(skge, ifup, skge->netdev, "enabling interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (dev->mtu > RX_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) skge->rx_buf_size = dev->mtu + ETH_HLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) skge->rx_buf_size = RX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) skge->mem_size = tx_size + rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) &skge->dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (!skge->mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) BUG_ON(skge->dma & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) goto free_pci_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) goto free_pci_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) err = skge_rx_fill(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) goto free_rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) skge->dma + rx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) goto free_rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (hw->ports == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) dev->name, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) hw->pdev->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) goto free_tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* Initialize MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) genesis_mac_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) yukon_mac_init(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* Configure RAMbuffers - equally between ports and tx/rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ram_addr = hw->ram_offset + 2 * chunk * port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /* Start receiver BMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) skge_led(skge, LED_MODE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) spin_lock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) hw->intr_mask |= portmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) skge_write32(hw, B0_IMSK, hw->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) spin_unlock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) napi_enable(&skge->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) skge_set_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) free_tx_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) kfree(skge->tx_ring.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) free_rx_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) skge_rx_clean(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) kfree(skge->rx_ring.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) free_pci_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) skge->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) skge->mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* stop receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static void skge_rx_stop(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) RB_RST_SET|RB_DIS_OP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static int skge_down(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (!skge->mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) netif_tx_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) del_timer_sync(&skge->link_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) napi_disable(&skge->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) spin_lock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) hw->intr_mask &= ~portmask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) spin_unlock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (hw->ports == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) free_irq(hw->pdev->irq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) genesis_stop(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) yukon_stop(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* Stop transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) RB_RST_SET|RB_DIS_OP_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) /* Disable Force Sync bit and Enable Alloc bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) skge_write8(hw, SK_REG(port, TXA_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /* Stop Interval Timer and Limit Counter of Tx Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* Reset PCI FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* Reset the RAM Buffer async Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) skge_rx_stop(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (is_genesis(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) skge_led(skge, LED_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) netif_tx_lock_bh(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) skge_tx_clean(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) netif_tx_unlock_bh(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) skge_rx_clean(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) kfree(skge->rx_ring.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) kfree(skge->tx_ring.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) skge->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) skge->mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) static inline int skge_avail(const struct skge_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) + (ring->to_clean - ring->to_use) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct skge_tx_desc *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) u32 control, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) dma_addr_t map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) if (skb_padto(skb, ETH_ZLEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) e = skge->tx_ring.to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) td = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) BUG_ON(td->control & BMU_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) e->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) len = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (dma_mapping_error(&hw->pdev->dev, map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) goto mapping_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) dma_unmap_addr_set(e, mapaddr, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) dma_unmap_len_set(e, maplen, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) td->dma_lo = lower_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) td->dma_hi = upper_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) const int offset = skb_checksum_start_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) /* This seems backwards, but it is what the sk98lin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) * does. Looks like hardware is wrong?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) control = BMU_TCP_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) control = BMU_UDP_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) td->csum_offs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) td->csum_start = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) td->csum_write = offset + skb->csum_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) control = BMU_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) control |= BMU_EOF | BMU_IRQ_EOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) struct skge_tx_desc *tf = td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) control |= BMU_STFWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) skb_frag_size(frag), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) if (dma_mapping_error(&hw->pdev->dev, map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) goto mapping_unwind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) e = e->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) e->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) tf = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) BUG_ON(tf->control & BMU_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) tf->dma_lo = lower_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) tf->dma_hi = upper_32_bits(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) dma_unmap_addr_set(e, mapaddr, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) dma_unmap_len_set(e, maplen, skb_frag_size(frag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) tf->control |= BMU_EOF | BMU_IRQ_EOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* Make sure all the descriptors written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) netdev_sent_queue(dev, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) "tx queued, slot %td, len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) e - skge->tx_ring.start, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) skge->tx_ring.to_use = e->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) netdev_dbg(dev, "transmit queue full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) mapping_unwind:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) e = skge->tx_ring.to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) dma_unmap_len(e, maplen), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) while (i-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) e = e->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) dma_unmap_len(e, maplen), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) mapping_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) /* Free resources associated with this reing element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) u32 control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* skb header vs. fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (control & BMU_STF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) dma_unmap_len(e, maplen), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) dma_unmap_len(e, maplen), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) /* Free all buffers in transmit ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static void skge_tx_clean(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) struct skge_tx_desc *td = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) skge_tx_unmap(skge->hw->pdev, e, td->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) if (td->control & BMU_EOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) dev_kfree_skb(e->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) td->control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) netdev_reset_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) skge->tx_ring.to_clean = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) skge_tx_clean(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static int skge_change_mtu(struct net_device *dev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) if (!netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) skge_down(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) err = skge_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) dev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static void genesis_add_filter(u8 filter[8], const u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) u32 crc, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) crc = ether_crc_le(ETH_ALEN, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) bit = ~crc & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) filter[bit/8] |= 1 << (bit%8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static void genesis_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) u8 filter[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) mode = xm_read32(hw, port, XM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) mode |= XM_MD_ENA_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) if (dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) mode |= XM_MD_ENA_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) mode &= ~XM_MD_ENA_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) if (dev->flags & IFF_ALLMULTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) memset(filter, 0xff, sizeof(filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) memset(filter, 0, sizeof(filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (skge->flow_status == FLOW_STAT_REM_SEND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) skge->flow_status == FLOW_STAT_SYMMETRIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) genesis_add_filter(filter, pause_mc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) netdev_for_each_mc_addr(ha, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) genesis_add_filter(filter, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) xm_write32(hw, port, XM_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) xm_outhash(hw, port, XM_HSM, filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) static void yukon_add_filter(u8 filter[8], const u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) filter[bit/8] |= 1 << (bit%8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) static void yukon_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) int port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) skge->flow_status == FLOW_STAT_SYMMETRIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) u8 filter[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) memset(filter, 0, sizeof(filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) reg = gma_read16(hw, port, GM_RX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) reg |= GM_RXCR_UCF_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) if (dev->flags & IFF_PROMISC) /* promiscuous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) else if (dev->flags & IFF_ALLMULTI) /* all multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) memset(filter, 0xff, sizeof(filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) reg &= ~GM_RXCR_MCF_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) reg |= GM_RXCR_MCF_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) if (rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) yukon_add_filter(filter, pause_mc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) netdev_for_each_mc_addr(ha, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) yukon_add_filter(filter, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) gma_write16(hw, port, GM_MC_ADDR_H1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) (u16)filter[0] | ((u16)filter[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) gma_write16(hw, port, GM_MC_ADDR_H2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) (u16)filter[2] | ((u16)filter[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) gma_write16(hw, port, GM_MC_ADDR_H3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) (u16)filter[4] | ((u16)filter[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) gma_write16(hw, port, GM_MC_ADDR_H4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) (u16)filter[6] | ((u16)filter[7] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) gma_write16(hw, port, GM_RX_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) static inline u16 phy_length(const struct skge_hw *hw, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) return status >> XMR_FS_LEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) return status >> GMR_FS_LEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) return (status & GMR_FS_ANY_ERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) (status & GMR_FS_RX_OK) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) static void skge_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) if (is_genesis(skge->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) genesis_set_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) yukon_set_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) /* Get receive buffer from descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) * Handles copy of small buffers and reallocation failures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) static struct sk_buff *skge_rx_get(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) struct skge_element *e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) u32 control, u32 status, u16 csum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) u16 len = control & BMU_BBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) "rx slot %td status 0x%x len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) e - skge->rx_ring.start, status, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) if (len > skge->rx_buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) if (bad_phy_status(skge->hw, status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) if (phy_length(skge->hw, status) != len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) if (len < RX_COPY_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) skb = netdev_alloc_skb_ip_align(dev, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) goto resubmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) dma_sync_single_for_cpu(&skge->hw->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) dma_unmap_len(e, maplen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) skb_copy_from_linear_data(e->skb, skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) dma_sync_single_for_device(&skge->hw->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) dma_unmap_addr(e, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) dma_unmap_len(e, maplen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) skge_rx_reuse(e, skge->rx_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) struct skge_element ee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) struct sk_buff *nskb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) if (!nskb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) goto resubmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) ee = *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) skb = ee.skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) prefetch(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) dev_kfree_skb(nskb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) goto resubmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) dma_unmap_single(&skge->hw->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) dma_unmap_addr(&ee, mapaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (dev->features & NETIF_F_RXCSUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) skb->csum = le16_to_cpu(csum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) "rx err, slot %td control 0x%x status 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) e - skge->rx_ring.start, control, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (is_genesis(skge->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (status & XMR_FS_FRA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (status & XMR_FS_FCS_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (status & GMR_FS_FRAGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (status & GMR_FS_CRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) resubmit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) skge_rx_reuse(e, skge->rx_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* Free all buffers in Tx ring which are no longer owned by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static void skge_tx_done(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) struct skge_ring *ring = &skge->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) unsigned int bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) for (e = ring->to_clean; e != ring->to_use; e = e->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) u32 control = ((const struct skge_tx_desc *) e->desc)->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (control & BMU_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) skge_tx_unmap(skge->hw->pdev, e, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) if (control & BMU_EOF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) "tx done slot %td\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) e - skge->tx_ring.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) bytes_compl += e->skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) dev_consume_skb_any(e->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) netdev_completed_queue(dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) skge->tx_ring.to_clean = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) /* Can run lockless until we need to synchronize to restart queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) if (unlikely(netif_queue_stopped(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) netif_tx_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (unlikely(netif_queue_stopped(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) netif_tx_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) static int skge_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) struct skge_port *skge = container_of(napi, struct skge_port, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) struct net_device *dev = skge->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) struct skge_ring *ring = &skge->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) skge_tx_done(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) struct skge_rx_desc *rd = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) control = rd->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) if (control & BMU_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) if (likely(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) ++work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) ring->to_clean = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /* restart receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) if (work_done < budget && napi_complete_done(napi, work_done)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) spin_lock_irqsave(&hw->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) hw->intr_mask |= napimask[skge->port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) skge_write32(hw, B0_IMSK, hw->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) spin_unlock_irqrestore(&hw->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* Parity errors seem to happen when Genesis is connected to a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) * with no other ports present. Heartbeat error??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) static void skge_mac_parity(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) ++dev->stats.tx_heartbeat_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) MFF_CLR_PERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static void skge_mac_intr(struct skge_hw *hw, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) genesis_mac_intr(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) yukon_mac_intr(hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) /* Handle device specific framing and timeout interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) static void skge_error_irq(struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) struct pci_dev *pdev = hw->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) if (is_genesis(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /* clear xmac errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) /* Timestamp (unused) overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (hwstatus & IS_IRQ_TIST_OV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) if (hwstatus & IS_RAM_RD_PAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) dev_err(&pdev->dev, "Ram read data parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) if (hwstatus & IS_RAM_WR_PAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dev_err(&pdev->dev, "Ram write data parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) if (hwstatus & IS_M1_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) skge_mac_parity(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) if (hwstatus & IS_M2_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) skge_mac_parity(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if (hwstatus & IS_R1_PAR_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) dev_err(&pdev->dev, "%s: receive queue parity error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) hw->dev[0]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) if (hwstatus & IS_R2_PAR_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) dev_err(&pdev->dev, "%s: receive queue parity error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) hw->dev[1]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) u16 pci_status, pci_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) pci_read_config_word(pdev, PCI_STATUS, &pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) pci_cmd, pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) /* Write the error bits back to clear them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) pci_status &= PCI_STATUS_ERROR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) pci_write_config_word(pdev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) pci_write_config_word(pdev, PCI_STATUS, pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /* if error still set then just ignore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) hwstatus = skge_read32(hw, B0_HWE_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) if (hwstatus & IS_IRQ_STAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) hw->intr_mask &= ~IS_HW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) * Interrupt from PHY are handled in tasklet (softirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) * because accessing phy registers requires spin wait which might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) * cause excess interrupt latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) static void skge_extirq(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) struct skge_hw *hw = from_tasklet(hw, t, phy_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) for (port = 0; port < hw->ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) struct net_device *dev = hw->dev[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) spin_lock(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (!is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) yukon_phy_intr(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) else if (hw->phy_type == SK_PHY_BCOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) bcom_phy_intr(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) spin_unlock(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) spin_lock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) hw->intr_mask |= IS_EXT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) skge_write32(hw, B0_IMSK, hw->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) spin_unlock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) static irqreturn_t skge_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) struct skge_hw *hw = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) spin_lock(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) /* Reading this register masks IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) status = skge_read32(hw, B0_SP_ISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) if (status == 0 || status == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) status &= hw->intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) if (status & IS_EXT_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) hw->intr_mask &= ~IS_EXT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) tasklet_schedule(&hw->phy_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (status & (IS_XA1_F|IS_R1_F)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) struct skge_port *skge = netdev_priv(hw->dev[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) napi_schedule(&skge->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if (status & IS_PA_TO_TX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) if (status & IS_PA_TO_RX1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) ++hw->dev[0]->stats.rx_over_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) if (status & IS_MAC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) skge_mac_intr(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) if (hw->dev[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) struct skge_port *skge = netdev_priv(hw->dev[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) if (status & (IS_XA2_F|IS_R2_F)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) napi_schedule(&skge->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) if (status & IS_PA_TO_RX2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) ++hw->dev[1]->stats.rx_over_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) if (status & IS_PA_TO_TX2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) if (status & IS_MAC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) skge_mac_intr(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) if (status & IS_HW_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) skge_error_irq(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) skge_write32(hw, B0_IMSK, hw->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) spin_unlock(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) static void skge_netpoll(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) skge_intr(dev->irq, skge->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) static int skge_set_mac_address(struct net_device *dev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) unsigned port = skge->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) const struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) if (!is_valid_ether_addr(addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) if (!netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) /* disable Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) spin_lock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) ctrl = gma_read16(hw, port, GM_GP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) xm_outaddr(hw, port, XM_SA, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) gma_write16(hw, port, GM_GP_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) spin_unlock_bh(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) } skge_chips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) { CHIP_ID_GENESIS, "Genesis" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) { CHIP_ID_YUKON, "Yukon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) { CHIP_ID_YUKON_LP, "Yukon-LP"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) static const char *skge_board_name(const struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) static char buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) if (skge_chips[i].id == hw->chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) return skge_chips[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) * Setup the board data structure, but don't bring up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) * the port(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) static int skge_reset(struct skge_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) u16 ctst, pci_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) u8 t8, mac_cfg, pmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) ctst = skge_read16(hw, B0_CTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /* do a SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) skge_write8(hw, B0_CTST, CS_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) skge_write8(hw, B0_CTST, CS_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) /* clear PCI errors, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) skge_write8(hw, B2_TST_CTRL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) pci_write_config_word(hw->pdev, PCI_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) pci_status | PCI_STATUS_ERROR_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) skge_write8(hw, B0_CTST, CS_MRST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /* restore CLK_RUN bits (for Yukon-Lite) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) skge_write16(hw, B0_CTST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) hw->chip_id = skge_read8(hw, B2_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) pmd_type = skge_read8(hw, B2_PMD_TYP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) hw->copper = (pmd_type == 'T' || pmd_type == '1');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) switch (hw->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) case CHIP_ID_GENESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) #ifdef CONFIG_SKGE_GENESIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) switch (hw->phy_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) case SK_PHY_XMAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) hw->phy_addr = PHY_ADDR_XMAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) case SK_PHY_BCOM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) hw->phy_addr = PHY_ADDR_BCOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) hw->phy_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) case CHIP_ID_YUKON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) case CHIP_ID_YUKON_LITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) case CHIP_ID_YUKON_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) hw->copper = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) hw->phy_addr = PHY_ADDR_MARV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) hw->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) mac_cfg = skge_read8(hw, B2_MAC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) /* read the adapters RAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) t8 = skge_read8(hw, B2_E_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) if (is_genesis(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) if (t8 == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) /* special case: 4 x 64k x 36, offset = 0x80000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) hw->ram_size = 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) hw->ram_offset = 0x80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) hw->ram_size = t8 * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) } else if (t8 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) hw->ram_size = 0x20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) hw->ram_size = t8 * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) hw->intr_mask = IS_HW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /* Use PHY IRQ for all but fiber based Genesis board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) hw->intr_mask |= IS_EXT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) genesis_init(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /* switch power to VCC (WA for VAUX problem) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) skge_write8(hw, B0_POWER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) /* avoid boards with stuck Hardware error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) hw->intr_mask &= ~IS_HW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) /* Clear PHY COMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) reg &= ~PCI_PHY_COMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) for (i = 0; i < hw->ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) /* turn off hardware timer (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) skge_write8(hw, B2_TI_CTRL, TIM_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) skge_write8(hw, B0_LED, LED_STAT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) /* enable the Tx Arbiters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) for (i = 0; i < hw->ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /* Initialize ram interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) /* Set interrupt moderation for Transmit only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) * Receive interrupts avoided by NAPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) skge_write32(hw, B2_IRQM_CTRL, TIM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) /* Leave irq disabled until first port is brought up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) skge_write32(hw, B0_IMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) for (i = 0; i < hw->ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) genesis_reset(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) yukon_reset(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) #ifdef CONFIG_SKGE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) static struct dentry *skge_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) static int skge_debug_show(struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) struct net_device *dev = seq->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) const struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) const struct skge_hw *hw = skge->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) const struct skge_element *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) return -ENETDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) skge_read32(hw, B0_IMSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) const struct skge_tx_desc *t = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) t->control, t->dma_hi, t->dma_lo, t->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) t->csum_offs, t->csum_write, t->csum_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) seq_puts(seq, "\nRx Ring:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) for (e = skge->rx_ring.to_clean; ; e = e->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) const struct skge_rx_desc *r = e->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) if (r->control & BMU_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) r->control, r->dma_hi, r->dma_lo, r->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) r->timestamp, r->csum1, r->csum1_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) DEFINE_SHOW_ATTRIBUTE(skge_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) * Use network device events to create/remove/rename
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) * debugfs file entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) static int skge_device_event(struct notifier_block *unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) struct net_device *dev = netdev_notifier_info_to_dev(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) struct skge_port *skge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) case NETDEV_CHANGENAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) if (skge->debugfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) skge->debugfs = debugfs_rename(skge_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) skge->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) skge_debug, dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) case NETDEV_GOING_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) debugfs_remove(skge->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) skge->debugfs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) case NETDEV_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) dev, &skge_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) static struct notifier_block skge_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) .notifier_call = skge_device_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) static __init void skge_debug_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) skge_debug = debugfs_create_dir("skge", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) register_netdevice_notifier(&skge_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) static __exit void skge_debug_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) if (skge_debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) unregister_netdevice_notifier(&skge_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) debugfs_remove(skge_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) skge_debug = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) #define skge_debug_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) #define skge_debug_cleanup()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) static const struct net_device_ops skge_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) .ndo_open = skge_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) .ndo_stop = skge_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) .ndo_start_xmit = skge_xmit_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) .ndo_do_ioctl = skge_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) .ndo_get_stats = skge_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) .ndo_tx_timeout = skge_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) .ndo_change_mtu = skge_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) .ndo_set_rx_mode = skge_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) .ndo_set_mac_address = skge_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) .ndo_poll_controller = skge_netpoll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /* Initialize network device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) static struct net_device *skge_devinit(struct skge_hw *hw, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) int highmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) struct skge_port *skge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) struct net_device *dev = alloc_etherdev(sizeof(*skge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) SET_NETDEV_DEV(dev, &hw->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) dev->netdev_ops = &skge_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) dev->ethtool_ops = &skge_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) dev->watchdog_timeo = TX_WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) dev->irq = hw->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) /* MTU range: 60 - 9000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) dev->min_mtu = ETH_ZLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) dev->max_mtu = ETH_JUMBO_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) if (highmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) dev->features |= NETIF_F_HIGHDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) skge->netdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) skge->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) skge->msg_enable = netif_msg_init(debug, default_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) /* Auto speed and flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) skge->autoneg = AUTONEG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) skge->flow_control = FLOW_MODE_SYM_OR_REM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) skge->duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) skge->speed = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) skge->advertising = skge_supported_modes(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) if (device_can_wakeup(&hw->pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) skge->wol = wol_supported(hw) & WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) hw->dev[port] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) skge->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) /* Only used for Genesis XMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) if (is_genesis(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) timer_setup(&skge->link_timer, xm_link_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) dev->features |= dev->hw_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) /* read the mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) static void skge_show_addr(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) const struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) static int only_32bit_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) struct net_device *dev, *dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) struct skge_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) int err, using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) dev_err(&pdev->dev, "cannot enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) err = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) dev_err(&pdev->dev, "cannot obtain PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) goto err_out_disable_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) using_dac = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) dev_err(&pdev->dev, "no usable DMA configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) goto err_out_free_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) /* byte swap descriptors in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) reg |= PCI_REV_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) /* space for skge@pci:0000:04:00.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) goto err_out_free_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) hw->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) spin_lock_init(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) spin_lock_init(&hw->phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) tasklet_setup(&hw->phy_task, skge_extirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) if (!hw->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) dev_err(&pdev->dev, "cannot map device registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) goto err_out_free_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) err = skge_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) DRV_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) skge_board_name(hw), hw->chip_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) dev = skge_devinit(hw, 0, using_dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) goto err_out_led_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) /* Some motherboards are broken and has zero in ROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) if (!is_valid_ether_addr(dev->dev_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) dev_err(&pdev->dev, "cannot register net device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) goto err_out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) skge_show_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) if (hw->ports > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) dev1 = skge_devinit(hw, 1, using_dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) if (!dev1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) goto err_out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) err = register_netdev(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) dev_err(&pdev->dev, "cannot register second net device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) goto err_out_free_dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) hw->irq_name, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) dev_err(&pdev->dev, "cannot assign irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) goto err_out_unregister_dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) skge_show_addr(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) pci_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) err_out_unregister_dev1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) unregister_netdev(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) err_out_free_dev1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) free_netdev(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) err_out_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) err_out_free_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) err_out_led_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) skge_write16(hw, B0_LED, LED_STAT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) iounmap(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) err_out_free_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) err_out_free_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) err_out_disable_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) static void skge_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) struct skge_hw *hw = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) struct net_device *dev0, *dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) dev1 = hw->dev[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) if (dev1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) unregister_netdev(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) dev0 = hw->dev[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) unregister_netdev(dev0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) tasklet_kill(&hw->phy_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) spin_lock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) hw->intr_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) if (hw->ports > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) skge_write32(hw, B0_IMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) skge_read32(hw, B0_IMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) spin_unlock_irq(&hw->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) skge_write16(hw, B0_LED, LED_STAT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) skge_write8(hw, B0_CTST, CS_RST_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) if (hw->ports > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) free_irq(pdev->irq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) if (dev1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) free_netdev(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) free_netdev(dev0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) iounmap(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) static int skge_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) struct skge_hw *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) for (i = 0; i < hw->ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) struct net_device *dev = hw->dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) skge_down(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) if (skge->wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) skge_wol_init(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) skge_write32(hw, B0_IMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) static int skge_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) struct skge_hw *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) err = skge_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) for (i = 0; i < hw->ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) struct net_device *dev = hw->dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) err = skge_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) netdev_err(dev, "could not up: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) dev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) #define SKGE_PM_OPS (&skge_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) #define SKGE_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) static void skge_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) struct skge_hw *hw = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) for (i = 0; i < hw->ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) struct net_device *dev = hw->dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) struct skge_port *skge = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) if (skge->wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) skge_wol_init(skge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) pci_set_power_state(pdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static struct pci_driver skge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) .id_table = skge_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) .probe = skge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) .remove = skge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) .shutdown = skge_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) .driver.pm = SKGE_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) static const struct dmi_system_id skge_32bit_dma_boards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) .ident = "Gigabyte nForce boards",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) DMI_MATCH(DMI_BOARD_NAME, "nForce"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) .ident = "ASUS P5NSLI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) .ident = "FUJITSU SIEMENS A8NE-FM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) static int __init skge_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) if (dmi_check_system(skge_32bit_dma_boards))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) only_32bit_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) skge_debug_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) return pci_register_driver(&skge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) static void __exit skge_cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) pci_unregister_driver(&skge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) skge_debug_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) module_init(skge_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) module_exit(skge_cleanup_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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