^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rami Rosen <rosenr@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/inetdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <net/hwbm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "mvneta_bm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <net/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <net/ipv6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <net/tso.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <net/page_pool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/bpf_trace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MVNETA_PORT_RX_RESET 0x1cc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MVNETA_PORT_RX_DMA_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MVNETA_PHY_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MVNETA_PHY_ADDR_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MVNETA_MBUS_RETRY 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MVNETA_UNIT_INTR_CAUSE 0x2080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MVNETA_UNIT_CONTROL 0x20B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MVNETA_PHY_POLLING_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MVNETA_BASE_ADDR_ENABLE 0x2290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MVNETA_PORT_CONFIG 0x2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MVNETA_UNI_PROMISC_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MVNETA_DEF_RXQ(q) ((q) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MVNETA_DEF_RXQ_ARP(q) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MVNETA_DEF_RXQ_TCP(q) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MVNETA_DEF_RXQ_UDP(q) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MVNETA_DEF_RXQ_BPDU(q) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MVNETA_TX_UNSET_ERR_SUM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MVNETA_PORT_CONFIG_EXTEND 0x2404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MVNETA_MAC_ADDR_LOW 0x2414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MVNETA_MAC_ADDR_HIGH 0x2418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MVNETA_SDMA_CONFIG 0x241c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MVNETA_SDMA_BRST_SIZE_16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MVNETA_RX_NO_DATA_SWAP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MVNETA_TX_NO_DATA_SWAP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MVNETA_DESC_SWAP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MVNETA_PORT_STATUS 0x2444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MVNETA_TX_IN_PRGRS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MVNETA_TX_FIFO_EMPTY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Only exists on Armada XP and Armada 370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MVNETA_SERDES_CFG 0x24A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MVNETA_QSGMII_SERDES_PROTO 0x0667
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MVNETA_HSGMII_SERDES_PROTO 0x1107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MVNETA_TYPE_PRIO 0x24bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MVNETA_FORCE_UNI BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MVNETA_TXQ_CMD_1 0x24e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MVNETA_TXQ_CMD 0x2448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MVNETA_TXQ_DISABLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MVNETA_ACC_MODE 0x2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MVNETA_BM_ADDRESS 0x2504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Exception Interrupt Port/Queue Cause register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Their behavior depend of the mapping done using the PCPX2Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * registers. For a given CPU if the bit associated to a queue is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * set, then for the register a read from this CPU will always return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 0 and a write won't do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MVNETA_INTR_NEW_CAUSE 0x25a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MVNETA_INTR_NEW_MASK 0x25a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* bits 0..7 = TXQ SENT, one bit per queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * bits 8..15 = RXQ OCCUP, one bit per queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * bits 16..23 = RXQ FREE, one bit per queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * bit 29 = OLD_REG_SUM, see old reg ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * bit 30 = TX_ERR_SUM, one bit for 4 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * bit 31 = MISC_SUM, one bit for 4 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MVNETA_MISCINTR_INTR_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MVNETA_INTR_OLD_CAUSE 0x25a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MVNETA_INTR_OLD_MASK 0x25ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Data Path Port/Queue Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MVNETA_INTR_MISC_CAUSE 0x25b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MVNETA_INTR_MISC_MASK 0x25b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MVNETA_CAUSE_PTP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MVNETA_CAUSE_PRBS_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MVNETA_INTR_ENABLE 0x25b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MVNETA_RXQ_CMD 0x2680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MVNETA_RXQ_DISABLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MVNETA_GMAC_CTRL_0 0x2c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MVNETA_GMAC_CTRL_2 0x2c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MVNETA_GMAC2_PORT_RGMII BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MVNETA_GMAC2_PORT_RESET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MVNETA_GMAC_STATUS 0x2c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MVNETA_GMAC_LINK_UP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MVNETA_GMAC_SPEED_1000 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MVNETA_GMAC_SPEED_100 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MVNETA_GMAC_AN_COMPLETE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MVNETA_GMAC_SYNC_OK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MVNETA_GMAC_CTRL_4 0x2c90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MVNETA_MIB_COUNTERS_BASE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MVNETA_MIB_LATE_COLLISION 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MVNETA_DA_FILT_OTH_MCAST 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MVNETA_DA_FILT_UCAST_BASE 0x3600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MVNETA_TXQ_DEC_SENT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MVNETA_TXQ_DEC_SENT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MVNETA_TXQ_SENT_DESC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MVNETA_PORT_TX_RESET 0x3cf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MVNETA_PORT_TX_DMA_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MVNETA_TX_MTU 0x3e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MVNETA_TX_TOKEN_SIZE 0x3e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MVNETA_LPI_CTRL_0 0x2cc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MVNETA_LPI_CTRL_1 0x2cc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MVNETA_LPI_CTRL_2 0x2cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MVNETA_LPI_STATUS 0x2ccc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Descriptor ring Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MVNETA_QUEUE_NEXT_DESC(q, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (((index) < (q)->last_desc) ? ((index) + 1) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Various constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MVNETA_RX_COAL_PKTS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MVNETA_RX_COAL_USEC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* The two bytes Marvell header. Either contains a special value used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * by Marvell switches when a specific hardware mode is enabled (not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * supported by this driver) or is filled automatically by zeroes on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * the RX side. Those two bytes being at the front of the Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * header, they allow to have the IP header aligned on a 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * boundary automatically: the hardware skips those two bytes on its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MVNETA_MH_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MVNETA_VLAN_TAG_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MVNETA_TX_CSUM_DEF_SIZE 1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MVNETA_TX_CSUM_MAX_SIZE 9800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MVNETA_ACC_MODE_EXT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MVNETA_ACC_MODE_EXT2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MVNETA_MAX_DECODE_WIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Timeout constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MVNETA_TX_MTU_MAX 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* The RSS lookup table actually has 256 entries but we do not use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * them yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MVNETA_RSS_LU_TABLE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Max number of Rx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MVNETA_MAX_RXD 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Max number of Tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MVNETA_MAX_TXD 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Max number of allowed TCP segments for software TSO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MVNETA_MAX_TSO_SEGS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* descriptor aligned size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MVNETA_DESC_ALIGNED_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Number of bytes to be taken into account by HW when putting incoming data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MVNETA_RX_PKT_SIZE(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ETH_HLEN + ETH_FCS_LEN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cache_line_size())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Driver assumes that the last 3 bits are 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MVNETA_SKB_HEADROOM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IS_TSO_HEADER(txq, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ((addr >= txq->tso_hdrs_phys) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ETHTOOL_STAT_EEE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ETHTOOL_STAT_SKB_ALLOC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ETHTOOL_STAT_REFILL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ETHTOOL_XDP_REDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ETHTOOL_XDP_PASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ETHTOOL_XDP_DROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ETHTOOL_XDP_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ETHTOOL_XDP_TX_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ETHTOOL_XDP_XMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ETHTOOL_XDP_XMIT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ETHTOOL_MAX_STATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct mvneta_statistic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned short type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const char name[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define T_REG_32 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define T_REG_64 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define T_SW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MVNETA_XDP_PASS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MVNETA_XDP_DROPPED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MVNETA_XDP_TX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MVNETA_XDP_REDIR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct mvneta_statistic mvneta_statistics[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x3000, T_REG_64, "good_octets_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0x3010, T_REG_32, "good_frames_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 0x3008, T_REG_32, "bad_octets_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { 0x3014, T_REG_32, "bad_frames_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x3018, T_REG_32, "broadcast_frames_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0x301c, T_REG_32, "multicast_frames_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { 0x3050, T_REG_32, "unrec_mac_control_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x3058, T_REG_32, "good_fc_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x305c, T_REG_32, "bad_fc_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x3060, T_REG_32, "undersize_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x3064, T_REG_32, "fragments_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0x3068, T_REG_32, "oversize_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x306c, T_REG_32, "jabber_received", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x3070, T_REG_32, "mac_receive_error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x3074, T_REG_32, "bad_crc_event", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x3078, T_REG_32, "collision", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x307c, T_REG_32, "late_collision", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x2484, T_REG_32, "rx_discard", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x2488, T_REG_32, "rx_overrun", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x3020, T_REG_32, "frames_64_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x3024, T_REG_32, "frames_65_to_127_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x3028, T_REG_32, "frames_128_to_255_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x302c, T_REG_32, "frames_256_to_511_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 0x3038, T_REG_64, "good_octets_sent", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0x3040, T_REG_32, "good_frames_sent", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x3044, T_REG_32, "excessive_collision", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0x3048, T_REG_32, "multicast_frames_sent", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x304c, T_REG_32, "broadcast_frames_sent", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0x3054, T_REG_32, "fc_sent", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 0x300c, T_REG_32, "internal_mac_transmit_err", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mvneta_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u64 rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* xdp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u64 xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u64 xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u64 xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u64 xdp_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u64 xdp_xmit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u64 xdp_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u64 xdp_tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct mvneta_ethtool_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mvneta_stats ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u64 skb_alloc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u64 refill_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct mvneta_pcpu_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct u64_stats_sync syncp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct mvneta_ethtool_stats es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u64 rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct mvneta_pcpu_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Pointer to the shared port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct mvneta_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Pointer to the CPU-local NAPI struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Cause of the previous interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __MVNETA_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct mvneta_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mvneta_pcpu_port __percpu *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct mvneta_pcpu_stats __percpu *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct mvneta_rx_queue *rxqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct mvneta_tx_queue *txqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct hlist_node node_online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct hlist_node node_dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int rxq_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Protect the access to the percpu interrupt registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * ensuring that the configuration remains coherent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bool is_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct bpf_prog *xdp_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* AXI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct clk *clk_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 mcast_count[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u16 tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) phy_interface_t phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int tx_csum_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct phylink *phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct phylink_config phylink_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct phy *comphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct mvneta_bm *bm_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct mvneta_bm_pool *pool_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct mvneta_bm_pool *pool_short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int bm_win_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bool eee_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool eee_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bool tx_lpi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Flags for special SoC configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool neta_armada3700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u16 rx_offset_correction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const struct mbus_dram_target_info *dram_target_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * layout of the transmit and reception DMA descriptors, and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * layout is therefore defined by the hardware design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MVNETA_TX_L3_OFF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MVNETA_TX_IP_HLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define MVNETA_TX_L4_UDP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define MVNETA_TX_L3_IP6 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MVNETA_TXD_IP_CSUM BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MVNETA_TXD_Z_PAD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MVNETA_TXD_L_DESC BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MVNETA_TXD_F_DESC BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MVNETA_TXD_L_DESC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MVNETA_TXD_F_DESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MVNETA_TX_L4_CSUM_FULL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define MVNETA_TX_L4_CSUM_NOT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MVNETA_RXD_ERR_CRC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define MVNETA_RXD_BM_POOL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define MVNETA_RXD_ERR_SUMMARY BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define MVNETA_RXD_ERR_OVERRUN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define MVNETA_RXD_ERR_LEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MVNETA_RXD_L3_IP4 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define MVNETA_RXD_LAST_DESC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MVNETA_RXD_FIRST_DESC BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MVNETA_RXD_LAST_DESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MVNETA_RXD_L4_CSUM_OK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #if defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mvneta_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 command; /* Options used by HW for packet transmitting.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u16 reserved1; /* csum_l4 (for future use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u16 data_size; /* Data size of transmitted packet in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 buf_phys_addr; /* Physical addr of transmitted buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 reserved2; /* hw_cmd - (for future use, PMT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 reserved3[4]; /* Reserved - (for future use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct mvneta_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 status; /* Info about received packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u16 reserved1; /* pnc_info - (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u16 data_size; /* Size of received packet in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 buf_phys_addr; /* Physical address of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 reserved2; /* pnc_flow_id (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 buf_cookie; /* cookie for access to RX buffer in rx path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u16 reserved3; /* prefetch_cmd, for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u16 reserved4; /* csum_l4 - (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct mvneta_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u16 data_size; /* Data size of transmitted packet in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u16 reserved1; /* csum_l4 (for future use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 command; /* Options used by HW for packet transmitting.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 reserved2; /* hw_cmd - (for future use, PMT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 buf_phys_addr; /* Physical addr of transmitted buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 reserved3[4]; /* Reserved - (for future use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct mvneta_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 data_size; /* Size of received packet in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 reserved1; /* pnc_info - (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 status; /* Info about received packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 reserved2; /* pnc_flow_id (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 buf_phys_addr; /* Physical address of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u16 reserved4; /* csum_l4 - (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u16 reserved3; /* prefetch_cmd, for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 buf_cookie; /* cookie for access to RX buffer in rx path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) enum mvneta_tx_buf_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MVNETA_TYPE_SKB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MVNETA_TYPE_XDP_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MVNETA_TYPE_XDP_NDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct mvneta_tx_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) enum mvneta_tx_buf_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct xdp_frame *xdpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct mvneta_tx_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Number of this TX queue, in the range 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Number of TX DMA descriptors in the descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Number of currently used TX DMA descriptor in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int tx_stop_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int tx_wake_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Array of transmitted buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct mvneta_tx_buf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Index of last TX DMA descriptor that was inserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int txq_put_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Index of the TX DMA descriptor to be cleaned up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int txq_get_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 done_pkts_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Virtual address of the TX DMA descriptors array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct mvneta_tx_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* DMA address of the TX DMA descriptors array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dma_addr_t descs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Index of the last TX DMA descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int last_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Index of the next TX DMA descriptor to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int next_desc_to_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* DMA buffers for TSO headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) char *tso_hdrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* DMA address of TSO headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dma_addr_t tso_hdrs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Affinity mask for CPUs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cpumask_t affinity_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mvneta_rx_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* rx queue number, in the range 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* num of rx descriptors in the rx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 pkts_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 time_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* page_pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct page_pool *page_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct xdp_rxq_info xdp_rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Virtual address of the RX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) void **buf_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Virtual address of the RX DMA descriptors array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct mvneta_rx_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* DMA address of the RX DMA descriptors array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dma_addr_t descs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Index of the last RX DMA descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int last_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Index of the next RX DMA descriptor to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int next_desc_to_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Index of first RX DMA descriptor to refill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int first_to_refill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 refill_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static enum cpuhp_state online_hpstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* The hardware supports eight (8) rx queues, but we are only allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * the first one to be used. Therefore, let's just allocate one queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int rxq_number = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int txq_number = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int rxq_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int rx_copybreak __read_mostly = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* HW BM need that each port be identify by a unique ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int global_port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define MVNETA_DRIVER_NAME "mvneta"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define MVNETA_DRIVER_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Utility/helper methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Write helper method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel(data, pp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Read helper method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return readl(pp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Increment txq get counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) txq->txq_get_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (txq->txq_get_index == txq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) txq->txq_get_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Increment txq put counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) txq->txq_put_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (txq->txq_put_index == txq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) txq->txq_put_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Clear all MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void mvneta_mib_counters_clear(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Perform dummy reads from MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Get System Network Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mvneta_get_stats64(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct rtnl_link_stats64 *stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct mvneta_pcpu_stats *cpu_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u64 rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u64 rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u64 rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cpu_stats = per_cpu_ptr(pp->stats, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) rx_packets = cpu_stats->es.ps.rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) rx_bytes = cpu_stats->es.ps.rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) rx_dropped = cpu_stats->rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) rx_errors = cpu_stats->rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) tx_packets = cpu_stats->es.ps.tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) tx_bytes = cpu_stats->es.ps.tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) stats->rx_packets += rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) stats->rx_bytes += rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) stats->rx_dropped += rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) stats->rx_errors += rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) stats->tx_packets += tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) stats->tx_bytes += tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) stats->tx_dropped = dev->stats.tx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Rx descriptors helper methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Checks whether the RX descriptor having this status is both the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * and the last descriptor for the RX packet. Each RX packet is currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * received through a single RX descriptor, so not having each RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * descriptor with its first and last bits set is an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int mvneta_rxq_desc_is_first_last(u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MVNETA_RXD_FIRST_LAST_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Add number of descriptors ready to receive new packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int ndescs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * be added at once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Get number of RX descriptors occupied by received packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Update num of rx desc called upon return from rx path or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * from mvneta_rxq_drop_pkts().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int rx_done, int rx_filled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) val = rx_done |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Only 255 descriptors can be added at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) while ((rx_done > 0) || (rx_filled > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (rx_done <= 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) val = rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) rx_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) val = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rx_done -= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (rx_filled <= 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) rx_filled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) rx_filled -= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Get pointer to next RX descriptor to be processed by SW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static struct mvneta_rx_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int rx_desc = rxq->next_desc_to_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) prefetch(rxq->descs + rxq->next_desc_to_proc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return rxq->descs + rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Change maximum receive size of the port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Set rx queue offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void mvneta_rxq_offset_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Offset is in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Tx descriptors helper methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Update HW with number of TX descriptors to be sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct mvneta_tx_queue *txq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int pend_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pend_desc += txq->pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Only 255 Tx descriptors can be added at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) val = min(pend_desc, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pend_desc -= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } while (pend_desc > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) txq->pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Get pointer to next TX descriptor to be processed (send) by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct mvneta_tx_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int tx_desc = txq->next_desc_to_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return txq->descs + tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Release the last allocated TX descriptor. Useful to handle DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * mapping failures in the TX path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (txq->next_desc_to_proc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) txq->next_desc_to_proc = txq->last_desc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) txq->next_desc_to_proc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Set rxq buf size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* Disable buffer management (BM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Enable buffer management (BM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) val |= MVNETA_RXQ_HW_BUF_ALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Notify HW about port's assignment of pool for bigger packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Notify HW about port's assignment of pool for smaller packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Set port's receive buffer size for assigned BM pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u8 pool_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!IS_ALIGNED(buf_size, 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_warn(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "illegal buf_size value %d, round to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) buf_size, ALIGN(buf_size, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) buf_size = ALIGN(buf_size, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Configure MBUS window in order to enable access BM internal SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u8 target, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 win_enable, win_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (pp->bm_win_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Find first not occupied window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (win_enable & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pp->bm_win_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (i == MVNETA_MAX_DECODE_WIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) i = pp->bm_win_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) (attr << 8) | target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) win_protect |= 3 << (2 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) win_enable &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u8 target, attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* Get BM window information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) &target, &attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pp->bm_win_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Open NETA -> BM window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) netdev_info(pp->dev, "fail to configure mbus window to BM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* Assign and initialize pools for port. In case of fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * buffer manager will remain disabled for current port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int mvneta_bm_port_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u32 long_pool_id, short_pool_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = mvneta_bm_port_mbus_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) netdev_info(pp->dev, "missing long pool id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Create port's long pool depending on mtu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MVNETA_BM_LONG, pp->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MVNETA_RX_PKT_SIZE(pp->dev->mtu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!pp->pool_long) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) netdev_info(pp->dev, "fail to obtain long pool for port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) pp->pool_long->port_map |= 1 << pp->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) pp->pool_long->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* If short pool id is not defined, assume using single pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) short_pool_id = long_pool_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Create port's short pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) MVNETA_BM_SHORT, pp->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MVNETA_BM_SHORT_PKT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (!pp->pool_short) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) netdev_info(pp->dev, "fail to obtain short pool for port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (short_pool_id != long_pool_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pp->pool_short->port_map |= 1 << pp->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pp->pool_short->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* Update settings of a pool for bigger packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct mvneta_bm_pool *bm_pool = pp->pool_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Release all buffers from long pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (hwbm_pool->buf_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) WARN(1, "cannot free all buffers in pool %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) bm_pool->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) goto bm_mtu_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* Fill entire long pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (num != hwbm_pool->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) WARN(1, "pool %d: %d of %d allocated\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) bm_pool->id, num, hwbm_pool->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) goto bm_mtu_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) bm_mtu_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) pp->bm_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Start the Ethernet port RX and TX activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static void mvneta_port_up(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 q_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Enable all initialized TXs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) q_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct mvneta_tx_queue *txq = &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (txq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) q_map |= (1 << queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) q_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Enable all initialized RXQs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (rxq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) q_map |= (1 << queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Stop the Ethernet port activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static void mvneta_port_down(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Stop Rx port activity. Check port Rx activity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Issue stop command for active channels only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mvreg_write(pp, MVNETA_RXQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) val << MVNETA_RXQ_DISABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* Wait for all Rx activity to terminate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) netdev_warn(pp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val = mvreg_read(pp, MVNETA_RXQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) } while (val & MVNETA_RXQ_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Stop Tx port activity. Check port Tx activity. Issue stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * command for active channels only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) mvreg_write(pp, MVNETA_TXQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) (val << MVNETA_TXQ_DISABLE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Wait for all Tx activity to terminate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) netdev_warn(pp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) "TIMEOUT for TX stopped status=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Check TX Command reg that all Txqs are stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) val = mvreg_read(pp, MVNETA_TXQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) } while (val & MVNETA_TXQ_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* Double check to verify that TX FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) netdev_warn(pp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "TX FIFO empty timeout status=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) val = mvreg_read(pp, MVNETA_PORT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) (val & MVNETA_TX_IN_PRGRS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Enable the port by setting the port enable bit of the MAC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void mvneta_port_enable(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Enable port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) val |= MVNETA_GMAC0_PORT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Disable the port and wait for about 200 usec before retuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static void mvneta_port_disable(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Reset the Enable bit in the Serial Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) val &= ~MVNETA_GMAC0_PORT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Multicast tables methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) val = 0x1 | (queue << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) val |= (val << 24) | (val << 16) | (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) for (offset = 0; offset <= 0xc; offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) val = 0x1 | (queue << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) val |= (val << 24) | (val << 16) | (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) for (offset = 0; offset <= 0xfc; offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) val = 0x1 | (queue << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) val |= (val << 24) | (val << 16) | (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) for (offset = 0; offset <= 0xfc; offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static void mvneta_percpu_unmask_interrupt(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct mvneta_port *pp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* All the queue are unmasked, but actually only the ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * mapped to this CPU will be unmasked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) mvreg_write(pp, MVNETA_INTR_NEW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) MVNETA_RX_INTR_MASK_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) MVNETA_TX_INTR_MASK_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) MVNETA_MISCINTR_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static void mvneta_percpu_mask_interrupt(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct mvneta_port *pp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* All the queue are masked, but actually only the ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * mapped to this CPU will be masked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static void mvneta_percpu_clear_intr_cause(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct mvneta_port *pp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* All the queue are cleared, but actually only the ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * mapped to this CPU will be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* This method sets defaults to the NETA port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * Clears interrupt Cause and Mask registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * Clears all MAC tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * Sets defaults to all registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * Resets RX and TX descriptor rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * Resets PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * This method can be called after mvneta_port_down() to return the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * settings to defaults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static void mvneta_defaults_set(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int max_cpu = num_present_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Clear all Cause registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Enable MBUS Retry bit16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Set CPU queue access map. CPUs are assigned to the RX and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * TX queues modulo their number. If there is only one TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * queue then it is assigned to the CPU associated to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * default RX queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) for_each_present_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) int rxq_map = 0, txq_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int rxq, txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) for (rxq = 0; rxq < rxq_number; rxq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if ((rxq % max_cpu) == cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) for (txq = 0; txq < txq_number; txq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if ((txq % max_cpu) == cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* With only one TX queue we configure a special case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * which will allow to get all the irq on a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (txq_number == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) txq_map = (cpu == pp->rxq_def) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) MVNETA_CPU_TXQ_ACCESS(1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Reset RX and TX DMAs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Disable Legacy WRR, Disable EJP, Release from reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Set Port Acceleration Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* HW buffer management + legacy parser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) val = MVNETA_ACC_MODE_EXT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* SW buffer management + legacy parser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) val = MVNETA_ACC_MODE_EXT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) mvreg_write(pp, MVNETA_ACC_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Update val of portCfg register accordingly with all RxQueue types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mvreg_write(pp, MVNETA_PORT_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* Build PORT_SDMA_CONFIG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* Default burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) val |= MVNETA_DESC_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* Assign port SDMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* Disable PHY polling in hardware, since we're using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * kernel phylib to do this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) val &= ~MVNETA_PHY_POLLING_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) mvneta_set_ucast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) mvneta_set_special_mcast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) mvneta_set_other_mcast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Set port interrupt enable register - default enable all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) mvreg_write(pp, MVNETA_INTR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) mvneta_mib_counters_clear(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* Set max sizes for tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u32 val, size, mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) mtu = max_tx_size * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (mtu > MVNETA_TX_MTU_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) mtu = MVNETA_TX_MTU_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Set MTU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) val = mvreg_read(pp, MVNETA_TX_MTU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) val &= ~MVNETA_TX_MTU_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) val |= mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) mvreg_write(pp, MVNETA_TX_MTU, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* TX token size and all TXQs token size must be larger that MTU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) size = val & MVNETA_TX_TOKEN_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (size < mtu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) size = mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) val |= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (size < mtu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) size = mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) val |= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Set unicast address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) unsigned int unicast_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) unsigned int tbl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Locate the Unicast table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) last_nibble = (0xf & last_nibble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* offset from unicast tbl base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) tbl_offset = (last_nibble / 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* offset within the above reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) reg_offset = last_nibble % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* Clear accepts frame bit at specified unicast DA tbl entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) unicast_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) unicast_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Set mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned int mac_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unsigned int mac_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (queue != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mac_l = (addr[4] << 8) | (addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) mac_h = (addr[0] << 24) | (addr[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) (addr[2] << 8) | (addr[3] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* Accept frames of this address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) mvneta_set_ucast_addr(pp, addr[5], queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Set the number of packets that will be received before RX interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * will be generated by HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct mvneta_rx_queue *rxq, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) value | MVNETA_RXQ_NON_OCCUPIED(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* Set the time delay in usec before RX interrupt will be generated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct mvneta_rx_queue *rxq, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) clk_rate = clk_get_rate(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) val = (clk_rate / 1000000) * value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* Set threshold for TX_DONE pkts coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct mvneta_tx_queue *txq, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u32 phys_addr, void *virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) rx_desc->buf_phys_addr = phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) i = rx_desc - rxq->descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) rxq->buf_virt_addr[i] = virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Decrement sent descriptors counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct mvneta_tx_queue *txq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) int sent_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Only 255 TX descriptors can be updated at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) while (sent_desc > 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) sent_desc = sent_desc - 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* Get number of TX descriptors already sent by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) int sent_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) MVNETA_TXQ_SENT_DESC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return sent_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* Get number of sent descriptors and decrement counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) * The number of sent descriptors is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int sent_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* Get number of sent descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* Decrement sent descriptors counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (sent_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return sent_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* Set TXQ descriptors fields relevant for CSUM calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) int ip_hdr_len, int l4_proto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * G_L4_chk, L4_type; required only for checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (l3_proto == htons(ETH_P_IP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) command |= MVNETA_TXD_IP_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) command |= MVNETA_TX_L3_IP6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (l4_proto == IPPROTO_TCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) command |= MVNETA_TX_L4_CSUM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) else if (l4_proto == IPPROTO_UDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) command |= MVNETA_TX_L4_CSUM_NOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* Display more error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static void mvneta_rx_error(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct mvneta_rx_desc *rx_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) u32 status = rx_desc->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* update per-cpu counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) switch (status & MVNETA_RXD_ERR_CODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case MVNETA_RXD_ERR_CRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) status, rx_desc->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) case MVNETA_RXD_ERR_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) status, rx_desc->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) case MVNETA_RXD_ERR_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) status, rx_desc->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) case MVNETA_RXD_ERR_RESOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) status, rx_desc->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* Handle RX checksum offload based on the descriptor's status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if ((pp->dev->features & NETIF_F_RXCSUM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) (status & MVNETA_RXD_L3_IP4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) (status & MVNETA_RXD_L4_CSUM_OK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) skb->csum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) skb->ip_summed = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* Return tx queue pointer (find last set bit) according to <cause> returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * form tx_done reg. <cause> must not be null. The return value is always a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * valid queue for matching the first one found in <cause>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) u32 cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) int queue = fls(cause) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* Free tx queue skbuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static void mvneta_txq_bufs_free(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct mvneta_tx_queue *txq, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct netdev_queue *nq, bool napi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) unsigned int bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) struct mvneta_tx_desc *tx_desc = txq->descs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) txq->txq_get_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) mvneta_txq_inc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) buf->type != MVNETA_TYPE_XDP_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) dma_unmap_single(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) tx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) tx_desc->data_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (buf->type == MVNETA_TYPE_SKB && buf->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) bytes_compl += buf->skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_kfree_skb_any(buf->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) } else if (buf->type == MVNETA_TYPE_XDP_TX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) buf->type == MVNETA_TYPE_XDP_NDO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (napi && buf->type == MVNETA_TYPE_XDP_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) xdp_return_frame_rx_napi(buf->xdpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) xdp_return_frame(buf->xdpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* Handle end of transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static void mvneta_txq_done(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) int tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) tx_done = mvneta_txq_sent_desc_proc(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (!tx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) mvneta_txq_bufs_free(pp, txq, tx_done, nq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) txq->count -= tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (netif_tx_queue_stopped(nq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (txq->count <= txq->tx_wake_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) netif_tx_wake_queue(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* Refill processing for SW buffer management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* Allocate page per descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static int mvneta_rx_refill(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct mvneta_rx_desc *rx_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) gfp_t gfp_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) page = page_pool_alloc_pages(rxq->page_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) gfp_mask | __GFP_NOWARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* Handle tx checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) int ip_hdr_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) __be16 l3_proto = vlan_get_protocol(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) u8 l4_proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (l3_proto == htons(ETH_P_IP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) struct iphdr *ip4h = ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* Calculate IPv4 checksum and L4 checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ip_hdr_len = ip4h->ihl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) l4_proto = ip4h->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) } else if (l3_proto == htons(ETH_P_IPV6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) struct ipv6hdr *ip6h = ipv6_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* Read l4_protocol from one of IPv6 extra headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (skb_network_header_len(skb) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ip_hdr_len = (skb_network_header_len(skb) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) l4_proto = ip6h->nexthdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return MVNETA_TX_L4_CSUM_NOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) return mvneta_txq_desc_csum(skb_network_offset(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) l3_proto, ip_hdr_len, l4_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return MVNETA_TX_L4_CSUM_NOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Drop packets received by the RXQ and free buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) int rx_done, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (rx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) for (i = 0; i < rx_done; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct mvneta_rx_desc *rx_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) mvneta_rxq_next_desc_get(rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct mvneta_bm_pool *bm_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) bm_pool = &pp->bm_priv->bm_pools[pool_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* Return dropped buffer to the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) rx_desc->buf_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) for (i = 0; i < rxq->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct mvneta_rx_desc *rx_desc = rxq->descs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) void *data = rxq->buf_virt_addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (!data || !(rx_desc->buf_phys_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) page_pool_put_full_page(rxq->page_pool, data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) xdp_rxq_info_unreg(&rxq->xdp_rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) page_pool_destroy(rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) rxq->page_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) mvneta_update_stats(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) struct mvneta_stats *ps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) stats->es.ps.rx_packets += ps->rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) stats->es.ps.rx_bytes += ps->rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* xdp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) stats->es.ps.xdp_redirect += ps->xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) stats->es.ps.xdp_pass += ps->xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) stats->es.ps.xdp_drop += ps->xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct mvneta_rx_desc *rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) int curr_desc = rxq->first_to_refill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) rx_desc = rxq->descs + curr_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (!(rx_desc->buf_phys_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct mvneta_pcpu_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) pr_err("Can't refill queue %d. Done %d from %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) rxq->id, i, rxq->refill_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) stats->es.refill_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) rxq->refill_num -= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) rxq->first_to_refill = curr_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct xdp_buff *xdp, int sync_len, bool napi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) for (i = 0; i < sinfo->nr_frags; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) page_pool_put_full_page(rxq->page_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) skb_frag_page(&sinfo->frags[i]), napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) sync_len, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct xdp_frame *xdpf, bool dma_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct mvneta_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct mvneta_tx_buf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (txq->count >= txq->tx_stop_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return MVNETA_XDP_DROPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) tx_desc = mvneta_txq_next_desc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) buf = &txq->buf[txq->txq_put_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (dma_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* ndo_xdp_xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) xdpf->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return MVNETA_XDP_DROPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) buf->type = MVNETA_TYPE_XDP_NDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct page *page = virt_to_page(xdpf->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dma_addr = page_pool_get_dma_addr(page) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sizeof(*xdpf) + xdpf->headroom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dma_sync_single_for_device(pp->dev->dev.parent, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) xdpf->len, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) buf->type = MVNETA_TYPE_XDP_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) buf->xdpf = xdpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) tx_desc->command = MVNETA_TXD_FLZ_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) tx_desc->buf_phys_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) tx_desc->data_size = xdpf->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) txq->pending++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) txq->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return MVNETA_XDP_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct mvneta_tx_queue *txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct netdev_queue *nq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct xdp_frame *xdpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) xdpf = xdp_convert_buff_to_frame(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (unlikely(!xdpf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return MVNETA_XDP_DROPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) txq = &pp->txqs[cpu % txq_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) __netif_tx_lock(nq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (ret == MVNETA_XDP_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) stats->es.ps.tx_bytes += xdpf->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) stats->es.ps.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) stats->es.ps.xdp_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) mvneta_txq_pend_desc_add(pp, txq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) stats->es.ps.xdp_tx_err++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) __netif_tx_unlock(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) mvneta_xdp_xmit(struct net_device *dev, int num_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct xdp_frame **frames, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) int i, nxmit_byte = 0, nxmit = num_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct mvneta_tx_queue *txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct netdev_queue *nq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (unlikely(test_bit(__MVNETA_DOWN, &pp->state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return -ENETDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) txq = &pp->txqs[cpu % txq_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) __netif_tx_lock(nq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) for (i = 0; i < num_frame; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (ret == MVNETA_XDP_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) nxmit_byte += frames[i]->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) xdp_return_frame_rx_napi(frames[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) nxmit--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (unlikely(flags & XDP_XMIT_FLUSH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mvneta_txq_pend_desc_add(pp, txq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) __netif_tx_unlock(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) stats->es.ps.tx_bytes += nxmit_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) stats->es.ps.tx_packets += nxmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) stats->es.ps.xdp_xmit += nxmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) stats->es.ps.xdp_xmit_err += num_frame - nxmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) return nxmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct bpf_prog *prog, struct xdp_buff *xdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) u32 frame_sz, struct mvneta_stats *stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) unsigned int len, data_len, sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) u32 ret, act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) data_len = xdp->data_end - xdp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) act = bpf_prog_run_xdp(prog, xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) sync = max(sync, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) switch (act) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) case XDP_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) stats->xdp_pass++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) return MVNETA_XDP_PASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) case XDP_REDIRECT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) err = xdp_do_redirect(pp->dev, xdp, prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ret = MVNETA_XDP_DROPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ret = MVNETA_XDP_REDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) stats->xdp_redirect++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) case XDP_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ret = mvneta_xdp_xmit_back(pp, xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (ret != MVNETA_XDP_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) bpf_warn_invalid_xdp_action(act);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) case XDP_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) trace_xdp_exception(pp->dev, prog, act);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) case XDP_DROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ret = MVNETA_XDP_DROPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) stats->xdp_drop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) mvneta_swbm_rx_frame(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct mvneta_rx_desc *rx_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct xdp_buff *xdp, int *size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) unsigned char *data = page_address(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) int data_len = -MVNETA_MH_SIZE, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct net_device *dev = pp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) enum dma_data_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct skb_shared_info *sinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (*size > MVNETA_MAX_RX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) len = MVNETA_MAX_RX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) data_len += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) len = *size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) data_len += len - ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) *size = *size - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) dma_dir = page_pool_get_dma_dir(rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) dma_sync_single_for_cpu(dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) rx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) len, dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) rx_desc->buf_phys_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) /* Prefetch header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) prefetch(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) xdp->data_hard_start = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) xdp->data_end = xdp->data + data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) xdp_set_data_meta_invalid(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) sinfo = xdp_get_shared_info_from_buff(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) sinfo->nr_frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) mvneta_swbm_add_rx_fragment(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct mvneta_rx_desc *rx_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct xdp_buff *xdp, int *size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct net_device *dev = pp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) enum dma_data_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) int data_len, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (*size > MVNETA_MAX_RX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) len = MVNETA_MAX_RX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) data_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) len = *size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) data_len = len - ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) dma_dir = page_pool_get_dma_dir(rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dma_sync_single_for_cpu(dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) rx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) len, dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) rx_desc->buf_phys_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) skb_frag_off_set(frag, pp->rx_offset_correction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) skb_frag_size_set(frag, data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) __skb_frag_set_page(frag, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) sinfo->nr_frags++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) page_pool_put_full_page(rxq->page_pool, page, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) *size -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static struct sk_buff *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) mvneta_swbm_build_skb(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct xdp_buff *xdp, u32 desc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) int i, num_frags = sinfo->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) skb = build_skb(xdp->data_hard_start, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) page_pool_release_page(rxq->page_pool, virt_to_page(xdp->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) skb_reserve(skb, xdp->data - xdp->data_hard_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) skb_put(skb, xdp->data_end - xdp->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) mvneta_rx_csum(pp, desc_status, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) for (i = 0; i < num_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) skb_frag_t *frag = &sinfo->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) skb_frag_page(frag), skb_frag_off(frag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) skb_frag_size(frag), PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) page_pool_release_page(rxq->page_pool, skb_frag_page(frag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) /* Main rx processing when using software buffer management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static int mvneta_rx_swbm(struct napi_struct *napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) struct mvneta_port *pp, int budget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) int rx_proc = 0, rx_todo, refill, size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) struct net_device *dev = pp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) struct xdp_buff xdp_buf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .frame_sz = PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .rxq = &rxq->xdp_rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct mvneta_stats ps = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) struct bpf_prog *xdp_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) u32 desc_status, frame_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* Get number of received packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) xdp_prog = READ_ONCE(pp->xdp_prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* Fairness NAPI loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) while (rx_proc < budget && rx_proc < rx_todo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) u32 rx_status, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) index = rx_desc - rxq->descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) page = (struct page *)rxq->buf_virt_addr[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) rx_status = rx_desc->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) rx_proc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) rxq->refill_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (rx_status & MVNETA_RXD_FIRST_DESC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) /* Check errors only for FIRST descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) mvneta_rx_error(pp, rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) size = rx_desc->data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) frame_sz = size - ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) desc_status = rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) &size, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (unlikely(!xdp_buf.data_hard_start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) rx_desc->buf_phys_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) page_pool_put_full_page(rxq->page_pool, page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) &size, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) } /* Middle or Last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (!(rx_status & MVNETA_RXD_LAST_DESC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* no last descriptor this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (xdp_prog &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) skb = mvneta_swbm_build_skb(pp, rxq, &xdp_buf, desc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) stats->es.skb_alloc_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) stats->rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ps.rx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ps.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) xdp_buf.data_hard_start = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (xdp_buf.data_hard_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (ps.xdp_redirect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) xdp_do_flush_map();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) if (ps.rx_packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) mvneta_update_stats(pp, &ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* return some buffers to hardware queue, one at a time is too slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) refill = mvneta_rx_refill_queue(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* Update rxq management counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) return ps.rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* Main rx processing when using hardware buffer management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static int mvneta_rx_hwbm(struct napi_struct *napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) struct mvneta_port *pp, int rx_todo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct net_device *dev = pp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) int rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) u32 rcvd_pkts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) u32 rcvd_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) /* Get number of received packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (rx_todo > rx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) rx_todo = rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) rx_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) /* Fairness NAPI loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) while (rx_done < rx_todo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) struct mvneta_bm_pool *bm_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) unsigned char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) u32 rx_status, frag_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) int rx_bytes, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) u8 pool_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) rx_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) rx_status = rx_desc->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) phys_addr = rx_desc->buf_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) bm_pool = &pp->bm_priv->bm_pools[pool_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (!mvneta_rxq_desc_is_first_last(rx_status) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) err_drop_frame_ret_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) /* Return the buffer to the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) rx_desc->buf_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) err_drop_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) mvneta_rx_error(pp, rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* leave the descriptor untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (rx_bytes <= rx_copybreak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* better copy a small frame and not unmap the DMA region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto err_drop_frame_ret_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) rx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) MVNETA_MH_SIZE + NET_SKB_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) mvneta_rx_csum(pp, rx_status, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) rcvd_pkts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) rcvd_bytes += rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) /* Return the buffer to the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) rx_desc->buf_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) /* leave the descriptor and buffer untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* Refill processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) struct mvneta_pcpu_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) netdev_err(dev, "Linux processing - Can't refill\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) stats->es.refill_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) goto err_drop_frame_ret_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) frag_size = bm_pool->hwbm_pool.frag_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) /* After refill old buffer has to be unmapped regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) * the skb is successfully built or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) bm_pool->buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) goto err_drop_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) rcvd_pkts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) rcvd_bytes += rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* Linux processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) skb_put(skb, rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) mvneta_rx_csum(pp, rx_status, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (rcvd_pkts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) stats->es.ps.rx_packets += rcvd_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) stats->es.ps.rx_bytes += rcvd_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /* Update rxq management counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) return rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) mvneta_tso_put_hdr(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) struct mvneta_port *pp, struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) struct mvneta_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) tx_desc = mvneta_txq_next_desc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) tx_desc->data_size = hdr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) tx_desc->command = mvneta_skb_tx_csum(pp, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) tx_desc->command |= MVNETA_TXD_F_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) txq->txq_put_index * TSO_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) buf->type = MVNETA_TYPE_SKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) buf->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct sk_buff *skb, char *data, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) bool last_tcp, bool is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) struct mvneta_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) tx_desc = mvneta_txq_next_desc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) tx_desc->data_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (unlikely(dma_mapping_error(dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) tx_desc->buf_phys_addr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) tx_desc->command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) buf->type = MVNETA_TYPE_SKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) buf->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (last_tcp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) /* last descriptor in the TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) tx_desc->command = MVNETA_TXD_L_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) /* last descriptor in SKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) buf->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) int hdr_len, total_len, data_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) int desc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct tso_t tso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /* Count needed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if ((txq->count + tso_count_descs(skb)) >= txq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) pr_info("*** Is this even possible???!?!?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* Initialize the TSO handler, and prepare the first payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) hdr_len = tso_start(skb, &tso);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) total_len = skb->len - hdr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) while (total_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) char *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) total_len -= data_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) desc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* prepare packet headers: MAC + IP + TCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) mvneta_tso_put_hdr(skb, pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) while (data_left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) desc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) size = min_t(int, tso.size, data_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (mvneta_tso_put_data(dev, txq, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) tso.data, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) size == data_left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) total_len == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) data_left -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) tso_build_data(skb, &tso, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) return desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* Release all used data descriptors; header descriptors must not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) * be DMA-unmapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) for (i = desc_count - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) struct mvneta_tx_desc *tx_desc = txq->descs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) dma_unmap_single(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) tx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) tx_desc->data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) /* Handle tx fragmentation processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) struct mvneta_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) int i, nr_frags = skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) for (i = 0; i < nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) void *addr = skb_frag_address(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) tx_desc = mvneta_txq_next_desc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) tx_desc->data_size = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) tx_desc->buf_phys_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) dma_map_single(pp->dev->dev.parent, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) tx_desc->data_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (dma_mapping_error(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) tx_desc->buf_phys_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (i == nr_frags - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /* Last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) buf->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* Descriptor in the middle: Not First, Not Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) tx_desc->command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) buf->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) buf->type = MVNETA_TYPE_SKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) /* Release all descriptors that were used to map fragments of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) * this packet, as well as the corresponding DMA mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) for (i = i - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) tx_desc = txq->descs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) dma_unmap_single(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) tx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) tx_desc->data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) /* Main tx processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) u16 txq_id = skb_get_queue_mapping(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) struct mvneta_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) int len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) int frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) u32 tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (skb_is_gso(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) frags = mvneta_tx_tso(skb, dev, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) frags = skb_shinfo(skb)->nr_frags + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) /* Get a descriptor for the first part of the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) tx_desc = mvneta_txq_next_desc_get(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) tx_cmd = mvneta_skb_tx_csum(pp, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) tx_desc->data_size = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) tx_desc->data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) if (unlikely(dma_mapping_error(dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) tx_desc->buf_phys_addr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) buf->type = MVNETA_TYPE_SKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) if (frags == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /* First and Last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) tx_cmd |= MVNETA_TXD_FLZ_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) tx_desc->command = tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) buf->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* First but not Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) tx_cmd |= MVNETA_TXD_F_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) buf->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) mvneta_txq_inc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) tx_desc->command = tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* Continue with other skb fragments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) if (mvneta_tx_frag_process(pp, skb, txq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) dma_unmap_single(dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) tx_desc->buf_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) tx_desc->data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) mvneta_txq_desc_put(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) if (frags > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) netdev_tx_sent_queue(nq, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) txq->count += frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (txq->count >= txq->tx_stop_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) netif_tx_stop_queue(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) if (!netdev_xmit_more() || netif_xmit_stopped(nq) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) mvneta_txq_pend_desc_add(pp, txq, frags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) txq->pending += frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) u64_stats_update_begin(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) stats->es.ps.tx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) stats->es.ps.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) u64_stats_update_end(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /* Free tx resources, when resetting a port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static void mvneta_txq_done_force(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) int tx_done = txq->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) mvneta_txq_bufs_free(pp, txq, tx_done, nq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) /* reset txq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) txq->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) txq->txq_put_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) txq->txq_get_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /* Handle tx done - called in softirq context. The <cause_tx_done> argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) struct mvneta_tx_queue *txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) struct netdev_queue *nq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) while (cause_tx_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) txq = mvneta_tx_done_policy(pp, cause_tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) __netif_tx_lock(nq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) if (txq->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) mvneta_txq_done(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) __netif_tx_unlock(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) cause_tx_done &= ~((1 << txq->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) /* Compute crc8 of the specified address, using a unique algorithm ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) * according to hw spec, different than generic crc8 algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static int mvneta_addr_crc(unsigned char *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) int crc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) for (i = 0; i < ETH_ALEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) crc = (crc ^ addr[i]) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) for (j = 7; j >= 0; j--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (crc & (0x100 << j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) crc ^= 0x107 << j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) /* This method controls the net device special MAC multicast support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) * The Special Multicast Table for MAC addresses supports MAC of the form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) * Table entries in the DA-Filter table. This method set the Special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) * Multicast Table appropriate entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) unsigned char last_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) unsigned int smc_table_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) unsigned int tbl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) /* Register offset from SMC table base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) tbl_offset = (last_byte / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /* Entry offset within the above reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) reg_offset = last_byte % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) + tbl_offset * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) if (queue == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) smc_table_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) smc_table_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) smc_table_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /* This method controls the network device Other MAC multicast support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * The Other Multicast Table is used for multicast of another type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * A CRC-8 is used as an index to the Other Multicast Table entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) * in the DA-Filter table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) * The method gets the CRC-8 value from the calling routine and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) * sets the Other Multicast Table appropriate entry according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) * specified CRC-8 .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) unsigned char crc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) unsigned int omc_table_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) unsigned int tbl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) reg_offset = crc8 % 4; /* Entry offset within the above reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) /* Clear accepts frame bit at specified Other DA table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) omc_table_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) omc_table_reg &= ~(0xff << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) /* The network device supports multicast using two tables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) * 1) Special Multicast Table for MAC addresses of the form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) * Table entries in the DA-Filter table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) * 2) Other Multicast Table for multicast of another type. A CRC-8 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) * is used as an index to the Other Multicast Table entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * DA-Filter table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) unsigned char crc_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) crc_result = mvneta_addr_crc(p_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) if (queue == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) if (pp->mcast_count[crc_result] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) crc_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) pp->mcast_count[crc_result]--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) if (pp->mcast_count[crc_result] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) netdev_info(pp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) "After delete there are %d valid Mcast for crc8=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) pp->mcast_count[crc_result], crc_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) pp->mcast_count[crc_result]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) mvneta_set_other_mcast_addr(pp, crc_result, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) /* Configure Fitering mode of Ethernet port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) int is_promisc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) u32 port_cfg_reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) val = mvreg_read(pp, MVNETA_TYPE_PRIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) /* Set / Clear UPM bit in port configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (is_promisc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) /* Accept all Unicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) val |= MVNETA_FORCE_UNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) /* Reject all Unicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) val &= ~MVNETA_FORCE_UNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) mvreg_write(pp, MVNETA_TYPE_PRIO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) /* register unicast and multicast addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static void mvneta_set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) /* Accept all: Multicast + Unicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) mvneta_rx_unicast_promisc_set(pp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) mvneta_set_ucast_table(pp, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) mvneta_set_special_mcast_table(pp, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) mvneta_set_other_mcast_table(pp, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) /* Accept single Unicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) mvneta_rx_unicast_promisc_set(pp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) mvneta_set_ucast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) /* Accept all multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) mvneta_set_special_mcast_table(pp, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) mvneta_set_other_mcast_table(pp, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) /* Accept only initialized multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) mvneta_set_special_mcast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) mvneta_set_other_mcast_table(pp, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (!netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) mvneta_mcast_addr_set(pp, ha->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) /* Interrupt handling - the callback for request_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static irqreturn_t mvneta_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct mvneta_port *pp = (struct mvneta_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) napi_schedule(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /* Interrupt handling - the callback for request_percpu_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) disable_percpu_irq(port->pp->dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) napi_schedule(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) static void mvneta_link_change(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) /* NAPI handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) * Bits 8 -15 of the cause Rx Tx register indicate that are received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) * Each CPU has its own causeRxTx register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static int mvneta_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) int rx_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) u32 cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) int rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) struct mvneta_port *pp = netdev_priv(napi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (!netif_running(pp->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) napi_complete(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) return rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /* Read cause register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) MVNETA_CAUSE_LINK_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) mvneta_link_change(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /* Release Tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) /* For the case where the last mvneta_poll did not process all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) * RX packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) port->cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) if (rx_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) rx_queue = rx_queue - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) rx_done = mvneta_rx_hwbm(napi, pp, budget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) &pp->rxqs[rx_queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) rx_done = mvneta_rx_swbm(napi, pp, budget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) &pp->rxqs[rx_queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) if (rx_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) cause_rx_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) napi_complete_done(napi, rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) if (pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) mvreg_write(pp, MVNETA_INTR_NEW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) MVNETA_RX_INTR_MASK(rxq_number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) MVNETA_TX_INTR_MASK(txq_number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) MVNETA_MISCINTR_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) enable_percpu_irq(pp->dev->irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) pp->cause_rx_tx = cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) port->cause_rx_tx = cause_rx_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) return rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) static int mvneta_create_page_pool(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) struct mvneta_rx_queue *rxq, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) struct page_pool_params pp_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .order = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .pool_size = size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .nid = NUMA_NO_NODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .dev = pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .offset = pp->rx_offset_correction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .max_len = MVNETA_MAX_RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) rxq->page_pool = page_pool_create(&pp_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) if (IS_ERR(rxq->page_pool)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) err = PTR_ERR(rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) rxq->page_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) goto err_free_pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) goto err_unregister_rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) err_unregister_rxq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) xdp_rxq_info_unreg(&rxq->xdp_rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) err_free_pp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) page_pool_destroy(rxq->page_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) rxq->page_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) err = mvneta_create_page_pool(pp, rxq, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) GFP_KERNEL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) netdev_err(pp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) "%s:rxq %d, %d of %d buffs filled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) __func__, rxq->id, i, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /* Add this number of RX descriptors as non occupied (ready to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) * get packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) mvneta_rxq_non_occup_desc_add(pp, rxq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /* Free all packets pending transmit from all TXQs and reset TX port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) static void mvneta_tx_reset(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) /* free the skb's in the tx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) for (queue = 0; queue < txq_number; queue++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) mvneta_txq_done_force(pp, &pp->txqs[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) static void mvneta_rx_reset(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) /* Rx/Tx queue initialization/cleanup methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) static int mvneta_rxq_sw_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) rxq->size = pp->rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) /* Allocate memory for RX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) rxq->size * MVNETA_DESC_ALIGNED_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) &rxq->descs_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) if (!rxq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) rxq->last_desc = rxq->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) static void mvneta_rxq_hw_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) /* Set Rx descriptors queue starting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) /* Set coalescing pkts and time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) if (!pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) /* Set Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) mvneta_rxq_offset_set(pp, rxq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) MVNETA_MAX_RX_BUF_SIZE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) MVNETA_RX_BUF_SIZE(pp->pkt_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) mvneta_rxq_bm_disable(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) mvneta_rxq_fill(pp, rxq, rxq->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* Set Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) mvneta_rxq_offset_set(pp, rxq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) NET_SKB_PAD - pp->rx_offset_correction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) mvneta_rxq_bm_enable(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) /* Fill RXQ with buffers from RX pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) mvneta_rxq_long_pool_set(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) mvneta_rxq_short_pool_set(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) /* Create a specified RX queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) static int mvneta_rxq_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) ret = mvneta_rxq_sw_init(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) mvneta_rxq_hw_init(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* Cleanup Rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) static void mvneta_rxq_deinit(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) struct mvneta_rx_queue *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) mvneta_rxq_drop_pkts(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) if (rxq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) dma_free_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) rxq->size * MVNETA_DESC_ALIGNED_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) rxq->descs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) rxq->descs_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) rxq->descs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) rxq->last_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) rxq->next_desc_to_proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) rxq->descs_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) rxq->first_to_refill = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) rxq->refill_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) static int mvneta_txq_sw_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) txq->size = pp->tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) /* A queue must always have room for at least one skb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) * Therefore, stop the queue when the free entries reaches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) * the maximum number of descriptors per skb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) /* Allocate memory for TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) txq->size * MVNETA_DESC_ALIGNED_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) &txq->descs_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) if (!txq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) txq->last_desc = txq->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) if (!txq->buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) txq->size * TSO_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) &txq->tso_hdrs_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) if (!txq->tso_hdrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) /* Setup XPS mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) else if (txq_number > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) cpu = txq->id % num_present_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) cpu = pp->rxq_def % num_present_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) cpumask_set_cpu(cpu, &txq->affinity_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) static void mvneta_txq_hw_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) /* Set maximum bandwidth for enabled TXQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) /* Set Tx descriptors queue starting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) /* Create and initialize a tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) static int mvneta_txq_init(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ret = mvneta_txq_sw_init(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) mvneta_txq_hw_init(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) kfree(txq->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) if (txq->tso_hdrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) dma_free_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) txq->size * TSO_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) txq->tso_hdrs, txq->tso_hdrs_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) if (txq->descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) dma_free_coherent(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) txq->size * MVNETA_DESC_ALIGNED_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) txq->descs, txq->descs_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) netdev_tx_reset_queue(nq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) txq->descs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) txq->last_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) txq->next_desc_to_proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) txq->descs_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) /* Set minimum bandwidth for disabled TXQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) /* Set Tx descriptors queue starting address and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) static void mvneta_txq_deinit(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) struct mvneta_tx_queue *txq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) mvneta_txq_sw_deinit(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) mvneta_txq_hw_deinit(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* Cleanup all Tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) static void mvneta_cleanup_txqs(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) for (queue = 0; queue < txq_number; queue++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) mvneta_txq_deinit(pp, &pp->txqs[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) /* Cleanup all Rx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) for (queue = 0; queue < rxq_number; queue++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) /* Init all Rx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static int mvneta_setup_rxqs(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) netdev_err(pp->dev, "%s: can't create rxq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) __func__, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) mvneta_cleanup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) /* Init all tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) static int mvneta_setup_txqs(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) int err = mvneta_txq_init(pp, &pp->txqs[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) netdev_err(pp->dev, "%s: can't create txq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) __func__, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) mvneta_cleanup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) return phy_power_on(pp->comphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) static int mvneta_config_interface(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) if (pp->comphy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) if (interface == PHY_INTERFACE_MODE_SGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) interface == PHY_INTERFACE_MODE_1000BASEX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) interface == PHY_INTERFACE_MODE_2500BASEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) ret = mvneta_comphy_init(pp, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) switch (interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) case PHY_INTERFACE_MODE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) mvreg_write(pp, MVNETA_SERDES_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) MVNETA_QSGMII_SERDES_PROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) case PHY_INTERFACE_MODE_1000BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) mvreg_write(pp, MVNETA_SERDES_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) MVNETA_SGMII_SERDES_PROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) mvreg_write(pp, MVNETA_SERDES_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) MVNETA_HSGMII_SERDES_PROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) pp->phy_interface = interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static void mvneta_start_dev(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) WARN_ON(mvneta_config_interface(pp, pp->phy_interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) mvneta_max_rx_size_set(pp, pp->pkt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) /* start the Rx/Tx activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) mvneta_port_enable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) /* Enable polling on the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) struct mvneta_pcpu_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) napi_enable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) napi_enable(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) /* Unmask interrupts. It has to be done from each CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) mvreg_write(pp, MVNETA_INTR_MISC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) MVNETA_CAUSE_PHY_STATUS_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) MVNETA_CAUSE_LINK_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) phylink_start(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) /* We may have called phylink_speed_down before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) phylink_speed_up(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) netif_tx_start_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) clear_bit(__MVNETA_DOWN, &pp->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) static void mvneta_stop_dev(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) set_bit(__MVNETA_DOWN, &pp->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) if (device_may_wakeup(&pp->dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) phylink_speed_down(pp->phylink, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) phylink_stop(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) struct mvneta_pcpu_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) napi_disable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) napi_disable(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) netif_carrier_off(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) mvneta_port_down(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) netif_tx_stop_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) /* Stop the port activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) mvneta_port_disable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) /* Clear all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) /* Mask all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) mvneta_tx_reset(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) mvneta_rx_reset(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) WARN_ON(phy_power_off(pp->comphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) static void mvneta_percpu_enable(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) struct mvneta_port *pp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) static void mvneta_percpu_disable(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) struct mvneta_port *pp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) disable_percpu_irq(pp->dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) /* Change the device mtu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) static int mvneta_change_mtu(struct net_device *dev, int mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) dev->mtu = mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) if (!netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) if (pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) mvneta_bm_update_mtu(pp, mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) netdev_update_features(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) /* The interface is running, so we have to force a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) * reallocation of the queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) mvneta_stop_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) on_each_cpu(mvneta_percpu_disable, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) mvneta_cleanup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) mvneta_cleanup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) if (pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) mvneta_bm_update_mtu(pp, mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) ret = mvneta_setup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) netdev_err(dev, "unable to setup rxqs after MTU change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) ret = mvneta_setup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) netdev_err(dev, "unable to setup txqs after MTU change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) on_each_cpu(mvneta_percpu_enable, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) mvneta_start_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) netdev_update_features(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) static netdev_features_t mvneta_fix_features(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) netdev_features_t features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) netdev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) "Disable IP checksum for MTU greater than %dB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) pp->tx_csum_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) return features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) /* Get mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) u32 mac_addr_l, mac_addr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) addr[0] = (mac_addr_h >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) addr[1] = (mac_addr_h >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) addr[2] = (mac_addr_h >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) addr[3] = mac_addr_h & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) addr[4] = (mac_addr_l >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) addr[5] = mac_addr_l & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) /* Handle setting mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) struct sockaddr *sockaddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) ret = eth_prepare_mac_addr_change(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) /* Remove previous address table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) mvneta_mac_addr_set(pp, dev->dev_addr, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) /* Set new addr in hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) eth_commit_mac_addr_change(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) static void mvneta_validate(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) unsigned long *supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) if (state->interface != PHY_INTERFACE_MODE_NA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) state->interface != PHY_INTERFACE_MODE_QSGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) state->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) !phy_interface_mode_is_8023z(state->interface) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) !phy_interface_mode_is_rgmii(state->interface)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) /* Allow all the expected bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) phylink_set(mask, Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) phylink_set_port_modes(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) /* Asymmetric pause is unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) phylink_set(mask, Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) /* Half-duplex at speeds higher than 100Mbit is unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) phylink_set(mask, 1000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) phylink_set(mask, 1000baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) phylink_set(mask, 2500baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) phylink_set(mask, 2500baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) if (!phy_interface_mode_is_8023z(state->interface)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) /* 10M and 100M are only supported in non-802.3z mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) phylink_set(mask, 10baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) phylink_set(mask, 10baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) phylink_set(mask, 100baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) phylink_set(mask, 100baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) bitmap_and(supported, supported, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) bitmap_and(state->advertising, state->advertising, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) /* We can only operate at 2500BaseX or 1000BaseX. If requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) * to advertise both, only report advertising at 2500BaseX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) phylink_helper_basex_speed(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) static void mvneta_mac_pcs_get_state(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) u32 gmac_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) if (gmac_stat & MVNETA_GMAC_SPEED_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) state->speed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) state->interface == PHY_INTERFACE_MODE_2500BASEX ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) SPEED_2500 : SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) else if (gmac_stat & MVNETA_GMAC_SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) state->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) state->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) state->pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) state->pause |= MLO_PAUSE_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) state->pause |= MLO_PAUSE_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) static void mvneta_mac_an_restart(struct phylink_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) MVNETA_GMAC2_PORT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) MVNETA_GMAC_INBAND_RESTART_AN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) MVNETA_GMAC_AN_SPEED_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) MVNETA_GMAC_AN_FLOW_CTRL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) MVNETA_GMAC_AN_DUPLEX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) /* Even though it might look weird, when we're configured in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) * SGMII or QSGMII mode, the RGMII bit needs to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) state->interface == PHY_INTERFACE_MODE_SGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) phy_interface_mode_is_8023z(state->interface))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) if (phylink_test(state->advertising, Pause))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) if (!phylink_autoneg_inband(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) /* Phy or fixed speed - nothing to do, leave the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) * configured speed, duplex and flow control as-is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) /* SGMII mode receives the state from the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) MVNETA_GMAC_FORCE_LINK_PASS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) MVNETA_GMAC_CONFIG_MII_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) MVNETA_GMAC_CONFIG_GMII_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) MVNETA_GMAC_CONFIG_FULL_DUPLEX)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) MVNETA_GMAC_INBAND_AN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) MVNETA_GMAC_AN_SPEED_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) MVNETA_GMAC_AN_DUPLEX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) /* 802.3z negotiation - only 1000base-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) MVNETA_GMAC_FORCE_LINK_PASS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) MVNETA_GMAC_CONFIG_MII_SPEED)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) MVNETA_GMAC_INBAND_AN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) MVNETA_GMAC_CONFIG_GMII_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) /* The MAC only supports FD mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) MVNETA_GMAC_CONFIG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) if (state->pause & MLO_PAUSE_AN && state->an_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) /* Armada 370 documentation says we can only change the port mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) * and in-band enable when the link is down, so force it down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) * while making these changes. We also do this for GMAC_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) MVNETA_GMAC_FORCE_LINK_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) /* When at 2.5G, the link partner can send frames with shortened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) * preambles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) if (pp->phy_interface != state->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) if (pp->comphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) WARN_ON(phy_power_off(pp->comphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) WARN_ON(mvneta_config_interface(pp, state->interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) if (new_ctrl0 != gmac_ctrl0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) if (new_ctrl2 != gmac_ctrl2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) if (new_ctrl4 != gmac_ctrl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) if (new_clk != gmac_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) if (new_an != gmac_an)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) MVNETA_GMAC2_PORT_RESET) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) u32 lpi_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) static void mvneta_mac_link_down(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) unsigned int mode, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) mvneta_port_down(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) if (!phylink_autoneg_inband(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) val |= MVNETA_GMAC_FORCE_LINK_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) pp->eee_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) mvneta_set_eee(pp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) static void mvneta_mac_link_up(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) struct phy_device *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) unsigned int mode, phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) int speed, int duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) bool tx_pause, bool rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) struct net_device *ndev = to_net_dev(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) if (!phylink_autoneg_inband(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) MVNETA_GMAC_CONFIG_MII_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) MVNETA_GMAC_CONFIG_GMII_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) MVNETA_GMAC_CONFIG_FLOW_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) MVNETA_GMAC_CONFIG_FULL_DUPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) val |= MVNETA_GMAC_FORCE_LINK_PASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) if (speed == SPEED_1000 || speed == SPEED_2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) else if (speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) val |= MVNETA_GMAC_CONFIG_MII_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) if (duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) if (tx_pause || rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) /* When inband doesn't cover flow control or flow control is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) * disabled, we need to manually configure it. This bit will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) if (tx_pause || rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) mvneta_port_up(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) if (phy && pp->eee_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) pp->eee_active = phy_init_eee(phy, 0) >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) static const struct phylink_mac_ops mvneta_phylink_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) .validate = mvneta_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) .mac_pcs_get_state = mvneta_mac_pcs_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) .mac_an_restart = mvneta_mac_an_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) .mac_config = mvneta_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) .mac_link_down = mvneta_mac_link_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) .mac_link_up = mvneta_mac_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) static int mvneta_mdio_probe(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) netdev_err(pp->dev, "could not attach PHY: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) phylink_ethtool_get_wol(pp->phylink, &wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) /* PHY WoL may be enabled but device wakeup disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) if (wol.supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) static void mvneta_mdio_remove(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) phylink_disconnect_phy(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) /* Electing a CPU must be done in an atomic way: it should be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) * after or before the removal/insertion of a CPU and this function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) * not reentrant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static void mvneta_percpu_elect(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) int elected_cpu = 0, max_cpu, cpu, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) /* Use the cpu associated to the rxq when it is online, in all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) * the other cases, use the cpu 0 which can't be offline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) if (cpu_online(pp->rxq_def))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) elected_cpu = pp->rxq_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) max_cpu = num_present_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) int rxq_map = 0, txq_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) int rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) for (rxq = 0; rxq < rxq_number; rxq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) if ((rxq % max_cpu) == cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) if (cpu == elected_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) /* Map the default receive queue queue to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) * elected CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) /* We update the TX queue map only if we have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) * queue. In this case we associate the TX queue to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) * the CPU bound to the default RX queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) if (txq_number == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) txq_map = (cpu == elected_cpu) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) MVNETA_CPU_TXQ_ACCESS(1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) /* Update the interrupt mask on each CPU according the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) * new mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) int other_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) * are routed to CPU 0, so we don't need all the cpu-hotplug support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) * Configuring the driver for a new CPU while the driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) * stopping is racy, so just avoid it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) if (pp->is_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) netif_tx_stop_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) * We have to synchronise on tha napi of each CPU except the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) * just being woken up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) for_each_online_cpu(other_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) if (other_cpu != cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) struct mvneta_pcpu_port *other_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) per_cpu_ptr(pp->ports, other_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) napi_synchronize(&other_port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) /* Mask all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) napi_enable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * Enable per-CPU interrupts on the CPU that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) * brought up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) mvneta_percpu_enable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) * Enable per-CPU interrupt on the one CPU we care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) * about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) mvneta_percpu_elect(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) /* Unmask all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) mvreg_write(pp, MVNETA_INTR_MISC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) MVNETA_CAUSE_PHY_STATUS_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) MVNETA_CAUSE_LINK_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) netif_tx_start_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) * Thanks to this lock we are sure that any pending cpu election is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) * done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) /* Mask all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) napi_synchronize(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) napi_disable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) /* Disable per-CPU interrupts on the CPU that is brought down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) mvneta_percpu_disable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) /* Check if a new CPU must be elected now this on is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) mvneta_percpu_elect(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) /* Unmask all ethernet port interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) mvreg_write(pp, MVNETA_INTR_MISC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) MVNETA_CAUSE_PHY_STATUS_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) MVNETA_CAUSE_LINK_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) netif_tx_start_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) static int mvneta_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) ret = mvneta_setup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) ret = mvneta_setup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) goto err_cleanup_rxqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) /* Connect to port interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) ret = request_irq(pp->dev->irq, mvneta_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) dev->name, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) dev->name, pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) goto err_cleanup_txqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) /* Enable per-CPU interrupt on all the CPU to handle our RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * queue interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) on_each_cpu(mvneta_percpu_enable, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) pp->is_stopped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) /* Register a CPU notifier to handle the case where our CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) * might be taken offline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) ret = cpuhp_state_add_instance_nocalls(online_hpstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) &pp->node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) &pp->node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) goto err_free_online_hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ret = mvneta_mdio_probe(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) netdev_err(dev, "cannot probe MDIO bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) goto err_free_dead_hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) mvneta_start_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) err_free_dead_hp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) if (!pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) &pp->node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) err_free_online_hp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) if (!pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) cpuhp_state_remove_instance_nocalls(online_hpstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) &pp->node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) if (pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) free_irq(pp->dev->irq, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) on_each_cpu(mvneta_percpu_disable, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) free_percpu_irq(pp->dev->irq, pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) err_cleanup_txqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) mvneta_cleanup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) err_cleanup_rxqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) mvneta_cleanup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) /* Stop the port, free port interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) static int mvneta_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) /* Inform that we are stopping so we don't want to setup the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) * driver for new CPUs in the notifiers. The code of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) * notifier for CPU online is protected by the same spinlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) * so when we get the lock, the notifer work is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) pp->is_stopped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) mvneta_stop_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) mvneta_mdio_remove(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) cpuhp_state_remove_instance_nocalls(online_hpstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) &pp->node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) &pp->node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) on_each_cpu(mvneta_percpu_disable, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) free_percpu_irq(dev->irq, pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) mvneta_stop_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) mvneta_mdio_remove(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) free_irq(dev->irq, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) mvneta_cleanup_rxqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) mvneta_cleanup_txqs(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) return phylink_mii_ioctl(pp->phylink, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) struct netlink_ext_ack *extack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) bool need_update, running = netif_running(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) struct bpf_prog *old_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) NL_SET_ERR_MSG_MOD(extack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) "Hardware Buffer Management not supported on XDP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) need_update = !!pp->xdp_prog != !!prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) if (running && need_update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) mvneta_stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) old_prog = xchg(&pp->xdp_prog, prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) if (old_prog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) bpf_prog_put(old_prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) if (running && need_update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) return mvneta_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) switch (xdp->command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) case XDP_SETUP_PROG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) return mvneta_xdp_setup(dev, xdp->prog, xdp->extack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) /* Ethtool methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) /* Set link ksettings (phy address, speed) for ethtools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) return phylink_ethtool_ksettings_set(pp->phylink, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) /* Get link ksettings for ethtools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) struct mvneta_port *pp = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) return phylink_ethtool_ksettings_get(pp->phylink, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) static int mvneta_ethtool_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) return phylink_ethtool_nway_reset(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) /* Set interrupt coalescing for ethtools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) static int mvneta_ethtool_set_coalesce(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) struct ethtool_coalesce *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) rxq->time_coal = c->rx_coalesce_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) rxq->pkts_coal = c->rx_max_coalesced_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) struct mvneta_tx_queue *txq = &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) txq->done_pkts_coal = c->tx_max_coalesced_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) /* get coalescing for ethtools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) static int mvneta_ethtool_get_coalesce(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) struct ethtool_coalesce *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) struct ethtool_drvinfo *drvinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) sizeof(drvinfo->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) sizeof(drvinfo->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) sizeof(drvinfo->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) struct mvneta_port *pp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) ring->rx_max_pending = MVNETA_MAX_RXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) ring->tx_max_pending = MVNETA_MAX_TXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) ring->rx_pending = pp->rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) ring->tx_pending = pp->tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) static int mvneta_ethtool_set_ringparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) ring->rx_pending : MVNETA_MAX_RXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) if (pp->tx_ring_size != ring->tx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) pp->tx_ring_size, ring->tx_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) mvneta_stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) if (mvneta_open(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) netdev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) "error on opening device after ring param change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) struct ethtool_pauseparam *pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) phylink_ethtool_get_pauseparam(pp->phylink, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) struct ethtool_pauseparam *pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) return phylink_ethtool_set_pauseparam(pp->phylink, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) if (sset == ETH_SS_STATS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) memcpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) mvneta_statistics[i].name, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) struct mvneta_ethtool_stats *es)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) struct mvneta_pcpu_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) u64 skb_alloc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) u64 refill_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) u64 xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) u64 xdp_xmit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) u64 xdp_tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) u64 xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) u64 xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) u64 xdp_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) u64 xdp_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) stats = per_cpu_ptr(pp->stats, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) start = u64_stats_fetch_begin_irq(&stats->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) skb_alloc_error = stats->es.skb_alloc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) refill_error = stats->es.refill_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) xdp_redirect = stats->es.ps.xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) xdp_pass = stats->es.ps.xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) xdp_drop = stats->es.ps.xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) xdp_xmit = stats->es.ps.xdp_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) xdp_xmit_err = stats->es.ps.xdp_xmit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) xdp_tx = stats->es.ps.xdp_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) xdp_tx_err = stats->es.ps.xdp_tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) es->skb_alloc_error += skb_alloc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) es->refill_error += refill_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) es->ps.xdp_redirect += xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) es->ps.xdp_pass += xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) es->ps.xdp_drop += xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) es->ps.xdp_xmit += xdp_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) es->ps.xdp_xmit_err += xdp_xmit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) es->ps.xdp_tx += xdp_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) es->ps.xdp_tx_err += xdp_tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) struct mvneta_ethtool_stats stats = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) const struct mvneta_statistic *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) void __iomem *base = pp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) u32 high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) mvneta_ethtool_update_pcpu_stats(pp, &stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) for (i = 0, s = mvneta_statistics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) s++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) switch (s->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) case T_REG_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) val = readl_relaxed(base + s->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) pp->ethtool_stats[i] += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) case T_REG_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) /* Docs say to read low 32-bit then high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) low = readl_relaxed(base + s->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) high = readl_relaxed(base + s->offset + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) val = (u64)high << 32 | low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) pp->ethtool_stats[i] += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) case T_SW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) switch (s->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) case ETHTOOL_STAT_EEE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) val = phylink_get_eee_err(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) pp->ethtool_stats[i] += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) case ETHTOOL_STAT_SKB_ALLOC_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) pp->ethtool_stats[i] = stats.skb_alloc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) case ETHTOOL_STAT_REFILL_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) pp->ethtool_stats[i] = stats.refill_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) case ETHTOOL_XDP_REDIRECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) pp->ethtool_stats[i] = stats.ps.xdp_redirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) case ETHTOOL_XDP_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) pp->ethtool_stats[i] = stats.ps.xdp_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) case ETHTOOL_XDP_DROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) pp->ethtool_stats[i] = stats.ps.xdp_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) case ETHTOOL_XDP_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) pp->ethtool_stats[i] = stats.ps.xdp_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) case ETHTOOL_XDP_TX_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) pp->ethtool_stats[i] = stats.ps.xdp_tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) case ETHTOOL_XDP_XMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) pp->ethtool_stats[i] = stats.ps.xdp_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) case ETHTOOL_XDP_XMIT_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) pp->ethtool_stats[i] = stats.ps.xdp_xmit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) static void mvneta_ethtool_get_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) mvneta_ethtool_update_stats(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) *data++ = pp->ethtool_stats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) if (sset == ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) return ARRAY_SIZE(mvneta_statistics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) return MVNETA_RSS_LU_TABLE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) struct ethtool_rxnfc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) u32 *rules __always_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) switch (info->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) case ETHTOOL_GRXRINGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) info->data = rxq_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) case ETHTOOL_GRXFH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) static int mvneta_config_rss(struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) netif_tx_stop_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) /* We have to synchronise on the napi of each CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) struct mvneta_pcpu_port *pcpu_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) napi_synchronize(&pcpu_port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) napi_disable(&pcpu_port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) napi_synchronize(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) napi_disable(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) pp->rxq_def = pp->indir[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) /* Update unicast mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) mvneta_set_rx_mode(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) /* Update val of portCfg register accordingly with all RxQueue types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) mvreg_write(pp, MVNETA_PORT_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) /* Update the elected CPU matching the new rxq_def */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) mvneta_percpu_elect(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) /* We have to synchronise on the napi of each CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) struct mvneta_pcpu_port *pcpu_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) napi_enable(&pcpu_port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) napi_enable(&pp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) netif_tx_start_all_queues(pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) const u8 *key, const u8 hfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) /* Current code for Armada 3700 doesn't support RSS features yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) /* We require at least one supported parameter to be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) * and no change in any of the unsupported parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) if (key ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) if (!indir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) return mvneta_config_rss(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) u8 *hfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) /* Current code for Armada 3700 doesn't support RSS features yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) if (pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) if (hfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) *hfunc = ETH_RSS_HASH_TOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) if (!indir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) static void mvneta_ethtool_get_wol(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) phylink_ethtool_get_wol(pp->phylink, wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) static int mvneta_ethtool_set_wol(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) ret = phylink_ethtool_set_wol(pp->phylink, wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) static int mvneta_ethtool_get_eee(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) struct ethtool_eee *eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) u32 lpi_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) eee->eee_enabled = pp->eee_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) eee->eee_active = pp->eee_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) eee->tx_lpi_enabled = pp->tx_lpi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) return phylink_ethtool_get_eee(pp->phylink, eee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) static int mvneta_ethtool_set_eee(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) struct ethtool_eee *eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) u32 lpi_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) /* The Armada 37x documents do not give limits for this other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) * it being an 8-bit register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) lpi_ctl0 &= ~(0xff << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) lpi_ctl0 |= eee->tx_lpi_timer << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) pp->eee_enabled = eee->eee_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) pp->tx_lpi_enabled = eee->tx_lpi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) return phylink_ethtool_set_eee(pp->phylink, eee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) static const struct net_device_ops mvneta_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) .ndo_open = mvneta_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) .ndo_stop = mvneta_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) .ndo_start_xmit = mvneta_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) .ndo_set_rx_mode = mvneta_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) .ndo_set_mac_address = mvneta_set_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) .ndo_change_mtu = mvneta_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) .ndo_fix_features = mvneta_fix_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) .ndo_get_stats64 = mvneta_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) .ndo_do_ioctl = mvneta_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) .ndo_bpf = mvneta_xdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) .ndo_xdp_xmit = mvneta_xdp_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) static const struct ethtool_ops mvneta_eth_tool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) ETHTOOL_COALESCE_MAX_FRAMES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) .nway_reset = mvneta_ethtool_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) .set_coalesce = mvneta_ethtool_set_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) .get_coalesce = mvneta_ethtool_get_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) .get_drvinfo = mvneta_ethtool_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) .get_ringparam = mvneta_ethtool_get_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) .set_ringparam = mvneta_ethtool_set_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) .get_pauseparam = mvneta_ethtool_get_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) .set_pauseparam = mvneta_ethtool_set_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) .get_strings = mvneta_ethtool_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) .get_ethtool_stats = mvneta_ethtool_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) .get_sset_count = mvneta_ethtool_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) .get_rxnfc = mvneta_ethtool_get_rxnfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) .get_rxfh = mvneta_ethtool_get_rxfh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) .set_rxfh = mvneta_ethtool_set_rxfh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) .get_wol = mvneta_ethtool_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) .set_wol = mvneta_ethtool_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) .get_eee = mvneta_ethtool_get_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) .set_eee = mvneta_ethtool_set_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) /* Initialize hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) static int mvneta_init(struct device *dev, struct mvneta_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) /* Disable port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) mvneta_port_disable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) /* Set port default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) mvneta_defaults_set(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) if (!pp->txqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) /* Initialize TX descriptor rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) struct mvneta_tx_queue *txq = &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) txq->id = queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) txq->size = pp->tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) if (!pp->rxqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) /* Create Rx descriptor rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) rxq->id = queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) rxq->size = pp->rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) rxq->time_coal = MVNETA_RX_COAL_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) rxq->buf_virt_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) = devm_kmalloc_array(pp->dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) rxq->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) sizeof(*rxq->buf_virt_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) if (!rxq->buf_virt_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) /* platform glue : initialize decoding windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) const struct mbus_dram_target_info *dram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) u32 win_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) u32 win_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) if (i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) win_enable = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) win_protect = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) if (dram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) mvreg_write(pp, MVNETA_WIN_BASE(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) (cs->base & 0xffff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) (cs->mbus_attr << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) dram->mbus_dram_target_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) mvreg_write(pp, MVNETA_WIN_SIZE(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) (cs->size - 1) & 0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) win_enable &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) win_protect |= 3 << (2 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) /* For Armada3700 open default 4GB Mbus window, leaving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) * arbitration of target/attribute to a different layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) * of configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) win_enable &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) win_protect = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) /* Power up the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) /* MAC Cause register should be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) if (phy_mode != PHY_INTERFACE_MODE_QSGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) phy_mode != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) !phy_interface_mode_is_8023z(phy_mode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) !phy_interface_mode_is_rgmii(phy_mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) /* Device initialization routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) static int mvneta_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) struct device_node *bm_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) struct mvneta_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) struct phylink *phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) struct phy *comphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) const char *dt_mac_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) char hw_mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) phy_interface_t phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) const char *mac_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) int tx_csum_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) txq_number, rxq_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) dev->irq = irq_of_parse_and_map(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) if (dev->irq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) err = of_get_phy_mode(dn, &phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) dev_err(&pdev->dev, "incorrect phy-mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) if (comphy == ERR_PTR(-EPROBE_DEFER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) err = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) } else if (IS_ERR(comphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) comphy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) spin_lock_init(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) pp->phylink_config.dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) pp->phylink_config.type = PHYLINK_NETDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) phy_mode, &mvneta_phylink_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) if (IS_ERR(phylink)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) err = PTR_ERR(phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) dev->tx_queue_len = MVNETA_MAX_TXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) dev->watchdog_timeo = 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) dev->netdev_ops = &mvneta_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) dev->ethtool_ops = &mvneta_eth_tool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) pp->phylink = phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) pp->comphy = comphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) pp->phy_interface = phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) pp->dn = dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) pp->rxq_def = rxq_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) pp->indir[0] = rxq_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) /* Get special SoC configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) pp->neta_armada3700 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) pp->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) if (IS_ERR(pp->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) pp->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) if (IS_ERR(pp->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) err = PTR_ERR(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) goto err_free_phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) clk_prepare_enable(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) if (!IS_ERR(pp->clk_bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) clk_prepare_enable(pp->clk_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) pp->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) if (IS_ERR(pp->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) err = PTR_ERR(pp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) /* Alloc per-cpu port structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) pp->ports = alloc_percpu(struct mvneta_pcpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) if (!pp->ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) /* Alloc per-cpu stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) if (!pp->stats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) goto err_free_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) dt_mac_addr = of_get_mac_address(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) if (!IS_ERR(dt_mac_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) mac_from = "device tree";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) ether_addr_copy(dev->dev_addr, dt_mac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) mvneta_get_mac_addr(pp, hw_mac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) if (is_valid_ether_addr(hw_mac_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) mac_from = "hardware";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) mac_from = "random";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) if (tx_csum_limit < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) "Wrong TX csum limit in DT, set to %dB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) MVNETA_TX_CSUM_DEF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) pp->tx_csum_limit = tx_csum_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) pp->dram_target_info = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) /* Armada3700 requires setting default configuration of Mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) * windows, however without using filled mbus_dram_target_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) if (pp->dram_target_info || pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) mvneta_conf_mbus_windows(pp, pp->dram_target_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) pp->tx_ring_size = MVNETA_MAX_TXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) pp->rx_ring_size = MVNETA_MAX_RXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) pp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) pp->id = global_port_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) /* Obtain access to BM resources if enabled and already initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) bm_node = of_parse_phandle(dn, "buffer-manager", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) if (bm_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) pp->bm_priv = mvneta_bm_get(bm_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) err = mvneta_bm_port_init(pdev, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) "use SW buffer management\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) mvneta_bm_put(pp->bm_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) pp->bm_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) /* Set RX packet offset correction for platforms, whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) * platforms and 0B for 32-bit ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) pp->rx_offset_correction = max(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) NET_SKB_PAD -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) MVNETA_RX_PKT_OFFSET_CORRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) of_node_put(bm_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) /* sw buffer management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) if (!pp->bm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) err = mvneta_init(&pdev->dev, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) goto err_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) err = mvneta_port_power_up(pp, pp->phy_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) dev_err(&pdev->dev, "can't power up port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) goto err_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) /* Armada3700 network controller does not support per-cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) * operation, so only single NAPI should be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) if (pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) for_each_present_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) struct mvneta_pcpu_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) per_cpu_ptr(pp->ports, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) netif_napi_add(dev, &port->napi, mvneta_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) NAPI_POLL_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) port->pp = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) NETIF_F_TSO | NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) dev->hw_features |= dev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) dev->vlan_features |= dev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) /* MTU range: 68 - 9676 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) dev->min_mtu = ETH_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) /* 9676 == 9700 - 20 and rounding to 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) dev->max_mtu = 9676;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) dev_err(&pdev->dev, "failed to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) goto err_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) netdev_info(dev, "Using %s mac address %pM\n", mac_from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) platform_set_drvdata(pdev, pp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) err_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) mvneta_bm_put(pp->bm_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) free_percpu(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) err_free_ports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) free_percpu(pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) clk_disable_unprepare(pp->clk_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) clk_disable_unprepare(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) err_free_phylink:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) if (pp->phylink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) phylink_destroy(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) irq_dispose_mapping(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) /* Device removal routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) static int mvneta_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) clk_disable_unprepare(pp->clk_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) clk_disable_unprepare(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) free_percpu(pp->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) free_percpu(pp->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) irq_dispose_mapping(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) phylink_destroy(pp->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) 1 << pp->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) mvneta_bm_put(pp->bm_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) static int mvneta_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) int queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) goto clean_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) pp->is_stopped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) cpuhp_state_remove_instance_nocalls(online_hpstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) &pp->node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) &pp->node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) mvneta_stop_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) mvneta_rxq_drop_pkts(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) struct mvneta_tx_queue *txq = &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) mvneta_txq_hw_deinit(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) clean_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) clk_disable_unprepare(pp->clk_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) clk_disable_unprepare(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) static int mvneta_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) struct platform_device *pdev = to_platform_device(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) struct mvneta_port *pp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) int err, queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) clk_prepare_enable(pp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) if (!IS_ERR(pp->clk_bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) clk_prepare_enable(pp->clk_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (pp->dram_target_info || pp->neta_armada3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) mvneta_conf_mbus_windows(pp, pp->dram_target_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) if (pp->bm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) err = mvneta_bm_port_init(pdev, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) dev_info(&pdev->dev, "use SW buffer management\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) pp->bm_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) mvneta_defaults_set(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) err = mvneta_port_power_up(pp, pp->phy_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) dev_err(device, "can't power up port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) for (queue = 0; queue < rxq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) rxq->next_desc_to_proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) mvneta_rxq_hw_init(pp, rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) for (queue = 0; queue < txq_number; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) struct mvneta_tx_queue *txq = &pp->txqs[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) txq->next_desc_to_proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) mvneta_txq_hw_init(pp, txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) if (!pp->neta_armada3700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) spin_lock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) pp->is_stopped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) spin_unlock(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) cpuhp_state_add_instance_nocalls(online_hpstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) &pp->node_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) &pp->node_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) mvneta_start_dev(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) mvneta_set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) static const struct of_device_id mvneta_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) { .compatible = "marvell,armada-370-neta" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) { .compatible = "marvell,armada-xp-neta" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) { .compatible = "marvell,armada-3700-neta" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) MODULE_DEVICE_TABLE(of, mvneta_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) static struct platform_driver mvneta_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) .probe = mvneta_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) .remove = mvneta_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) .name = MVNETA_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) .of_match_table = mvneta_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) .pm = &mvneta_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) static int __init mvneta_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) mvneta_cpu_online,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) mvneta_cpu_down_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) online_hpstate = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) NULL, mvneta_cpu_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) goto err_dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) ret = platform_driver_register(&mvneta_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) err_dead:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) cpuhp_remove_multi_state(online_hpstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) module_init(mvneta_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) static void __exit mvneta_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) platform_driver_unregister(&mvneta_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) cpuhp_remove_multi_state(online_hpstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) module_exit(mvneta_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) module_param(rxq_number, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) module_param(txq_number, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) module_param(rxq_def, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) module_param(rx_copybreak, int, 0644);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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