^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the MDIO interface of Marvell network interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Since the MDIO interface of Marvell network interfaces is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * between all network interfaces, having a single driver allows to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * handle concurrent accesses properly (you may have four Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ports, but they in fact share the same SMI interface to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the MDIO bus). This driver is currently used by the mvneta and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * mv643xx_eth drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MVMDIO_SMI_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MVMDIO_SMI_PHY_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MVMDIO_SMI_PHY_REG_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MVMDIO_SMI_READ_OPERATION BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MVMDIO_SMI_WRITE_OPERATION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MVMDIO_SMI_READ_VALID BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MVMDIO_SMI_BUSY BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MVMDIO_ERR_INT_CAUSE 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MVMDIO_ERR_INT_SMI_DONE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MVMDIO_ERR_INT_MASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MVMDIO_XSMI_MGNT_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MVMDIO_XSMI_PHYADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MVMDIO_XSMI_DEVADDR_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MVMDIO_XSMI_READ_VALID BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MVMDIO_XSMI_BUSY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MVMDIO_XSMI_ADDR_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * SMI Timeout measurements:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MVMDIO_SMI_POLL_INTERVAL_MIN 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MVMDIO_SMI_POLL_INTERVAL_MAX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MVMDIO_XSMI_POLL_INTERVAL_MIN 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MVMDIO_XSMI_POLL_INTERVAL_MAX 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct orion_mdio_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *clk[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * If we have access to the error interrupt pin (which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * somewhat misnamed as it not only reflects internal errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * but also reflects SMI completion), use that to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * SMI access completion instead of polling the SMI busy bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int err_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) wait_queue_head_t smi_busy_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum orion_mdio_bus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) BUS_TYPE_SMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BUS_TYPE_XSMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct orion_mdio_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int (*is_done)(struct orion_mdio_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int poll_interval_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int poll_interval_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Wait for the SMI unit to be ready for another operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long end = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int timedout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ops->is_done(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else if (timedout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (dev->err_interrupt <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) usleep_range(ops->poll_interval_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ops->poll_interval_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (time_is_before_jiffies(end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ++timedout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* wait_event_timeout does not guarantee a delay of at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * least one whole jiffie, so timeout must be no less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * than two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (timeout < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) wait_event_timeout(dev->smi_busy_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ops->is_done(dev), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ++timedout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(bus->parent, "Timeout: SMI busy for too long\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct orion_mdio_ops orion_mdio_smi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .is_done = orion_mdio_smi_is_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (regnum & MII_ADDR_C45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MVMDIO_SMI_READ_OPERATION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = readl(dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!(val & MVMDIO_SMI_READ_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(bus->parent, "SMI bus read not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return val & GENMASK(15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int regnum, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (regnum & MII_ADDR_C45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MVMDIO_SMI_WRITE_OPERATION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) (value << MVMDIO_SMI_DATA_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .is_done = orion_mdio_xsmi_is_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!(regnum & MII_ADDR_C45))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MVMDIO_XSMI_READ_OPERATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev->regs + MVMDIO_XSMI_MGNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MVMDIO_XSMI_READ_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(bus->parent, "XSMI bus read not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int regnum, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!(regnum & MII_ADDR_C45))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MVMDIO_XSMI_WRITE_OPERATION | value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev->regs + MVMDIO_XSMI_MGNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct orion_mdio_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MVMDIO_ERR_INT_SMI_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(~MVMDIO_ERR_INT_SMI_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev->regs + MVMDIO_ERR_INT_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wake_up(&dev->smi_busy_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int orion_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enum orion_mdio_bus_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct orion_mdio_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) type = (enum orion_mdio_bus_type)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(&pdev->dev, "No SMI register address given\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bus = devm_mdiobus_alloc_size(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sizeof(struct orion_mdio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case BUS_TYPE_SMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bus->read = orion_mdio_smi_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bus->write = orion_mdio_smi_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case BUS_TYPE_XSMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bus->read = orion_mdio_xsmi_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bus->write = orion_mdio_xsmi_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bus->name = "orion_mdio_bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!dev->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(&pdev->dev, "Unable to remap SMI register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) init_waitqueue_head(&dev->smi_busy_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (PTR_ERR(dev->clk[i]) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ERR(dev->clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clk_prepare_enable(dev->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!IS_ERR(of_clk_get(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ARRAY_SIZE(dev->clk))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "unsupported number of clocks, limiting to the first "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __stringify(ARRAY_SIZE(dev->clk)) "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev->clk[0] = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (PTR_ERR(dev->clk[0]) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!IS_ERR(dev->clk[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk_prepare_enable(dev->clk[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev->err_interrupt = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (dev->err_interrupt > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "disabling interrupt, resource size is too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev->err_interrupt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (dev->err_interrupt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) orion_mdio_err_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) IRQF_SHARED, pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(MVMDIO_ERR_INT_SMI_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev->regs + MVMDIO_ERR_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else if (dev->err_interrupt == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = of_mdiobus_register(bus, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) out_mdio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (dev->err_interrupt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (IS_ERR(dev->clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clk_disable_unprepare(dev->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_put(dev->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int orion_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct mii_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct orion_mdio_dev *dev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (dev->err_interrupt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mdiobus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(dev->clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk_disable_unprepare(dev->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_put(dev->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct of_device_id orion_mdio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_DEVICE_TABLE(of, orion_mdio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct platform_driver orion_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .probe = orion_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .remove = orion_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "orion-mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .of_match_table = orion_mdio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) module_platform_driver(orion_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_DESCRIPTION("Marvell MDIO interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_ALIAS("platform:orion-mdio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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