Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/tcp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/checksum.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <xway_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <lantiq_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LTQ_ETOP_MDIO		0x11804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MDIO_REQUEST		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MDIO_READ		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MDIO_ADDR_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MDIO_ADDR_OFFSET	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MDIO_REG_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MDIO_REG_OFFSET		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MDIO_VAL_MASK		0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PPE32_CGEN		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LQ_PPE32_ENET_MAC_CFG	0x1840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define LTQ_ETOP_ENETS0		0x11850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LTQ_ETOP_MAC_DA0	0x1186C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LTQ_ETOP_MAC_DA1	0x11870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LTQ_ETOP_CFG		0x16020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LTQ_ETOP_IGPLEN		0x16080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX_DMA_CHAN		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MAX_DMA_CRC_LEN		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MAX_DMA_DATA_LEN	0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ETOP_FTCU		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ETOP_MII_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ETOP_MII_NORMAL		0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ETOP_MII_REVERSE	0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ETOP_PLEN_UNDER		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ETOP_CGEN		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* use 2 static channels for TX/RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define LTQ_ETOP_TX_CHANNEL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define LTQ_ETOP_RX_CHANNEL	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IS_TX(x)		(x == LTQ_ETOP_TX_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IS_RX(x)		(x == LTQ_ETOP_RX_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ltq_etop_w32_mask(x, y, z)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRV_VERSION	"1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void __iomem *ltq_etop_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct ltq_etop_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int tx_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct ltq_dma_channel dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct sk_buff *skb[LTQ_DESC_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) struct ltq_etop_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct ltq_eth_data *pldata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct ltq_etop_chan ch[MAX_DMA_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int tx_free[MAX_DMA_CHAN >> 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!ch->skb[ch->dma.desc])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ch->dma.desc_base[ch->dma.desc].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		CPHYSADDR(ch->skb[ch->dma.desc]->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ch->dma.desc_base[ch->dma.desc].ctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		MAX_DMA_DATA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ltq_etop_hw_receive(struct ltq_etop_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct sk_buff *skb = ch->skb[ch->dma.desc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ltq_etop_alloc_skb(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		netdev_err(ch->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			"failed to allocate new rx buffer, stopping DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ltq_dma_close(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ch->dma.desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ch->dma.desc %= LTQ_DESC_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	skb->protocol = eth_type_trans(skb, ch->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ltq_etop_poll_rx(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct ltq_etop_chan *ch = container_of(napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				struct ltq_etop_chan, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	while (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		ltq_etop_hw_receive(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		work_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		napi_complete_done(&ch->napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		ltq_dma_ack_irq(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ltq_etop_poll_tx(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct ltq_etop_chan *ch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		container_of(napi, struct ltq_etop_chan, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct netdev_queue *txq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	while ((ch->dma.desc_base[ch->tx_free].ctl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_kfree_skb_any(ch->skb[ch->tx_free]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		ch->skb[ch->tx_free] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		memset(&ch->dma.desc_base[ch->tx_free], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			sizeof(struct ltq_dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ch->tx_free++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		ch->tx_free %= LTQ_DESC_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (netif_tx_queue_stopped(txq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		netif_tx_start_queue(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	napi_complete(&ch->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ltq_dma_ack_irq(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ltq_etop_dma_irq(int irq, void *_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct ltq_etop_priv *priv = _priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int ch = irq - LTQ_DMA_CH0_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	napi_schedule(&priv->ch[ch].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ltq_dma_free(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ch->dma.irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		free_irq(ch->dma.irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (IS_RX(ch->idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		int desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			dev_kfree_skb_any(ch->skb[ch->dma.desc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ltq_etop_hw_exit(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ltq_pmu_disable(PMU_PPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	for (i = 0; i < MAX_DMA_CHAN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (IS_TX(i) || IS_RX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			ltq_etop_free_channel(dev, &priv->ch[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ltq_etop_hw_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ltq_pmu_enable(PMU_PPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	switch (priv->pldata->mii_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case PHY_INTERFACE_MODE_RMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		ltq_etop_w32_mask(ETOP_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			ETOP_MII_REVERSE, LTQ_ETOP_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case PHY_INTERFACE_MODE_MII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		ltq_etop_w32_mask(ETOP_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			ETOP_MII_NORMAL, LTQ_ETOP_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		netdev_err(dev, "unknown mii mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			priv->pldata->mii_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* enable crc generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ltq_dma_init_port(DMA_PORT_ETOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	for (i = 0; i < MAX_DMA_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		int irq = LTQ_DMA_CH0_INT + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		struct ltq_etop_chan *ch = &priv->ch[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		ch->idx = ch->dma.nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		ch->dma.dev = &priv->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (IS_TX(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			ltq_dma_alloc_tx(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		} else if (IS_RX(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			ltq_dma_alloc_rx(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 					ch->dma.desc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				if (ltq_etop_alloc_skb(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			ch->dma.desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ch->dma.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct ethtool_ops ltq_etop_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.get_drvinfo = ltq_etop_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.nway_reset = phy_ethtool_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	u32 val = MDIO_REQUEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		phy_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ltq_etop_w32(val, LTQ_ETOP_MDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	u32 val = MDIO_REQUEST | MDIO_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ltq_etop_w32(val, LTQ_ETOP_MDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ltq_etop_mdio_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* nothing to do  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ltq_etop_mdio_probe(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	phydev = phy_find_first(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (!phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		netdev_err(dev, "no PHY found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	phydev = phy_connect(dev, phydev_name(phydev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			     &ltq_etop_mdio_link, priv->pldata->mii_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (IS_ERR(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		netdev_err(dev, "Could not attach to PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return PTR_ERR(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	phy_set_max_speed(phydev, SPEED_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	phy_attached_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ltq_etop_mdio_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	priv->mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (!priv->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		netdev_err(dev, "failed to allocate mii bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	priv->mii_bus->priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	priv->mii_bus->read = ltq_etop_mdio_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	priv->mii_bus->write = ltq_etop_mdio_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	priv->mii_bus->name = "ltq_mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		priv->pdev->name, priv->pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (mdiobus_register(priv->mii_bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (ltq_etop_mdio_probe(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		goto err_out_unregister_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err_out_unregister_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	mdiobus_unregister(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err_out_free_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	mdiobus_free(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ltq_etop_mdio_cleanup(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	phy_disconnect(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	mdiobus_unregister(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	mdiobus_free(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ltq_etop_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	for (i = 0; i < MAX_DMA_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		struct ltq_etop_chan *ch = &priv->ch[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		if (!IS_TX(i) && (!IS_RX(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		ltq_dma_open(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		ltq_dma_enable_irq(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		napi_enable(&ch->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	phy_start(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	netif_tx_start_all_queues(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ltq_etop_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	netif_tx_stop_all_queues(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	phy_stop(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	for (i = 0; i < MAX_DMA_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		struct ltq_etop_chan *ch = &priv->ch[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		if (!IS_RX(i) && !IS_TX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		napi_disable(&ch->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		ltq_dma_close(&ch->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	int queue = skb_get_queue_mapping(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	u32 byte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		netdev_err(dev, "tx ring full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		netif_tx_stop_queue(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	/* dma needs to start on a 16 byte aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	byte_offset = CPHYSADDR(skb->data) % 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	ch->skb[ch->dma.desc] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 						DMA_TO_DEVICE)) - byte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	ch->dma.desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	ch->dma.desc %= LTQ_DESC_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		netif_tx_stop_queue(txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ltq_etop_set_mac_address(struct net_device *dev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	int ret = eth_mac_addr(dev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		/* store the mac for the unicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 			LTQ_ETOP_MAC_DA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ltq_etop_set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	/* ensure that the unicast filter is not enabled in promiscious mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ltq_etop_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	struct ltq_etop_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	struct sockaddr mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	bool random_mac = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	dev->watchdog_timeo = 10 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	err = ltq_etop_hw_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		goto err_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	ltq_etop_change_mtu(dev, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	if (!is_valid_ether_addr(mac.sa_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		pr_warn("etop: invalid MAC, using random\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		eth_random_addr(mac.sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		random_mac = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	err = ltq_etop_set_mac_address(dev, &mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		goto err_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	if (random_mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		dev->addr_assign_type = NET_ADDR_RANDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	ltq_etop_set_multicast_list(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	err = ltq_etop_mdio_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		goto err_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) err_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	ltq_etop_hw_exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	ltq_etop_hw_exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	err = ltq_etop_hw_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		goto err_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) err_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	ltq_etop_hw_exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	netdev_err(dev, "failed to restart etop after TX timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct net_device_ops ltq_eth_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.ndo_open = ltq_etop_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.ndo_stop = ltq_etop_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.ndo_start_xmit = ltq_etop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.ndo_change_mtu = ltq_etop_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.ndo_do_ioctl = phy_do_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.ndo_set_mac_address = ltq_etop_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	.ndo_set_rx_mode = ltq_etop_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	.ndo_select_queue = dev_pick_tx_zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	.ndo_init = ltq_etop_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	.ndo_tx_timeout = ltq_etop_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ltq_etop_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	struct ltq_etop_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 		dev_err(&pdev->dev, "failed to get etop resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	res = devm_request_mem_region(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 		resource_size(res), dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		dev_err(&pdev->dev, "failed to request etop resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	ltq_etop_membase = devm_ioremap(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 		res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	if (!ltq_etop_membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 		dev_err(&pdev->dev, "failed to remap etop engine %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 			pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	strcpy(dev->name, "eth%d");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	dev->netdev_ops = &ltq_eth_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	dev->ethtool_ops = &ltq_etop_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	priv->res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	priv->pldata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 	priv->netdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	for (i = 0; i < MAX_DMA_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 		if (IS_TX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 			netif_napi_add(dev, &priv->ch[i].napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 				ltq_etop_poll_tx, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		else if (IS_RX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 			netif_napi_add(dev, &priv->ch[i].napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 				ltq_etop_poll_rx, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 		priv->ch[i].netdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ltq_etop_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	if (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 		netif_tx_stop_all_queues(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 		ltq_etop_hw_exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 		ltq_etop_mdio_cleanup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static struct platform_driver ltq_mii_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	.remove = ltq_etop_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 		.name = "ltq_etop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) init_ltq_etop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 		pr_err("ltq_etop: Error registering platform driver!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) exit_ltq_etop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	platform_driver_unregister(&ltq_mii_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) module_init(init_ltq_etop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) module_exit(exit_ltq_etop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_DESCRIPTION("Lantiq SoC ETOP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MODULE_LICENSE("GPL");