^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2004 IDT Inc. (rischelp@idt.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2017 Roman Yeryomin <roman@advem.lv>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Writing to a DMA status register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * When writing to the status register, you should mask the bit you have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * been testing the status register with. Both Tx and Rx DMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * should stick to this procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <asm/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <asm/mach-rc32434/rb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <asm/mach-rc32434/rc32434.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <asm/mach-rc32434/eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <asm/mach-rc32434/dma_v.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRV_NAME "korina"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRV_VERSION "0.20"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRV_RELDATE "15Sep2017"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ((dev)->dev_addr[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ((dev)->dev_addr[3] << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((dev)->dev_addr[4] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ((dev)->dev_addr[5]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MII_CLOCK 1250000 /* no more than 2.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* the following must be powers of two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define KORINA_NUM_RDS 64 /* number of receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define KORINA_NUM_TDS 64 /* number of transmit descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* KORINA_RBSIZE is the hardware's default maximum receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * frame size in bytes. Having this hardcoded means that there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * is no support for MTU sizes greater than 1500. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TX_TIMEOUT (6000 * HZ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum chain_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) desc_filled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) desc_empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Information that need to be kept for each board. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct korina_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct eth_regs *eth_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct dma_reg *rx_dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct dma_reg *tx_dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dma_desc *td_ring; /* transmit descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dma_desc *rd_ring; /* receive descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct sk_buff *tx_skb[KORINA_NUM_TDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct sk_buff *rx_skb[KORINA_NUM_RDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int rx_next_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int rx_chain_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int rx_chain_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum chain_status rx_chain_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int tx_next_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int tx_chain_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int tx_chain_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum chain_status tx_chain_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int tx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int tx_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spinlock_t lock; /* NIC xmit lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int dma_halt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int dma_run_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct timer_list media_check_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct work_struct restart_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) extern unsigned int idt_cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(0, &ch->dmandptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(dma_addr, &ch->dmadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void korina_abort_dma(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dma_reg *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(0x10, &ch->dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) while (!(readl(&ch->dmas) & DMA_STAT_HALT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(0, &ch->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writel(0, &ch->dmadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(0, &ch->dmandptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(dma_addr, &ch->dmandptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void korina_abort_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) korina_abort_dma(dev, lp->tx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void korina_abort_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) korina_abort_dma(dev, lp->rx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void korina_start_rx(struct korina_private *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct dma_desc *rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void korina_chain_rx(struct korina_private *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct dma_desc *rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* transmit packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 chain_prev, chain_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct dma_desc *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spin_lock_irqsave(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) td = &lp->td_ring[lp->tx_chain_tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* stop queue when full, drop pkts if queue already full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) lp->tx_full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (lp->tx_count == (KORINA_NUM_TDS - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_unlock_irqrestore(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) lp->tx_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) lp->tx_skb[lp->tx_chain_tail] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) length = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dma_cache_wback((u32)skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Setup the transmit descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_cache_inv((u32) td, sizeof(*td));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) td->ca = CPHYSADDR(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (lp->tx_chain_status == desc_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Update tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) td->control = DMA_COUNT(length) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DMA_DESC_COF | DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Move tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) lp->tx_chain_tail = chain_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Write to NDPTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &lp->tx_dma_regs->dmandptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Move head to tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) lp->tx_chain_head = lp->tx_chain_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Update tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) td->control = DMA_COUNT(length) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DMA_DESC_COF | DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Link to prev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) lp->td_ring[chain_prev].control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ~DMA_DESC_COF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Link to prev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lp->td_ring[chain_prev].link = CPHYSADDR(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Move tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) lp->tx_chain_tail = chain_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Write to NDPTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) &(lp->tx_dma_regs->dmandptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Move head to tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) lp->tx_chain_head = lp->tx_chain_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) lp->tx_chain_status = desc_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (lp->tx_chain_status == desc_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Update tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) td->control = DMA_COUNT(length) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DMA_DESC_COF | DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Move tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) lp->tx_chain_tail = chain_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) lp->tx_chain_status = desc_filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Update tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) td->control = DMA_COUNT(length) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DMA_DESC_COF | DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) lp->td_ring[chain_prev].control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ~DMA_DESC_COF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) lp->td_ring[chain_prev].link = CPHYSADDR(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) lp->tx_chain_tail = chain_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_cache_wback((u32) td, sizeof(*td));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock_irqrestore(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mdio_read(struct net_device *dev, int mii_id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(0, &lp->eth_regs->miimcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(0, &lp->eth_regs->miimcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) writel(mii_id | reg, &lp->eth_regs->miimaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = (int)(readl(&lp->eth_regs->miimrdd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(0, &lp->eth_regs->miimcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(1, &lp->eth_regs->miimcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(mii_id | reg, &lp->eth_regs->miimaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel(val, &lp->eth_regs->miimwtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Ethernet Rx DMA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 dmas, dmasm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) irqreturn_t retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dmas = readl(&lp->rx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dmasm = readl(&lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writel(dmasm | (DMA_STAT_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DMA_STAT_HALT | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) &lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) napi_schedule(&lp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (dmas & DMA_STAT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) printk(KERN_ERR "%s: DMA error\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int korina_rx(struct net_device *dev, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct sk_buff *skb, *skb_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 *pkt_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 devcs, pkt_len, dmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dma_cache_inv((u32)rd, sizeof(*rd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (count = 0; count < limit; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) skb = lp->rx_skb[lp->rx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) skb_new = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) devcs = rd->devcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* check that this is a whole packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * WARNING: DMA_FD bit incorrectly set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * in Rc32434 (errata ref #077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!(devcs & ETH_RX_LD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!(devcs & ETH_RX_ROK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Update statistics counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (devcs & ETH_RX_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (devcs & ETH_RX_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (devcs & ETH_RX_OVR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (devcs & ETH_RX_CV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (devcs & ETH_RX_CES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pkt_len = RCVPKT_LENGTH(devcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* must be the (first and) last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * descriptor then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* invalidate the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Malloc up new buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!skb_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Do not count the CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) skb_put(skb, pkt_len - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Pass the packet to upper layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) napi_gro_receive(&lp->napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev->stats.rx_bytes += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Update the mcast stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (devcs & ETH_RX_MP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev->stats.multicast++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) lp->rx_skb[lp->rx_next_done] = skb_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rd->devcs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Restore descriptor's curr_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (skb_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rd->ca = CPHYSADDR(skb_new->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rd->ca = CPHYSADDR(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rd->control = DMA_COUNT(KORINA_RBSIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DMA_DESC_COD | DMA_DESC_IOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lp->rd_ring[(lp->rx_next_done - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) KORINA_RDS_MASK].control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ~DMA_DESC_COD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_cache_wback((u32)rd, sizeof(*rd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rd = &lp->rd_ring[lp->rx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dmas = readl(&lp->rx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (dmas & DMA_STAT_HALT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &lp->rx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) lp->dma_halt_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rd->devcs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) skb = lp->rx_skb[lp->rx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rd->ca = CPHYSADDR(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma_cache_wback((u32)rd, sizeof(*rd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) korina_chain_rx(lp, rd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int korina_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct korina_private *lp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) container_of(napi, struct korina_private, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) work_done = korina_rx(dev, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) napi_complete_done(napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel(readl(&lp->rx_dma_regs->dmasm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Set or clear the multicast filter for this adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void korina_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 recognise = ETH_ARC_AB; /* always accept broadcasts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Set promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) recognise |= ETH_ARC_PRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* All multicast and broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) recognise |= ETH_ARC_AM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Build the hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (netdev_mc_count(dev) > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 hash_table[4] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) crc = ether_crc_le(6, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) crc >>= 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Accept filtered multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) recognise |= ETH_ARC_AFM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Fill the MAC hash tables with their values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel((u32)(hash_table[1] << 16 | hash_table[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &lp->eth_regs->ethhash0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel((u32)(hash_table[3] << 16 | hash_table[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &lp->eth_regs->ethhash1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_lock_irqsave(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writel(recognise, &lp->eth_regs->etharc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) spin_unlock_irqrestore(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void korina_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 devcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 dmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) spin_lock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Process all desc that are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) while (IS_DMA_FINISHED(td->control)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (lp->tx_full == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) lp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) devcs = lp->td_ring[lp->tx_next_done].devcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) (ETH_TX_FD | ETH_TX_LD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) printk(KERN_ERR "%s: split tx ignored\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) } else if (devcs & ETH_TX_TOK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev->stats.tx_bytes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) lp->tx_skb[lp->tx_next_done]->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (devcs & ETH_TX_UND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Oversized frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (devcs & ETH_TX_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Excessive deferrals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (devcs & ETH_TX_ED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Collisions: medium busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (devcs & ETH_TX_EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (devcs & ETH_TX_LC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* We must always free the original skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (lp->tx_skb[lp->tx_next_done]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) lp->tx_skb[lp->tx_next_done] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) lp->td_ring[lp->tx_next_done].link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) lp->td_ring[lp->tx_next_done].ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) lp->tx_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Go on to next transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) td = &lp->td_ring[lp->tx_next_done];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Clear the DMA status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dmas = readl(&lp->tx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel(~dmas, &lp->tx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) writel(readl(&lp->tx_dma_regs->dmasm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ~(DMA_STAT_FINI | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_unlock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) korina_tx_dma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 dmas, dmasm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) irqreturn_t retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dmas = readl(&lp->tx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dmasm = readl(&lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) korina_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (lp->tx_chain_status == desc_filled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &(lp->tx_dma_regs->dmandptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) lp->tx_chain_status = desc_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) lp->tx_chain_head = lp->tx_chain_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (dmas & DMA_STAT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) printk(KERN_ERR "%s: DMA error\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void korina_check_media(struct net_device *dev, unsigned int init_media)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mii_check_media(&lp->mii_if, 0, init_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (lp->mii_if.full_duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &lp->eth_regs->ethmac2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &lp->eth_regs->ethmac2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static void korina_poll_media(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct korina_private *lp = from_timer(lp, t, media_check_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) korina_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mod_timer(&lp->media_check_timer, jiffies + HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void korina_set_carrier(struct mii_if_info *mii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (mii->force_media) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* autoneg is off: Link is always assumed to be up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!netif_carrier_ok(mii->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) netif_carrier_on(mii->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } else /* Let MMI library update carrier status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) korina_check_media(mii->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct mii_ioctl_data *data = if_mii(rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) korina_set_carrier(&lp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* ethtool helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static void netdev_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) strlcpy(info->bus_info, lp->dev->name, sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int netdev_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int netdev_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) spin_lock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) rc = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_unlock_irq(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) korina_set_carrier(&lp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static u32 netdev_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return mii_link_ok(&lp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct ethtool_ops netdev_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .get_drvinfo = netdev_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .get_link = netdev_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .get_link_ksettings = netdev_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .set_link_ksettings = netdev_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int korina_alloc_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Initialize the transmit descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) for (i = 0; i < KORINA_NUM_TDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) lp->td_ring[i].control = DMA_DESC_IOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) lp->td_ring[i].ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) lp->td_ring[i].link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) lp->tx_full = lp->tx_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) lp->tx_chain_status = desc_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Initialize the receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (i = 0; i < KORINA_NUM_RDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) lp->rx_skb[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) lp->rd_ring[i].control = DMA_DESC_IOD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DMA_COUNT(KORINA_RBSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) lp->rd_ring[i].devcs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) lp->rd_ring[i].ca = CPHYSADDR(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* loop back receive descriptors, so the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * descriptor points to the first one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) lp->rd_ring[i - 1].control |= DMA_DESC_COD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) lp->rx_next_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) lp->rx_chain_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) lp->rx_chain_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) lp->rx_chain_status = desc_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void korina_free_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (i = 0; i < KORINA_NUM_RDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) lp->rd_ring[i].control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (lp->rx_skb[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_kfree_skb_any(lp->rx_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) lp->rx_skb[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for (i = 0; i < KORINA_NUM_TDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) lp->td_ring[i].control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (lp->tx_skb[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_kfree_skb_any(lp->tx_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) lp->tx_skb[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Initialize the RC32434 ethernet controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int korina_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Disable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) korina_abort_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) korina_abort_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* reset ethernet logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(0, &lp->eth_regs->ethintfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Enable Ethernet Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Allocate rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (korina_alloc_ring(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) korina_free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) writel(0, &lp->rx_dma_regs->dmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Start Rx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) korina_start_rx(lp, &lp->rd_ring[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) writel(readl(&lp->tx_dma_regs->dmasm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ~(DMA_STAT_FINI | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) writel(readl(&lp->rx_dma_regs->dmasm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Accept only packets destined for this Ethernet device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) writel(ETH_ARC_AB, &lp->eth_regs->etharc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Set all Ether station address registers to their initial values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &lp->eth_regs->ethmac2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Back to back inter-packet-gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) writel(0x15, &lp->eth_regs->ethipgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Non - Back to back inter-packet-gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) writel(0x12, &lp->eth_regs->ethipgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Management Clock Prescaler Divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Clock independent setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &lp->eth_regs->ethmcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* don't transmit until fifo contains 48b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) writel(48, &lp->eth_regs->ethfifott);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) napi_enable(&lp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Restart the RC32434 ethernet controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void korina_restart_task(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct korina_private *lp = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct korina_private, restart_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) disable_irq(lp->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) disable_irq(lp->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) writel(readl(&lp->tx_dma_regs->dmasm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DMA_STAT_FINI | DMA_STAT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) writel(readl(&lp->rx_dma_regs->dmasm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) napi_disable(&lp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) korina_free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (korina_init(dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) printk(KERN_ERR "%s: cannot restart device\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) korina_multicast_list(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) enable_irq(lp->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) enable_irq(lp->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void korina_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) schedule_work(&lp->restart_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static void korina_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) korina_tx_dma_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int korina_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = korina_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) printk(KERN_ERR "%s: cannot open device\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Install the interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * that handles the Done Finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 0, "Korina ethernet Rx", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev->name, lp->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) 0, "Korina ethernet Tx", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev->name, lp->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err_free_rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mod_timer(&lp->media_check_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) err_free_rx_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) free_irq(lp->rx_irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) korina_free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int korina_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct korina_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) del_timer(&lp->media_check_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) disable_irq(lp->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) disable_irq(lp->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) korina_abort_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) tmp = readl(&lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writel(tmp, &lp->tx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) korina_abort_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) tmp = readl(&lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) writel(tmp, &lp->rx_dma_regs->dmasm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) napi_disable(&lp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) cancel_work_sync(&lp->restart_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) korina_free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) free_irq(lp->rx_irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) free_irq(lp->tx_irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct net_device_ops korina_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .ndo_open = korina_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .ndo_stop = korina_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ndo_start_xmit = korina_send_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .ndo_set_rx_mode = korina_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .ndo_tx_timeout = korina_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .ndo_do_ioctl = korina_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .ndo_poll_controller = korina_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int korina_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct korina_device *bif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct korina_private *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dev = alloc_etherdev(sizeof(struct korina_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) bif->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) memcpy(dev->dev_addr, bif->mac, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev->base_addr = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) lp->eth_regs = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!lp->eth_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) printk(KERN_ERR DRV_NAME ": cannot remap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto probe_err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) lp->rx_dma_regs = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!lp->rx_dma_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) goto probe_err_dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) lp->tx_dma_regs = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!lp->tx_dma_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) goto probe_err_dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!lp->td_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto probe_err_td_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dma_cache_inv((unsigned long)(lp->td_ring),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) TD_RING_SIZE + RD_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* now convert TD_RING pointer to KSEG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) spin_lock_init(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* just use the rx dma irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev->irq = lp->rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) lp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev->netdev_ops = &korina_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev->ethtool_ops = &netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev->watchdog_timeo = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) netif_napi_add(dev, &lp->napi, korina_poll, NAPI_POLL_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) lp->mii_if.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) lp->mii_if.mdio_read = mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) lp->mii_if.mdio_write = mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) lp->mii_if.phy_id = lp->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) lp->mii_if.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) lp->mii_if.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) rc = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ": cannot register net device: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) goto probe_err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) timer_setup(&lp->media_check_timer, korina_poll_media, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) INIT_WORK(&lp->restart_task, korina_restart_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) probe_err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) kfree((struct dma_desc *)KSEG0ADDR(lp->td_ring));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) probe_err_td_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) iounmap(lp->tx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) probe_err_dma_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) iounmap(lp->rx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) probe_err_dma_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) iounmap(lp->eth_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) probe_err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int korina_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct korina_device *bif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct korina_private *lp = netdev_priv(bif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) iounmap(lp->eth_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) iounmap(lp->rx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) iounmap(lp->tx_dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) kfree((struct dma_desc *)KSEG0ADDR(lp->td_ring));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) unregister_netdev(bif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) free_netdev(bif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static struct platform_driver korina_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .driver.name = "korina",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .probe = korina_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .remove = korina_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) module_platform_driver(korina_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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