^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 JMicron Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * https://www.jmicron.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __JME_H_INCLUDED__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __JME_H_INCLUDED__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DRV_NAME "jme"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRV_VERSION "1.0.8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Message related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JME_DEF_MSG_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (NETIF_MSG_PROBE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) NETIF_MSG_LINK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) NETIF_MSG_RX_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) NETIF_MSG_TX_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) NETIF_MSG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef TX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define tx_dbg(priv, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define tx_dbg(priv, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Extra PCI Configuration space interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DCSR_MRRS 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DCSR_MRRS_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum pci_dcsr_mrrs_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MRRS_128B = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MRRS_256B = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MRRS_512B = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MRRS_1024B = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MRRS_2048B = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MRRS_4096B = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_SPI 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum pci_spi_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SPI_EN = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SPI_MISO = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SPI_MOSI = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SPI_SCLK = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SPI_CS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct jme_spi_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __user *uwbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __user *urbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __u8 wn; /* Number of write actions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __u8 rn; /* Number of read actions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __u8 bitn; /* Number of bits per action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Internal use only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 *kwbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 *krbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum jme_spi_op_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SPI_MODE_CPHA = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SPI_MODE_CPOL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SPI_MODE_DUP = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HALF_US 500 /* 500 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCI_PRIV_PE1 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum pci_priv_pe1_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PE1_ASPMSUPRT = 0x00000003, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * RW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Aspm_support[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * (R/W Port of 5C[11:10])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PE1_GPREG0 = 0x0000FF00, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * SRW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Cfg_gp_reg0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * [7:6] phy_giga BG control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * [4:0] Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PE1_REVID = 0xFF000000, /* RO: Rev ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum pci_priv_pe1_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PE1_GPREG0_ENBG = 0x00000000, /* en BG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Dynamic(adaptive)/Static PCC values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum dynamic_pcc_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PCC_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PCC_P1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PCC_P2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PCC_P3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PCC_OFF_TO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PCC_P1_TO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PCC_P2_TO = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PCC_P3_TO = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PCC_OFF_CNT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PCC_P1_CNT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PCC_P2_CNT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PCC_P3_CNT = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dynpcc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long last_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long last_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long intr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned char cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char attempt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCC_INTERVAL_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCC_P2_THRESHOLD 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCC_INTR_THRESHOLD 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCC_TX_TO 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCC_TX_CNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * TX/RX Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RING_DESC_ALIGN 16 /* Descriptor alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TX_DESC_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TX_RING_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct txdesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __u8 all[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __le32 dw[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __u8 rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __le16 datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le16 mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* DW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le16 pktsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le16 rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* DW3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le32 bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le16 rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __u8 rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le16 datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le16 rsv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* DW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 bufaddrh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* DW3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __le32 bufaddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } desc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __u8 ehdrsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __u8 rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __u8 rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le16 trycnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le16 segcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* DW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le16 pktsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __le16 rsv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* DW3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __le32 bufaddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } descwb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum jme_txdesc_flags_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TXFLAG_OWN = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TXFLAG_INT = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TXFLAG_64BIT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TXFLAG_TCPCS = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) TXFLAG_UDPCS = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TXFLAG_IPCS = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) TXFLAG_LSEN = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TXFLAG_TAGON = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TXDESC_MSS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum jme_txwbdesc_flags_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TXWBFLAG_OWN = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TXWBFLAG_INT = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TXWBFLAG_TMOUT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) TXWBFLAG_TRYOUT = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TXWBFLAG_COL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TXWBFLAG_TRYOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TXWBFLAG_COL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RX_DESC_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RX_RING_NR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RX_BUF_DMA_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RX_PREPAD_SIZE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ETH_CRC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define RX_VLANHDR_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ETH_HLEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ETH_CRC_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RX_VLANHDR_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RX_BUF_DMA_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct rxdesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __u8 all[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __le32 dw[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __le16 rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __u8 rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le16 datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le16 wbcpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* DW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __le32 bufaddrh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* DW3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le32 bufaddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le16 framesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __u8 errstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __u8 desccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* DW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __le32 rsshash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* DW3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __u8 hashfun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __u8 hashtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le16 resrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) } descwb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum jme_rxdesc_flags_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RXFLAG_OWN = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) RXFLAG_INT = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) RXFLAG_64BIT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum jme_rxwbdesc_flags_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RXWBFLAG_OWN = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RXWBFLAG_INT = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RXWBFLAG_MF = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) RXWBFLAG_64BIT = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) RXWBFLAG_TCPON = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RXWBFLAG_UDPON = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RXWBFLAG_IPCS = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) RXWBFLAG_TCPCS = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RXWBFLAG_UDPCS = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RXWBFLAG_TAGON = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RXWBFLAG_IPV4 = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RXWBFLAG_IPV6 = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RXWBFLAG_PAUSE = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RXWBFLAG_MAGIC = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RXWBFLAG_WAKEUP = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RXWBFLAG_DEST = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RXWBFLAG_DEST_UNI = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RXWBFLAG_DEST_MUL = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RXWBFLAG_DEST_BRO = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) enum jme_rxwbdesc_desccnt_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) RXWBDCNT_WBCPL = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RXWBDCNT_DCNT = 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) enum jme_rxwbdesc_errstat_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) RXWBERR_LIMIT = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RXWBERR_MIIER = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RXWBERR_NIBON = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RXWBERR_COLON = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RXWBERR_ABORT = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RXWBERR_SHORT = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RXWBERR_OVERUN = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RXWBERR_CRCERR = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) RXWBERR_ALLERR = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Buffer information corresponding to ring descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct jme_buffer_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int nr_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned long start_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * The structure holding buffer information and ring descriptors all together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct jme_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void *alloc; /* pointer to allocated memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void *desc; /* pointer to ring memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dma_addr_t dmaalloc; /* phys address of ring alloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dma_addr_t dma; /* phys address for ring dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Buffer information corresponding to each descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct jme_buffer_info *bufinf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int next_to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) atomic_t next_to_clean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) atomic_t nr_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define NET_STAT(priv) (priv->dev->stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define NETDEV_GET_STATS(netdev, fun_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DECLARE_NET_DEVICE_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DECLARE_NAPI_STRUCT struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) netif_napi_add(dev, napis, pollfn, q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define JME_NAPI_WEIGHT(w) int w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define JME_NAPI_WEIGHT_VAL(w) w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define JME_NAPI_WEIGHT_SET(w, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define JME_NAPI_DISABLE(priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!napi_disable_pending(&priv->napi)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define JME_RX_SCHEDULE_PREP(priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) napi_schedule_prep(&priv->napi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define JME_RX_SCHEDULE(priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Jmac Adapter Private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct jme_adapter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct jme_ring rxring[RX_RING_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct jme_ring txring[TX_RING_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spinlock_t phy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spinlock_t macaddr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) spinlock_t rxmcs_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct tasklet_struct rxempty_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct tasklet_struct rxclean_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct tasklet_struct txclean_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct tasklet_struct linkch_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct tasklet_struct pcc_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 reg_txcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 reg_txpfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 reg_rxcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 reg_rxmcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 reg_ghc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 reg_pmcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 reg_gpreg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 tx_ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 tx_wake_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 rx_ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 mrrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int fpgaver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 chiprev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 chip_main_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 chip_sub_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 pcirev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ethtool_link_ksettings old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int old_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct dynpcc_info dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) atomic_t intr_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) atomic_t link_changing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) atomic_t tx_cleaning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) atomic_t rx_cleaning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) atomic_t rx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int (*jme_rx)(struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DECLARE_NAPI_STRUCT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DECLARE_NET_DEVICE_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) enum jme_flags_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) JME_FLAG_MSI = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) JME_FLAG_SSET = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) JME_FLAG_POLL = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) JME_FLAG_SHUTDOWN = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TX_TIMEOUT (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define JME_REG_LEN 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static inline struct jme_adapter*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) jme_napi_priv(struct napi_struct *napi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct jme_adapter *jme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) jme = container_of(napi, struct jme_adapter, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return jme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * MMaped I/O Resters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) enum jme_iomap_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) JME_MAC = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) JME_PHY = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) JME_MISC = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) JME_RSS = 0x0C00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) enum jme_iomap_lens {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) JME_MAC_LEN = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) JME_PHY_LEN = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) JME_MISC_LEN = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) JME_RSS_LEN = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum jme_iomap_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) JME_GHC = JME_MAC | 0x54, /* Global Host Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * TX Control/Status Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) enum jme_txcs_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) TXCS_QUEUE7S = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) TXCS_QUEUE6S = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TXCS_QUEUE5S = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) TXCS_QUEUE4S = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) TXCS_QUEUE3S = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) TXCS_QUEUE2S = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) TXCS_QUEUE1S = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) TXCS_QUEUE0S = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) TXCS_FIFOTH = 0x000000C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) TXCS_DMASIZE = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) TXCS_BURST = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) TXCS_ENABLE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) enum jme_txcs_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) TXCS_FIFOTH_16QW = 0x000000C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) TXCS_FIFOTH_12QW = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) TXCS_FIFOTH_8QW = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) TXCS_FIFOTH_4QW = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TXCS_DMASIZE_64B = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) TXCS_DMASIZE_128B = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TXCS_DMASIZE_256B = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) TXCS_DMASIZE_512B = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) TXCS_SELECT_QUEUE0 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) TXCS_SELECT_QUEUE1 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) TXCS_SELECT_QUEUE2 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) TXCS_SELECT_QUEUE3 = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) TXCS_SELECT_QUEUE4 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) TXCS_SELECT_QUEUE5 = 0x00050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) TXCS_SELECT_QUEUE6 = 0x00060000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TXCS_SELECT_QUEUE7 = 0x00070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TXCS_DEFAULT = TXCS_FIFOTH_4QW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) TXCS_BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * TX MAC Control/Status Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) enum jme_txmcs_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) TXMCS_IFG2 = 0xC0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) TXMCS_IFG1 = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TXMCS_TTHOLD = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) TXMCS_FBURST = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) TXMCS_CARRIEREXT = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TXMCS_DEFER = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) TXMCS_BACKOFF = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) TXMCS_CARRIERSENSE = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) TXMCS_COLLISION = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) TXMCS_CRC = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TXMCS_PADDING = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) enum jme_txmcs_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) TXMCS_IFG2_6_4 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TXMCS_IFG2_8_5 = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) TXMCS_IFG2_10_6 = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) TXMCS_IFG2_12_7 = 0xC0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) TXMCS_IFG1_8_4 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) TXMCS_IFG1_12_6 = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) TXMCS_IFG1_16_8 = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) TXMCS_IFG1_20_10 = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) TXMCS_TTHOLD_1_8 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) TXMCS_TTHOLD_1_4 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) TXMCS_TTHOLD_1_2 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) TXMCS_TTHOLD_FULL = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) TXMCS_IFG1_16_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) TXMCS_TTHOLD_FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) TXMCS_DEFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) TXMCS_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) TXMCS_PADDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) enum jme_txpfc_bits_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) TXPFC_VLAN_TAG = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) TXPFC_VLAN_EN = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) TXPFC_PF_EN = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) enum jme_txtrhd_bits_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) TXTRHD_TXPEN = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) TXTRHD_TXP = 0x7FFFFF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) TXTRHD_TXREN = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) TXTRHD_TXRL = 0x0000007F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) enum jme_txtrhd_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) TXTRHD_TXP_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) TXTRHD_TXRL_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) enum jme_txtrhd_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) TXTRHD_FULLDUPLEX = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) TXTRHD_TXREN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * RX Control/Status Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) enum jme_rxcs_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* FIFO full threshold for transmitting Tx Pause Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RXCS_FIFOTHTP = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* FIFO threshold for processing next packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RXCS_FIFOTHNP = 0x0C000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) RXCS_QUEUESEL = 0x00030000, /* Queue selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RXCS_SHORT = 0x00000010, /* Enable receive short packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) RXCS_QST = 0x00000004, /* Receive queue start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RXCS_SUSPEND = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RXCS_ENABLE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) enum jme_rxcs_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RXCS_FIFOTHTP_16T = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RXCS_FIFOTHTP_32T = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RXCS_FIFOTHTP_64T = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) RXCS_FIFOTHTP_128T = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) RXCS_FIFOTHNP_16QW = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RXCS_FIFOTHNP_32QW = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) RXCS_FIFOTHNP_64QW = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RXCS_FIFOTHNP_128QW = 0x0C000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) RXCS_DMAREQSZ_16B = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RXCS_DMAREQSZ_32B = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RXCS_DMAREQSZ_64B = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RXCS_DMAREQSZ_128B = 0x03000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RXCS_QUEUESEL_Q0 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RXCS_QUEUESEL_Q1 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RXCS_QUEUESEL_Q2 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RXCS_QUEUESEL_Q3 = 0x00030000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RXCS_RETRYGAP_256ns = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RXCS_RETRYGAP_512ns = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RXCS_RETRYGAP_1024ns = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RXCS_RETRYGAP_2048ns = 0x00003000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RXCS_RETRYGAP_4096ns = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RXCS_RETRYGAP_8192ns = 0x00005000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RXCS_RETRYGAP_16384ns = 0x00006000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RXCS_RETRYGAP_32768ns = 0x00007000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RXCS_RETRYCNT_0 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) RXCS_RETRYCNT_4 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RXCS_RETRYCNT_8 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RXCS_RETRYCNT_12 = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RXCS_RETRYCNT_16 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RXCS_RETRYCNT_20 = 0x00000500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RXCS_RETRYCNT_24 = 0x00000600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RXCS_RETRYCNT_28 = 0x00000700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RXCS_RETRYCNT_32 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RXCS_RETRYCNT_36 = 0x00000900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RXCS_RETRYCNT_40 = 0x00000A00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RXCS_RETRYCNT_44 = 0x00000B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RXCS_RETRYCNT_48 = 0x00000C00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RXCS_RETRYCNT_52 = 0x00000D00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RXCS_RETRYCNT_56 = 0x00000E00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RXCS_RETRYCNT_60 = 0x00000F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RXCS_FIFOTHNP_16QW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RXCS_DMAREQSZ_128B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RXCS_RETRYGAP_256ns |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RXCS_RETRYCNT_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * RX MAC Control/Status Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) enum jme_rxmcs_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RXMCS_ALLFRAME = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RXMCS_BRDFRAME = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RXMCS_MULFRAME = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RXMCS_UNIFRAME = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RXMCS_ALLMULFRAME = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RXMCS_MULFILTERED = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RXMCS_RXCOLLDEC = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RXMCS_FLOWCTRL = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RXMCS_VTAGRM = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RXMCS_PREPAD = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) RXMCS_CHECKSUM = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RXMCS_DEFAULT = RXMCS_VTAGRM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RXMCS_PREPAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RXMCS_FLOWCTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RXMCS_CHECKSUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Extern PHY common register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define PHY_GAD_TEST_MODE_1 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define PHY_GAD_TEST_MODE_MSK 0x0000E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define JM_PHY_SPEC_REG_READ 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define JM_PHY_SPEC_REG_WRITE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PHY_CALIBRATION_DELAY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define JM_PHY_SPEC_ADDR_REG 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define JM_PHY_SPEC_DATA_REG 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define JM_PHY_EXT_COMM_0_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define JM_PHY_EXT_COMM_1_REG 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define JM_PHY_EXT_COMM_2_REG 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define PCI_PRIV_SHARE_NICCTRL 0xF5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define JME_FLAG_PHYEA_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Wakeup Frame setup interface registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define WAKEUP_FRAME_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define WAKEUP_FRAME_MASK_DWNR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) enum jme_wfoi_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) WFOI_MASK_SEL = 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) WFOI_CRC_SEL = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) WFOI_FRAME_SEL = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) enum jme_wfoi_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) WFOI_MASK_SHIFT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * SMI Related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) enum jme_smi_bit_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SMI_DATA_MASK = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SMI_REG_ADDR_MASK = 0x0000F800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SMI_PHY_ADDR_MASK = 0x000007C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) SMI_OP_WRITE = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Set to 1, after req done it'll be cleared to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SMI_OP_REQ = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) SMI_OP_MDC = 0x00000002, /* Software CLK Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SMI_OP_MDEN = 0x00000001, /* Software access Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) enum jme_smi_bit_shift {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SMI_DATA_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) SMI_REG_ADDR_SHIFT = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SMI_PHY_ADDR_SHIFT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline u32 smi_reg_addr(int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static inline u32 smi_phy_addr(int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define JME_PHY_TIMEOUT 100 /* 100 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define JME_PHY_REG_NR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Global Host Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) enum jme_ghc_bit_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GHC_SWRST = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GHC_TO_CLK_SRC = 0x00C00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GHC_TXMAC_CLK_SRC = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GHC_DPX = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GHC_SPEED = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GHC_LINK_POLL = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) enum jme_ghc_speed_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GHC_SPEED_10M = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GHC_SPEED_100M = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GHC_SPEED_1000M = 0x00000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) enum jme_ghc_to_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GHC_TO_CLK_OFF = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GHC_TO_CLK_GPHY = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GHC_TO_CLK_PCIE = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GHC_TO_CLK_INVALID = 0x00C00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) enum jme_ghc_txmac_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GHC_TXMAC_CLK_OFF = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GHC_TXMAC_CLK_GPHY = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GHC_TXMAC_CLK_PCIE = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GHC_TXMAC_CLK_INVALID = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Power management control and status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) enum jme_pmcs_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PMCS_STMASK = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PMCS_WF7DET = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PMCS_WF6DET = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PMCS_WF5DET = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PMCS_WF4DET = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PMCS_WF3DET = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PMCS_WF2DET = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PMCS_WF1DET = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PMCS_WF0DET = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PMCS_LFDET = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PMCS_LRDET = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PMCS_MFDET = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PMCS_ENMASK = 0x0000FFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PMCS_WF7EN = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PMCS_WF6EN = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PMCS_WF5EN = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PMCS_WF4EN = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PMCS_WF3EN = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PMCS_WF2EN = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PMCS_WF1EN = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PMCS_WF0EN = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PMCS_LFEN = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PMCS_LREN = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PMCS_MFEN = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * New PHY Power Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) enum jme_phy_pwr_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PHY_PWR_CLKSEL = 0x08000000, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * XTL_OUT Clock select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * (an internal free-running clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * 0: xtl_out = phy_giga.A_XTL25_O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * 1: xtl_out = phy_giga.PD_OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * Giga PHY Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) enum jme_phy_link_bit_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PHY_LINK_SPEED_MASK = 0x0000C000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PHY_LINK_DUPLEX = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PHY_LINK_UP = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PHY_LINK_MDI_STAT = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) enum jme_phy_link_speed_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PHY_LINK_SPEED_10M = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PHY_LINK_SPEED_100M = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PHY_LINK_SPEED_1000M = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * SMB Control and Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) enum jme_smbcsr_bit_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SMBCSR_CNACK = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SMBCSR_RELOAD = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SMBCSR_EEPROMD = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SMBCSR_INITDONE = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SMBCSR_BUSY = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) enum jme_smbintf_bit_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SMBINTF_HWDATR = 0xFF000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SMBINTF_HWDATW = 0x00FF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SMBINTF_HWADDR = 0x0000FF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SMBINTF_HWRWN = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SMBINTF_HWCMD = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SMBINTF_FASTM = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SMBINTF_GPIOSCL = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SMBINTF_GPIOSDA = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SMBINTF_GPIOEN = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) enum jme_smbintf_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SMBINTF_HWRWN_READ = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) SMBINTF_HWRWN_WRITE = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) enum jme_smbintf_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SMBINTF_HWDATR_SHIFT = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SMBINTF_HWDATW_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) SMBINTF_HWADDR_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define JME_SMB_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define JME_EEPROM_MAGIC 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * Timer Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) enum jme_tmcsr_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) TMCSR_SWIT = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) TMCSR_EN = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) TMCSR_CNT = 0x00FFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * General Purpose REG-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) enum jme_gpreg0_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GPREG0_DISSH = 0xFF000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) GPREG0_PCIRLMT = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GPREG0_PCCNOMUTCLR = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GPREG0_LNKINTPOLL = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) GPREG0_PCCTMR = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GPREG0_PHYADDR = 0x0000001F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) enum jme_gpreg0_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GPREG0_DISSH_DW7 = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) GPREG0_DISSH_DW6 = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GPREG0_DISSH_DW5 = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GPREG0_DISSH_DW4 = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GPREG0_DISSH_DW3 = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GPREG0_DISSH_DW2 = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GPREG0_DISSH_DW1 = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) GPREG0_DISSH_DW0 = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GPREG0_DISSH_ALL = 0xFF000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GPREG0_PCIRLMT_8 = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GPREG0_PCIRLMT_6 = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GPREG0_PCIRLMT_5 = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GPREG0_PCIRLMT_4 = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GPREG0_PCCTMR_16ns = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GPREG0_PCCTMR_256ns = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GPREG0_PCCTMR_1us = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GPREG0_PCCTMR_1ms = 0x00000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) GPREG0_PHYADDR_1 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GPREG0_PCCTMR_1us |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GPREG0_PHYADDR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * General Purpose REG-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) enum jme_gpreg1_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GPREG1_RXCLKOFF = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GPREG1_PCREQN = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GPREG1_INTRDELAYUNIT = 0x00000018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GPREG1_INTRDELAYENABLE = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) enum jme_gpreg1_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GPREG1_INTDLYUNIT_16NS = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GPREG1_INTDLYUNIT_256NS = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GPREG1_INTDLYUNIT_1US = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GPREG1_INTDLYUNIT_16US = 0x00000018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GPREG1_INTDLYEN_1U = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GPREG1_INTDLYEN_2U = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GPREG1_INTDLYEN_3U = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GPREG1_INTDLYEN_4U = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GPREG1_INTDLYEN_5U = 0x00000005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GPREG1_INTDLYEN_6U = 0x00000006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GPREG1_INTDLYEN_7U = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GPREG1_DEFAULT = GPREG1_PCREQN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * Interrupt Status Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) enum jme_interrupt_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) INTR_SWINTR = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) INTR_TMINTR = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) INTR_LINKCH = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) INTR_PAUSERCV = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) INTR_MAGICRCV = 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) INTR_WAKERCV = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) INTR_PCCRX0TO = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) INTR_PCCRX1TO = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) INTR_PCCRX2TO = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) INTR_PCCRX3TO = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) INTR_PCCTXTO = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) INTR_PCCRX0 = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) INTR_PCCRX1 = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) INTR_PCCRX2 = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) INTR_PCCRX3 = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) INTR_PCCTX = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) INTR_RX3EMP = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) INTR_RX2EMP = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) INTR_RX1EMP = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) INTR_RX0EMP = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) INTR_RX3 = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) INTR_RX2 = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) INTR_RX1 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) INTR_RX0 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) INTR_TX7 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) INTR_TX6 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) INTR_TX5 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) INTR_TX4 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) INTR_TX3 = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) INTR_TX2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) INTR_TX1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) INTR_TX0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const u32 INTR_ENABLE = INTR_SWINTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) INTR_TMINTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) INTR_LINKCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) INTR_PCCRX0TO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) INTR_PCCRX0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) INTR_PCCTXTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) INTR_PCCTX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) INTR_RX0EMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * PCC Control Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) enum jme_pccrx_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PCCRXTO_MASK = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PCCRX_MASK = 0x0000FF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) enum jme_pcctx_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PCCTXTO_MASK = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PCCTX_MASK = 0x0000FF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PCCTX_QS_MASK = 0x000000FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) enum jme_pccrx_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PCCRXTO_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PCCRX_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) enum jme_pcctx_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PCCTXTO_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PCCTX_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) enum jme_pcctx_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PCCTXQ0_EN = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PCCTXQ1_EN = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PCCTXQ2_EN = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PCCTXQ3_EN = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PCCTXQ4_EN = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PCCTXQ5_EN = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PCCTXQ6_EN = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PCCTXQ7_EN = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * Chip Mode Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) enum jme_chipmode_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) CM_FPGAVER_MASK = 0xFFFF0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) CM_CHIPREV_MASK = 0x0000FF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) CM_CHIPMODE_MASK = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) enum jme_chipmode_shifts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) CM_FPGAVER_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) CM_CHIPREV_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * Aggressive Power Mode Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) enum jme_apmc_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) JME_APMC_PCIE_SD_EN = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) JME_APMC_PSEUDO_HP_EN = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) JME_APMC_EPIEN = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) JME_APMC_EPIEN_CTRL = 0x03000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) enum jme_apmc_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) JME_APMC_EPIEN_CTRL_EN = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #ifdef REG_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static char *MAC_REG_NAME[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "JME_PMCS"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static char *PE_REG_NAME[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "JME_SMBCSR", "JME_SMBINTF"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static char *MISC_REG_NAME[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "JME_PCCSRX0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static inline void reg_dbg(const struct jme_adapter *jme,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) const char *msg, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) const char *regname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) switch (reg & 0xF00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case 0x000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case 0x400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) regname = PE_REG_NAME[(reg & 0xFF) >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) case 0x800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) regname = PE_REG_NAME[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) msg, val, regname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static inline void reg_dbg(const struct jme_adapter *jme,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) const char *msg, u32 val, u32 reg) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * Read/Write MMaped I/O Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static inline u32 jread32(struct jme_adapter *jme, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return readl(jme->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) reg_dbg(jme, "REG WRITE", val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) writel(val, jme->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Read after write should cause flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) reg_dbg(jme, "REG WRITE FLUSH", val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) writel(val, jme->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) readl(jme->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * PHY Regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) enum jme_phy_reg17_bit_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PREG17_SPEED = 0xC000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PREG17_DUPLEX = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PREG17_SPDRSV = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PREG17_LNKUP = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PREG17_MDI = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) enum jme_phy_reg17_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PREG17_SPEED_10M = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PREG17_SPEED_100M = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PREG17_SPEED_1000M = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define BMSR_ANCOMP 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * Workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static inline int is_buggy250(unsigned short device, u8 chiprev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static inline int new_phy_power_ctrl(u8 chip_main_rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return chip_main_rev >= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * Function prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static int jme_set_link_ksettings(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) const struct ethtool_link_ksettings *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void jme_set_unicastaddr(struct net_device *netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static void jme_set_multi(struct net_device *netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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