Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/drivers/acorn/net/ether1.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1996 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Network driver for Acorn Ether1 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _LINUX_ether1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _LINUX_ether1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifdef __ETHER1_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* use 0 for production, 1 for verification, >2 for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #ifndef NET_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define NET_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define priv(dev)	((struct ether1_priv *)netdev_priv(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Page register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_PAGE	(priv(dev)->base + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_CONTROL	(priv(dev)->base + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CTRL_RST	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CTRL_LOOPBACK	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CTRL_CA		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CTRL_ACK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ETHER1_RAM	(priv(dev)->base + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* HW address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IDPROM_ADDRESS	(priv(dev)->base + 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct ether1_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int tx_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int tx_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	volatile unsigned int tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	volatile unsigned int rx_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	volatile unsigned int rx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned char bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned char resetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned char initialising : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned char restart      : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define I82586_NULL (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) typedef struct { /* tdr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned short tdr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned short tdr_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned short tdr_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned short tdr_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TDR_TIME	(0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TDR_SHORT	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TDR_OPEN	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TDR_XCVRPROB	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TDR_LNKOK	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) } tdr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) typedef struct { /* transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned short tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned short tx_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned short tx_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned short tx_tbdoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) } tx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) typedef struct { /* tbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned short tbd_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TBD_CNT		(0x3fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TBD_EOL		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned short tbd_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned short tbd_bufl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned short tbd_bufh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) } tbd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) typedef struct { /* rfd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned short rfd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RFD_NOEOF	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define RFD_FRAMESHORT	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RFD_DMAOVRN	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define RFD_NORESOURCES	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define RFD_ALIGNERROR	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RFD_CRCERROR	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define RFD_OK		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define RFD_FDCONSUMED	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define RFD_COMPLETE	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned short rfd_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define RFD_CMDSUSPEND	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define RFD_CMDEL	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned short rfd_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned short rfd_rbdoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned char  rfd_dest[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned char  rfd_src[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned short rfd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) } rfd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) typedef struct { /* rbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned short rbd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RBD_ACNT	(0x3fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RBD_ACNTVALID	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RBD_EOF		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned short rbd_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned short rbd_bufl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned short rbd_bufh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned short rbd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } rbd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) typedef struct { /* nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned short nop_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned short nop_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned short nop_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } nop_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) typedef struct { /* set multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned short mc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned short mc_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned short mc_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned short mc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned char  mc_addrs[1][6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } mc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) typedef struct { /* set address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned short sa_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned short sa_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned short sa_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned char  sa_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } sa_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) typedef struct { /* config command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned short cfg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned short cfg_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned short cfg_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned char  cfg_bytecnt;	/* size foll data: 4 - 12		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned char  cfg_fifolim;	/* FIFO threshold			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned char  cfg_byte8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CFG8_SRDY	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CFG8_SAVEBADF	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned char  cfg_byte9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CFG9_ADDRLEN(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CFG9_ADDRLENBUF	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CFG9_PREAMB2	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CFG9_PREAMB4	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CFG9_PREAMB8	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CFG9_PREAMB16	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CFG9_ILOOPBACK	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CFG9_ELOOPBACK	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned char  cfg_byte10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CFG10_LINPRI(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CFG10_ACR(x)	(x << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CFG10_BOFMET	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned char  cfg_ifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned char  cfg_slotl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned char  cfg_byte13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CFG13_SLOTH(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CFG13_RETRY(x)	(x << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned char  cfg_byte14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CFG14_PROMISC	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CFG14_DISBRD	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CFG14_MANCH	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CFG14_TNCRS	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CFG14_NOCRC	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CFG14_CRC16	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CFG14_BTSTF	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CFG14_FLGPAD	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned char  cfg_byte15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CFG15_CSTF(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CFG15_ICSS	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CFG15_CDTF(x)	(x << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CFG15_ICDS	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned short cfg_minfrmlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } cfg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) typedef struct { /* scb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned short scb_status;	/* status of 82586			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SCB_STRXMASK		(7 << 4)	/* Receive unit status		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SCB_STRXIDLE		(0 << 4)	/* Idle				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SCB_STRXSUSP		(1 << 4)	/* Suspended			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SCB_STRXNRES		(2 << 4)	/* No resources			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SCB_STRXRDY		(4 << 4)	/* Ready			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SCB_STCUMASK		(7 << 8)	/* Command unit status		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SCB_STCUIDLE		(0 << 8)	/* Idle				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SCB_STCUSUSP		(1 << 8)	/* Suspended			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SCB_STCUACTV		(2 << 8)	/* Active			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SCB_STRNR		(1 << 12)	/* Receive unit not ready	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SCB_STCNA		(1 << 13)	/* Command unit not ready	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SCB_STFR		(1 << 14)	/* Frame received		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SCB_STCX		(1 << 15)	/* Command completed		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned short scb_command;	/* Next command				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SCB_CMDRXSTART		(1 << 4)	/* Start (at rfa_offset)	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCB_CMDRXRESUME		(2 << 4)	/* Resume reception		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SCB_CMDRXSUSPEND	(3 << 4)	/* Suspend reception		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SCB_CMDRXABORT		(4 << 4)	/* Abort reception		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SCB_CMDCUCSTART		(1 << 8)	/* Start (at cbl_offset)	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCB_CMDCUCRESUME	(2 << 8)	/* Resume execution		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCB_CMDCUCSUSPEND	(3 << 8)	/* Suspend execution		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCB_CMDCUCABORT		(4 << 8)	/* Abort execution		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SCB_CMDACKRNR		(1 << 12)	/* Ack RU not ready		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCB_CMDACKCNA		(1 << 13)	/* Ack CU not ready		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCB_CMDACKFR		(1 << 14)	/* Ack Frame received		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SCB_CMDACKCX		(1 << 15)	/* Ack Command complete		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned short scb_cbl_offset;	/* Offset of first command unit		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	unsigned short scb_rfa_offset;	/* Offset of first receive frame area	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned short scb_crc_errors;	/* Properly aligned frame with CRC error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned short scb_aln_errors;	/* Misaligned frames			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned short scb_rsc_errors;	/* Frames lost due to no space		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned short scb_ovn_errors;	/* Frames lost due to slow bus		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } scb_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) typedef struct { /* iscp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned short iscp_busy;	/* set by CPU before CA			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned short iscp_offset;	/* offset of SCB			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned short iscp_basel;	/* base of SCB				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned short iscp_baseh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } iscp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)     /* this address must be 0xfff6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) typedef struct { /* scp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned short scp_sysbus;	/* bus size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCP_SY_16BBUS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SCP_SY_8BBUS	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned short scp_junk[2];	/* junk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned short scp_iscpl;	/* lower 16 bits of iscp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	unsigned short scp_iscph;	/* upper 16 bits of iscp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } scp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CMD_NOP			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CMD_SETADDRESS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CMD_CONFIG		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CMD_SETMULTICAST	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CMD_TX			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CMD_TDR			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CMD_DUMP		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CMD_DIAGNOSE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CMD_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CMD_INTR		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CMD_SUSP		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CMD_EOL			(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define STAT_COLLISIONS		(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define STAT_COLLEXCESSIVE	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STAT_COLLAFTERTX	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STAT_TXDEFERRED		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STAT_TXSLOWDMA		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define STAT_TXLOSTCTS		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STAT_NOCARRIER		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define STAT_FAIL		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STAT_ABORTED		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STAT_OK			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STAT_BUSY		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define STAT_COMPLETE		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * Ether1 card definitions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * FAST accesses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  *	+0	Page register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * 			16 pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  *	+4	Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  *			'1' = reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *			'2' = loopback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  *			'4' = CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *			'8' = int ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * RAM at address + 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * Pod. Prod id = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * Words after ID block [base + 8 words]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  *	+0 pcb issue (0x0c and 0xf3 invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *	+1 - +6 eth hw address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */