^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/ethernet/freescale/gianfar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Gianfar Ethernet Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on 8260_io/fcc_enet.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Maintainer: Kumar Gala
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Still left to do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * -Add support for module parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * -Add patch for ethtool phys id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __GIANFAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __GIANFAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ethtool_flow_spec_container {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ethtool_rx_flow_spec fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ethtool_rx_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* The maximum number of packets to be handled in one call of gfar_poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GFAR_DEV_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Length for FCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GMAC_FCB_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Length for TxPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GMAC_TXPAL_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Default padding amount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEFAULT_PADDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Number of bytes to align the rx bufs to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RXBUF_ALIGNMENT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRV_NAME "gfar-enet"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX_TX_QS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX_RX_QS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* MAXIMUM NUMBER OF GROUPS SUPPORTED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAXGROUPS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* These need to be powers of 2 for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEFAULT_TX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DEFAULT_RX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GFAR_RX_BUFF_ALLOC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GFAR_RX_MAX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GFAR_TX_MAX_RING_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FBTHR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEFAULT_RX_LFC_THR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEFAULT_LFC_PTVVAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GFAR_RXB_TRUESIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TX_RING_MOD_MASK(size) (size-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RX_RING_MOD_MASK(size) (size-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GFAR_JUMBO_FRAME_SIZE 9600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DEFAULT_FIFO_TX_THR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DEFAULT_FIFO_TX_STARVE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* The number of Exact Match registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GFAR_EM_NUM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Latency of interface clock in nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Interface clock latency , in this case, means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * time described by a value of 1 in the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * coalescing registers' time fields. Since those fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * refer to the time it takes for 64 clocks to pass, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * latencies are as such:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GFAR_GBIT_TIME 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GFAR_100_TIME 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GFAR_10_TIME 25600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DEFAULT_TX_COALESCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DEFAULT_TXCOUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DEFAULT_TXTIME 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DEFAULT_RXTIME 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DEFAULT_RX_COALESCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DEFAULT_RXCOUNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* TBI register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MII_TBICON 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* TBICON register bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TBICON_CLK_SELECT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* MAC register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MACCFG1_SOFT_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MACCFG1_RESET_RX_MC 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MACCFG1_RESET_TX_MC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MACCFG1_RESET_RX_FUN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MACCFG1_RESET_TX_FUN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MACCFG1_LOOPBACK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MACCFG1_RX_FLOW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MACCFG1_TX_FLOW 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MACCFG1_SYNCD_RX_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MACCFG1_RX_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MACCFG1_SYNCD_TX_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MACCFG1_TX_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MACCFG2_INIT_SETTINGS 0x00007205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MACCFG2_FULL_DUPLEX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MACCFG2_IF 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MACCFG2_MII 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MACCFG2_GMII 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MACCFG2_HUGEFRAME 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MACCFG2_LENGTHCHECK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MACCFG2_MPEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ECNTRL_FIFM 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ECNTRL_INIT_SETTINGS 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ECNTRL_TBI_MODE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ECNTRL_REDUCED_MODE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ECNTRL_R100 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ECNTRL_REDUCED_MII_MODE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ECNTRL_SGMII_MODE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MINFLR_INIT_SETTINGS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Tqueue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TQUEUE_EN0 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TQUEUE_EN1 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TQUEUE_EN2 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TQUEUE_EN3 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TQUEUE_EN4 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TQUEUE_EN5 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TQUEUE_EN6 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TQUEUE_EN7 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TQUEUE_EN_ALL 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TR03WT_WT0_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TR03WT_WT1_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TR03WT_WT2_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TR03WT_WT3_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TR47WT_WT4_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TR47WT_WT5_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TR47WT_WT6_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TR47WT_WT7_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Rqueue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RQUEUE_EX0 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RQUEUE_EX1 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RQUEUE_EX2 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RQUEUE_EX3 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RQUEUE_EX4 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RQUEUE_EX5 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RQUEUE_EX6 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RQUEUE_EX7 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RQUEUE_EX_ALL 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RQUEUE_EN0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RQUEUE_EN1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RQUEUE_EN2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RQUEUE_EN3 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RQUEUE_EN4 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RQUEUE_EN5 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RQUEUE_EN6 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RQUEUE_EN7 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RQUEUE_EN_ALL 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Init to do tx snooping for buffers and descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DMACTRL_INIT_SETTINGS 0x000000c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DMACTRL_GRS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DMACTRL_GTS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TSTAT_CLEAR_THALT_ALL 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TSTAT_CLEAR_THALT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TSTAT_CLEAR_THALT0 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TSTAT_CLEAR_THALT1 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TSTAT_CLEAR_THALT2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TSTAT_CLEAR_THALT3 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TSTAT_CLEAR_THALT4 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TSTAT_CLEAR_THALT5 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TSTAT_CLEAR_THALT6 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TSTAT_CLEAR_THALT7 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Interrupt coalescing macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IC_ICEN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IC_ICFT_MASK 0x1fe00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IC_ICFT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define mk_ic_icft(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IC_ICTT_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define mk_ic_value(count, time) (IC_ICEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mk_ic_icft(count) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mk_ic_ictt(time))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IC_ICFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RCTRL_TS_ENABLE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RCTRL_PAL_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RCTRL_LFC 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RCTRL_VLEX 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RCTRL_FILREN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RCTRL_GHTX 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RCTRL_IPCSEN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RCTRL_TUCSEN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define RCTRL_PRSDEP_MASK 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RCTRL_PRSDEP_INIT 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define RCTRL_PRSFM 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RCTRL_PROM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define RCTRL_EMEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RCTRL_TUCSEN | RCTRL_FILREN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RCTRL_PRSDEP_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RCTRL_EXTHASH (RCTRL_GHTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RSTAT_CLEAR_RHALT 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RSTAT_CLEAR_RXF0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RSTAT_RXF_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TCTRL_IPCSEN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TCTRL_TUCSEN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TCTRL_VLINS 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TCTRL_THDF 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TCTRL_RFCPAUSE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TCTRL_TFCPAUSE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TCTRL_TXSCHED_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TCTRL_TXSCHED_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* priority scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TCTRL_TXSCHED_PRIO 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* weighted round-robin scheduling (WRRS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TCTRL_TXSCHED_WRRS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* default WRRS weight and policy setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * tailored to the tr03wt and tr47wt registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * equal weight for all Tx Qs, measured in 64byte units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DEFAULT_WRRS_WEIGHT 0x18181818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IEVENT_INIT_CLEAR 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IEVENT_BABR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IEVENT_RXC 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IEVENT_BSY 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IEVENT_EBERR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IEVENT_MSRO 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IEVENT_GTSC 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IEVENT_BABT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IEVENT_TXC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IEVENT_TXE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IEVENT_TXB 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IEVENT_TXF 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IEVENT_LC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IEVENT_CRL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IEVENT_XFUN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IEVENT_RXB0 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IEVENT_MAG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IEVENT_GRSC 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IEVENT_RXF0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IEVENT_FGPI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IEVENT_FIR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IEVENT_FIQ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IEVENT_DPE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IEVENT_PERR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IEVENT_ERR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) | IEVENT_MAG | IEVENT_BABR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMASK_INIT_CLEAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMASK_BABR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMASK_RXC 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMASK_BSY 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMASK_EBERR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMASK_MSRO 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMASK_GTSC 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMASK_BABT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMASK_TXC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMASK_TXEEN 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMASK_TXBEN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMASK_TXFEN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMASK_LC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMASK_CRL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMASK_XFUN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMASK_RXB0 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMASK_MAG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMASK_GRSC 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMASK_RXFEN0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMASK_FGPI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMASK_FIR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMASK_FIQ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMASK_DPE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMASK_PERR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) | IMASK_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Attribute fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* This enables rx snooping for buffers and descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ATTR_BDSTASH 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ATTR_BUFSTASH 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ATTR_SNOOPING 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ATTR_INIT_SETTINGS ATTR_SNOOPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ATTRELI_INIT_SETTINGS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ATTRELI_EL_MASK 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define ATTRELI_EL(x) (x << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ATTRELI_EI_MASK 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ATTRELI_EI(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BD_LFLAG(flags) ((flags) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define BD_LENGTH_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FPR_FILER_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MAX_FILER_IDX 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* This default RIR value directly corresponds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * to the 3-bit hash value generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DEFAULT_8RXQ_RIR0 0x05397700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Map even hash values to Q0, and odd ones to Q1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DEFAULT_2RXQ_RIR0 0x04104100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* RQFCR register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define RQFCR_GPI 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define RQFCR_HASHTBL_Q 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RQFCR_HASHTBL_0 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define RQFCR_HASHTBL_1 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RQFCR_HASHTBL_2 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RQFCR_HASHTBL_3 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RQFCR_HASH 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define RQFCR_QUEUE 0x0000FC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define RQFCR_CLE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define RQFCR_RJE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define RQFCR_AND 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RQFCR_CMP_EXACT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RQFCR_CMP_MATCH 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RQFCR_CMP_NOEXACT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RQFCR_CMP_NOMATCH 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* RQFCR PID values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define RQFCR_PID_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define RQFCR_PID_PARSE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define RQFCR_PID_ARB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define RQFCR_PID_DAH 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define RQFCR_PID_DAL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define RQFCR_PID_SAH 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RQFCR_PID_SAL 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define RQFCR_PID_ETY 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define RQFCR_PID_VID 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define RQFCR_PID_PRI 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define RQFCR_PID_TOS 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RQFCR_PID_L4P 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RQFCR_PID_DIA 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define RQFCR_PID_SIA 0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define RQFCR_PID_DPT 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RQFCR_PID_SPT 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* RQFPR when PID is 0x0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define RQFPR_HDR_GE_512 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define RQFPR_LERR 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define RQFPR_RAR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define RQFPR_RARQ 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define RQFPR_AR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define RQFPR_ARQ 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define RQFPR_EBC 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define RQFPR_VLN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define RQFPR_CFI 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define RQFPR_JUM 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define RQFPR_IPF 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define RQFPR_FIF 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define RQFPR_IPV4 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define RQFPR_IPV6 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define RQFPR_ICC 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define RQFPR_ICV 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define RQFPR_TCP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define RQFPR_UDP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define RQFPR_TUC 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define RQFPR_TUV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define RQFPR_PER 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define RQFPR_EER 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* TxBD status field bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TXBD_READY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TXBD_PADCRC 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TXBD_WRAP 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TXBD_INTERRUPT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TXBD_LAST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TXBD_CRC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define TXBD_DEF 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TXBD_HUGEFRAME 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TXBD_LATECOLLISION 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TXBD_RETRYLIMIT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TXBD_RETRYCOUNTMASK 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TXBD_UNDERRUN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TXBD_TOE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Tx FCB param bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define TXFCB_VLN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define TXFCB_IP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define TXFCB_IP6 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define TXFCB_TUP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define TXFCB_UDP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TXFCB_CIP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TXFCB_CTU 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TXFCB_NPH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* RxBD status field bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RXBD_EMPTY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RXBD_RO1 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RXBD_WRAP 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RXBD_INTERRUPT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define RXBD_LAST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RXBD_FIRST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RXBD_MISS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define RXBD_BROADCAST 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RXBD_MULTICAST 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define RXBD_LARGE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RXBD_NONOCTET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RXBD_SHORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RXBD_CRCERR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define RXBD_OVERRUN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define RXBD_TRUNCATED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define RXBD_STATS 0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) | RXBD_CRCERR | RXBD_OVERRUN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) | RXBD_TRUNCATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Rx FCB status field bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define RXFCB_VLN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define RXFCB_IP 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define RXFCB_IP6 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define RXFCB_TUP 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define RXFCB_CIP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define RXFCB_CTU 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define RXFCB_EIP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define RXFCB_ETU 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define RXFCB_CSUM_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define RXFCB_PERR_MASK 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define RXFCB_PERR_BADL3 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define GFAR_WOL_MAGIC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define GFAR_WOL_FILER_UCAST 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct txbd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __be16 status; /* Status Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __be16 length; /* Buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __be32 lstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __be32 bufPtr; /* Buffer Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct txfcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 ptp; /* Flag to enable tx timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 l4os; /* Level 4 Header Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 l3os; /* Level 3 Header Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __be16 phcs; /* Pseudo-header Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __be16 vlctl; /* VLAN control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct rxbd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __be16 status; /* Status Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __be16 length; /* Buffer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __be32 lstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __be32 bufPtr; /* Buffer Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct rxfcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __be16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 rq; /* Receive Queue index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 pro; /* Layer 4 Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) __be16 vlctl; /* VLAN control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct gianfar_skb_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct rmon_mib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 rbyt; /* 0x.69c - Receive Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 rdrp; /* 0x.6dc - Receive Drop Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 car1; /* 0x.730 - Carry Register One */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 car2; /* 0x.734 - Carry Register Two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 cam1; /* 0x.738 - Carry Mask Register One */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 cam2; /* 0x.73c - Carry Mask Register Two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct gfar_extra_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) atomic64_t rx_alloc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) atomic64_t rx_large;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) atomic64_t rx_short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) atomic64_t rx_nonoctet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) atomic64_t rx_crcerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) atomic64_t rx_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) atomic64_t rx_bsy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) atomic64_t rx_babr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) atomic64_t rx_trunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) atomic64_t eberr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) atomic64_t tx_babt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) atomic64_t tx_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) atomic64_t tx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define GFAR_EXTRA_STATS_LEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Number of stats exported via ethtool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct gfar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 tsec_id; /* 0x.000 - Controller ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 tsec_id2; /* 0x.004 - Controller ID2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 res1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 ievent; /* 0x.010 - Interrupt Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 imask; /* 0x.014 - Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 edis; /* 0x.018 - Error Disabled Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 emapg; /* 0x.01c - Group Error mapping register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 ecntrl; /* 0x.020 - Ethernet Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 minflr; /* 0x.024 - Minimum Frame Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 ptv; /* 0x.028 - Pause Time Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 dmactrl; /* 0x.02c - DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 tbipa; /* 0x.030 - TBI PHY Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 res2[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) shutoff register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u8 res3[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 res4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 res5[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 tctrl; /* 0x.100 - Transmit Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 tstat; /* 0x.104 - Transmit Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 dfvlan; /* 0x.108 - Default VLAN Control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 tqueue; /* 0x.114 - Transmit queue control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 res7[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u8 res8[52];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 res9a[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 res9b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 res9c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 res9d[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 res9e[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 res9f[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 res9g[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 res9h[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u8 res9[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 tbaseh; /* 0x.200 - TxBD base address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 res10a[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u8 res10b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 res10c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u8 res10d[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u8 res10e[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 res10f[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u8 res10g[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 res10[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 rctrl; /* 0x.300 - Receive Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 rstat; /* 0x.304 - Receive Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u8 res12[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 rqueue; /* 0x.314 - Receive queue control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 rir0; /* 0x.318 - Ring mapping register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 rir1; /* 0x.31c - Ring mapping register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 rir2; /* 0x.320 - Ring mapping register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 rir3; /* 0x.324 - Ring mapping register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 res13[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 rbifx; /* 0x.330 - Receive bit field extract control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 rqfar; /* 0x.334 - Receive queue filing table address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u8 res14[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 res15a[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 res15b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 res15c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 res15d[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u8 res15e[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u8 res15f[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 res15g[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u8 res15h[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u8 res16[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 rbaseh; /* 0x.400 - RxBD base address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u8 res17a[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 res17b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 res17c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 res17d[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 res17e[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u8 res17f[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u8 res17g[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u8 res17[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 hafdup; /* 0x.50c - Half Duplex Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u8 res18[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u32 ifctrl; /* 0x.538 - Interface control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 ifstat; /* 0x.53c - Interface Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u8 res20[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct rmon_mib rmon; /* 0x.680-0x.73c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u8 res21[188];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 res22[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 gaddr0; /* 0x.880 - Group address register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 gaddr1; /* 0x.884 - Group address register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 gaddr2; /* 0x.888 - Group address register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 gaddr3; /* 0x.88c - Group address register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 gaddr4; /* 0x.890 - Group address register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 gaddr5; /* 0x.894 - Group address register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 gaddr6; /* 0x.898 - Group address register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 gaddr7; /* 0x.89c - Group address register 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u8 res23a[352];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 fifocfg; /* 0x.a00 - FIFO interface config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 res23b[252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 res23c[248];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 attr; /* 0x.bf8 - Attributes Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 res24[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u8 res24a[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 res24b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 res24c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 res24d[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 res24e[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 res24f[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 res24g[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 res24h[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 res24x[556];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u8 res25[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 res26[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u8 res27[208];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Flags related to gianfar device features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #if (MAXGROUPS == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DEFAULT_MAPPING 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define DEFAULT_MAPPING 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define ISRG_RR0 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define ISRG_TR0 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* The same driver can operate in two modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* SQ_SG_MODE: Single Queue Single Group Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * (Backward compatible mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * MQ_MG_MODE: Multi Queue Multi Group mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SQ_SG_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MQ_MG_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* GFAR_SQ_POLLING: Single Queue NAPI polling mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * The driver supports a single pair of RX/Tx queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * per interrupt group (Rx/Tx int line). MQ_MG mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * devices have 2 interrupt groups, so the device will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * have a total of 2 Tx and 2 Rx queues in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * GFAR_MQ_POLLING: Multi Queue NAPI polling mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * The driver supports all the 8 Rx and Tx HW queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * each queue mapped by the Device Tree to one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * the 2 interrupt groups. This mode implies significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * processing overhead (CPU and controller level).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) enum gfar_poll_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GFAR_SQ_POLLING = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) GFAR_MQ_POLLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * Per TX queue stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct tx_q_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned long tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned long tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * struct gfar_priv_tx_q - per tx queue structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * @txlock: per queue tx spin lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * @tx_skbuff:skb pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * @skb_curtx: to be used skb pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * @skb_dirtytx:the last used skb pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * @stats: bytes/packets stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * @qindex: index of this queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * @dev: back pointer to the dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * @grp: back pointer to the group to which this queue belongs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * @tx_bd_base: First tx buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * @cur_tx: Next free ring entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * @dirty_tx: First buffer in line to be transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * @tx_ring_size: Tx ring size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * @num_txbdfree: number of free TxBds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * @txcoalescing: enable/disable tx coalescing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * @txic: transmit interrupt coalescing value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * @txcount: coalescing value if based on tx frame count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * @txtime: coalescing value if based on time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct gfar_priv_tx_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* cacheline 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct txbd8 *tx_bd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct txbd8 *cur_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned int num_txbdfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned short skb_curtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned short tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct tx_q_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct gfar_priv_grp *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* cacheline 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct sk_buff **tx_skbuff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct txbd8 *dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned short skb_dirtytx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned short qindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Configuration info for the coalescing features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) unsigned int txcoalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) unsigned long txic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dma_addr_t tx_bd_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * Per RX queue stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct rx_q_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned long rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned long rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned long rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct gfar_rx_buff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned int page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * struct gfar_priv_rx_q - per rx queue structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * @rx_buff: Array of buffer info metadata structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * @rx_bd_base: First rx buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * @next_to_use: index of the next buffer to be alloc'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * @next_to_clean: index of the next buffer to be cleaned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * @qindex: index of this queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * @ndev: back pointer to net_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * @rx_ring_size: Rx ring size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * @rxcoalescing: enable/disable rx-coalescing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @rxic: receive interrupt coalescing vlaue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct gfar_priv_rx_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct rxbd8 *rx_bd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u16 rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u16 qindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct gfar_priv_grp *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u16 next_to_clean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u16 next_to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u16 next_to_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct rx_q_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 __iomem *rfbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned char rxcoalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned long rxic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dma_addr_t rx_bd_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) enum gfar_irqinfo_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GFAR_TX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GFAR_RX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GFAR_ER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GFAR_NUM_IRQS = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct gfar_irqinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) char name[GFAR_INT_NAME_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * struct gfar_priv_grp - per group structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * @napi: the napi poll function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * @priv: back pointer to the priv structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * @regs: the ioremapped register space for this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * @irqinfo: TX/RX/ER irq data for this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct gfar_priv_grp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) spinlock_t grplock __aligned(SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct napi_struct napi_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct napi_struct napi_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct gfar __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct gfar_priv_tx_q *tx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct gfar_priv_rx_q *rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) unsigned int tstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned int rstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct gfar_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) unsigned long num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) unsigned long tx_bit_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned long num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned long rx_bit_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define gfar_irq(grp, ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ((grp)->irqinfo[GFAR_##ID])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) enum gfar_errata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) GFAR_ERRATA_74 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GFAR_ERRATA_76 = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) GFAR_ERRATA_A002 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) enum gfar_dev_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GFAR_DOWN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) GFAR_RESETTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* Struct stolen almost completely (and shamelessly) from the FCC enet source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * (Ok, that's not so true anymore, but there is a family resemblance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * and tx_bd_base always point to the currently available buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * The dirty_tx tracks the current buffer that is being sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * controller. The cur_tx and dirty_tx are equal under both completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * empty and completely full conditions. The empty/ready indicator in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * the buffer descriptor determines the actual condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct gfar_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) enum gfar_errata errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u16 uses_rxfcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u16 padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* HW time stamping enabled flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int hwts_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int hwts_tx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct gfar_priv_grp gfargrp[MAXGROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) unsigned short mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) unsigned short poll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned int num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) unsigned int num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) unsigned int num_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int tx_actual_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Network Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct gfar_extra_stats extra_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* PHY stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) phy_interface_t interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct device_node *phy_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct device_node *tbi_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int oldspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int oldduplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int oldlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) uint32_t msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct platform_device *ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) extended_hash:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) bd_stash_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) rx_filer_enable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Enable priorty based Tx scheduling in Hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) prio_sched_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Flow control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pause_aneg_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) tx_pause_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) rx_pause_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* The total tx and rx ring size for the enabled queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned int total_tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned int total_rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u32 rqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 tqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* RX per device parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned int rx_stash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) unsigned int rx_stash_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 cur_filer_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* RX queue filer rule set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct ethtool_rx_list rx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct mutex rx_queue_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Hash registers and their width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u32 __iomem *hash_regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int hash_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* wake-on-lan settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u16 wol_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) u16 wol_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*Filer table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static inline int gfar_has_errata(struct gfar_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) enum gfar_errata err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return priv->errata & err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static inline u32 gfar_read(unsigned __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) val = ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static inline void gfar_write(unsigned __iomem *addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static inline void gfar_write_filer(struct gfar_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) unsigned int far, unsigned int fcr, unsigned int fpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct gfar __iomem *regs = priv->gfargrp[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) gfar_write(®s->rqfar, far);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) gfar_write(®s->rqfcr, fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) gfar_write(®s->rqfpr, fpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static inline void gfar_read_filer(struct gfar_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) unsigned int far, unsigned int *fcr, unsigned int *fpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct gfar __iomem *regs = priv->gfargrp[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) gfar_write(®s->rqfar, far);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *fcr = gfar_read(®s->rqfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) *fpr = gfar_read(®s->rqfpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static inline void gfar_write_isrg(struct gfar_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct gfar __iomem *regs = priv->gfargrp[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 __iomem *baddr = ®s->isrg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 isrg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int grp_idx, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) isrg |= (ISRG_RR0 >> i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) isrg |= (ISRG_TR0 >> i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gfar_write(baddr, isrg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) baddr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) isrg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static inline int gfar_is_dma_stopped(struct gfar_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct gfar __iomem *regs = priv->gfargrp[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) (IEVENT_GRSC | IEVENT_GTSC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct gfar __iomem *regs = priv->gfargrp[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return gfar_read(®s->ievent) & IEVENT_GRSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static inline void gfar_wmb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #if defined(CONFIG_PPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* The powerpc-specific eieio() is used, as wmb() has too strong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * semantics (it requires synchronization between cacheable and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * uncacheable mappings, which eieio() doesn't provide and which we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * don't need), thus requiring a more expensive sync instruction. At
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * some point, the set of architecture-independent barrier functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * should be expanded to include weaker barriers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) wmb(); /* order write acesses for BD (or FCB) fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 lstatus = be32_to_cpu(bdp->lstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) lstatus &= BD_LFLAG(TXBD_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) bdp->lstatus = cpu_to_be32(lstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (rxq->next_to_clean > rxq->next_to_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return rxq->next_to_clean - rxq->next_to_use - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct rxbd8 *bdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u32 bdp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) bdp = &rxq->rx_bd_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return bdp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) int startup_gfar(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) void stop_gfar(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) void gfar_mac_reset(struct gfar_private *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int gfar_set_features(struct net_device *dev, netdev_features_t features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) extern const struct ethtool_ops gfar_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define RQFCR_PID_PRI_MASK 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define RQFCR_PID_L4P_MASK 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define RQFCR_PID_VID_MASK 0xFFFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define RQFCR_PID_PORT_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define RQFCR_PID_MAC_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Represents a receive filer table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct gfar_filer_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* The 20 additional entries are a shadow for one extra element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct filer_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #endif /* __GIANFAR_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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