^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 2000-2001, Lineo (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef FEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/net_tstamp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Just figures, Motorola would have to change the offsets for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * registers in the same peripheral device on different models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * of the ColdFire!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FEC_IEVENT 0x004 /* Interrupt event reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FEC_IMASK 0x008 /* Interrupt mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FEC_ECNTRL 0x024 /* Ethernet control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FEC_MII_DATA 0x040 /* MII manage frame reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FEC_MII_SPEED 0x044 /* MII speed control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FEC_R_CNTRL 0x084 /* Receive control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FEC_OPD 0x0ec /* Opcode + Pause duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FEC_RACC 0x1c4 /* Receive Accelerator function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BM_MIIGSK_CFGR_MII 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BM_MIIGSK_CFGR_RMII 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BM_MIIGSK_CFGR_FRCONT_10M 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RMON_T_PACKETS 0x204 /* RMON TX packet count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RMON_T_COL 0x224 /* RMON TX collision count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RMON_T_OCTETS 0x244 /* RMON TX octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RMON_R_PACKETS 0x284 /* RMON RX packet count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RMON_R_RESVD_O 0x2a4 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FEC_ECNTRL 0x000 /* Ethernet control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FEC_IEVENT 0x004 /* Interrupt even reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FEC_IMASK 0x008 /* Interrupt mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FEC_IVEC 0x00c /* Interrupt vec status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FEC_MII_DATA 0x040 /* MII manage frame reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FEC_MII_SPEED 0x044 /* MII speed control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FEC_R_FSTART 0x090 /* FIFO receive start reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FEC_R_CNTRL 0x104 /* Receive control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FEC_X_CNTRL 0x144 /* Transmit Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FEC_R_DES_START_1 FEC_R_DES_START_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FEC_R_DES_START_2 FEC_R_DES_START_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FEC_X_DES_START_1 FEC_X_DES_START_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FEC_X_DES_START_2 FEC_X_DES_START_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Not existed in real chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Just for pass build.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FEC_RCMR_1 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FEC_RCMR_2 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FEC_DMA_CFG_1 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FEC_DMA_CFG_2 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FEC_TXIC0 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FEC_TXIC1 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FEC_TXIC2 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FEC_RXIC0 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FEC_RXIC1 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FEC_RXIC2 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif /* CONFIG_M5272 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Define the buffer descriptor structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Evidently, ARM SoCs have the FEC block generated in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * little endian mode so adjust endianness accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define fec32_to_cpu le32_to_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define fec16_to_cpu le16_to_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define cpu_to_fec32 cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define cpu_to_fec16 cpu_to_le16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define __fec32 __le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define __fec16 __le16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct bufdesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __fec16 cbd_datlen; /* Data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __fec16 cbd_sc; /* Control and status info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __fec32 cbd_bufaddr; /* Buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define fec32_to_cpu be32_to_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define fec16_to_cpu be16_to_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define cpu_to_fec32 cpu_to_be32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define cpu_to_fec16 cpu_to_be16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define __fec32 __be32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define __fec16 __be16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct bufdesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __fec16 cbd_sc; /* Control and status info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __fec16 cbd_datlen; /* Data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __fec32 cbd_bufaddr; /* Buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct bufdesc_ex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct bufdesc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __fec32 cbd_esc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __fec32 cbd_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __fec32 cbd_bdu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __fec32 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __fec16 res0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * The following definitions courtesy of commproc.h, which where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BD_SC_BR ((ushort)0x0020) /* Break received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BD_SC_FR ((ushort)0x0010) /* Framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BD_SC_PR ((ushort)0x0008) /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BD_SC_OV ((ushort)0x0002) /* Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define BD_SC_CD ((ushort)0x0001) /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Buffer descriptor control/status used by Ethernet receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BD_ENET_RX_EMPTY ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BD_ENET_RX_WRAP ((ushort)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BD_ENET_RX_INTR ((ushort)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BD_ENET_RX_LAST ((ushort)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BD_ENET_RX_FIRST ((ushort)0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BD_ENET_RX_MISS ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BD_ENET_RX_LG ((ushort)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BD_ENET_RX_NO ((ushort)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BD_ENET_RX_SH ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BD_ENET_RX_CR ((ushort)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define BD_ENET_RX_OV ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define BD_ENET_RX_CL ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Enhanced buffer descriptor control/status used by Ethernet receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define BD_ENET_RX_VLAN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Buffer descriptor control/status used by Ethernet transmit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BD_ENET_TX_READY ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BD_ENET_TX_PAD ((ushort)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BD_ENET_TX_WRAP ((ushort)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define BD_ENET_TX_INTR ((ushort)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define BD_ENET_TX_LAST ((ushort)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BD_ENET_TX_TC ((ushort)0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define BD_ENET_TX_DEF ((ushort)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define BD_ENET_TX_HB ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define BD_ENET_TX_LC ((ushort)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BD_ENET_TX_RL ((ushort)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define BD_ENET_TX_RCMASK ((ushort)0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BD_ENET_TX_UN ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define BD_ENET_TX_CSL ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* enhanced buffer descriptor control/status used by Ethernet transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BD_ENET_TX_INT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BD_ENET_TX_TS 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BD_ENET_TX_PINS 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BD_ENET_TX_IINS 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* This device has up to three irqs on some platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define FEC_IRQ_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Maximum number of queues supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * User can point the queue number that is less than or equal to 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FEC_ENET_MAX_TX_QS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define FEC_ENET_MAX_RX_QS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (((X) == 2) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FEC_R_DES_START_2 : FEC_R_DES_START_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (((X) == 2) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FEC_X_DES_START_2 : FEC_X_DES_START_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (((X) == 2) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DMA_CLASS_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IDLE_SLOPE_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IDLE_SLOPE(X) (((X) == 1) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RCMR_MATCHEN (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* The number of Tx and Rx buffers. These are allocated from the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * pool. The code may assume these are power of two, so it it best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * to keep them that size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * We don't need to allocate pages for the transmitter. We just use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * the skbuffer directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FEC_ENET_RX_PAGES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FEC_ENET_RX_FRSIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FEC_ENET_TX_FRSIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TX_RING_SIZE 512 /* Must be power of two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TX_RING_MOD_MASK 511 /* for this to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define BD_ENET_RX_INT 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BD_ENET_RX_PTP ((ushort)0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BD_ENET_RX_ICE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BD_ENET_RX_PCR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Interrupt events/masks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define FEC_ENET_RXF_GET(X) (((X) == 0) ? FEC_ENET_RXF_0 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (((X) == 1) ? FEC_ENET_RXF_1 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FEC_ENET_RXF_2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define FEC_ENET_TS_AVAIL ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FEC_ENET_TS_TIMER ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* ENET interrupt coalescing macro define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define FEC_ITR_CLK_SEL (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define FEC_ITR_EN (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define FEC_ITR_ICTT(X) ((X) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define FEC_VLAN_TAG_LEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define FEC_ETHTYPE_LEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Controller is ENET-MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define FEC_QUIRK_ENET_MAC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Controller needs driver to swap frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define FEC_QUIRK_SWAP_FRAME (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Controller uses gasket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FEC_QUIRK_USE_GASKET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Controller has GBIT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define FEC_QUIRK_HAS_GBIT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Controller has extend desc buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Controller has hardware checksum support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define FEC_QUIRK_HAS_CSUM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Controller has hardware vlan support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define FEC_QUIRK_HAS_VLAN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* ENET IP errata ERR006358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * detected as not set during a prior frame transmission, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * frames not being transmitted until there is a 0-to-1 transition on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * ENET_TDAR[TDAR].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define FEC_QUIRK_ERR006358 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* ENET IP hw AVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * - Two class indicators on receive with configurable priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * - Two class indicators and line speed timer on transmit allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * implementation class credit based shapers externally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * - Additional DMA registers provisioned to allow managing up to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * independent rings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define FEC_QUIRK_HAS_AVB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* There is a TDAR race condition for mutliQ when the software sets TDAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * The issue exist at i.MX6SX enet IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define FEC_QUIRK_ERR007885 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * After set ENET_ATCR[Capture], there need some time cycles before the counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * value is capture in the register clock domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * The wait-time-cycles is at least 6 clock cycles of the slower clock between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * (40ns * 6).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define FEC_QUIRK_BUG_CAPTURE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Controller has only one MDIO bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define FEC_QUIRK_SINGLE_MDIO (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Controller supports RACC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define FEC_QUIRK_HAS_RACC (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Controller supports interrupt coalesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define FEC_QUIRK_HAS_COALESCE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Interrupt doesn't wake CPU from deep idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define FEC_QUIRK_ERR006687 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* The MIB counters should be cleared and enabled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * initialisation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define FEC_QUIRK_MIB_CLEAR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * those FIFO receive registers are resolved in other platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FEC_QUIRK_HAS_FRREG (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * the generation of an MII event. This must be avoided in the older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * FEC blocks where it will stop MII events being generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define FEC_QUIRK_CLEAR_SETUP_MII (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct bufdesc_prop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Address of Rx and Tx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct bufdesc *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct bufdesc *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct bufdesc *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void __iomem *reg_desc_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned short ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned char dsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned char dsize_log2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct fec_enet_priv_tx_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct bufdesc_prop bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned char *tx_bounce[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct sk_buff *tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned short tx_stop_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned short tx_wake_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct bufdesc *dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) char *tso_hdrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dma_addr_t tso_hdrs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct fec_enet_priv_rx_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct bufdesc_prop bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct sk_buff *rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct fec_stop_mode_gpr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * tx_bd_base always point to the base of the buffer descriptors. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * cur_rx and cur_tx point to the currently available buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * The dirty_tx tracks the current buffer that is being sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * controller. The cur_tx and dirty_tx are equal under both completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * empty and completely full conditions. The empty/ready indicator in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * the buffer descriptor determines the actual condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct fec_enet_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Hardware registers of the FEC device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void __iomem *hwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct clk *clk_enet_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct clk *clk_ptp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bool ptp_clk_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct mutex ptp_clk_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* The saved address of a sent-in-place packet/buffer, for skfree(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int total_tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int total_rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Phylib and MDIO interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) uint phy_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phy_interface_t phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct device_node *phy_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int irq[FEC_IRQ_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool bufdesc_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int pause_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int wol_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int csum_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct work_struct tx_timeout_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct ptp_clock_info ptp_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long last_overflow_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spinlock_t tmreg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct cyclecounter cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct timecounter tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int rx_hwtstamp_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 base_incval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 cycle_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int hwts_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int hwts_tx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct delayed_work time_keep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct regulator *reg_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct fec_stop_mode_gpr stop_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int tx_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int rx_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* hw interrupt coalesce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int rx_pkts_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int rx_time_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int tx_pkts_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int tx_time_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int itr_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* ptp clock period in ns*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int ptp_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* pps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int pps_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int reload_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int pps_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int next_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u64 ethtool_stats[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void fec_ptp_init(struct platform_device *pdev, int irq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void fec_ptp_stop(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) void fec_ptp_start_cyclecounter(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void fec_ptp_disable_hwts(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif /* FEC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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