^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Dave DNET Ethernet Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DNET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DNET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DRV_NAME "dnet"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PFX DRV_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Register access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define dnet_writel(port, value, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) writel((value), (port)->regs + DNET_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* ALL DNET FIFO REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DNET_VERCAPS 0x100 /* VERCAPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DNET_INTR_SRC 0x104 /* INTR_SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DNET_INTR_ENB 0x108 /* INTR_ENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DNET_RX_STATUS 0x10C /* RX_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DNET_TX_STATUS 0x110 /* TX_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DNET_SYS_CTL 0x124 /* SYS_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* ALL DNET MAC REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* ALL DNET RX STATISTICS COUNTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DNET_RX_PKT_IGNR_CNT 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DNET_RX_LEN_CHK_ERR_CNT 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DNET_RX_LNG_FRM_CNT 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DNET_RX_SHRT_FRM_CNT 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DNET_RX_IPG_VIOL_CNT 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DNET_RX_CRC_ERR_CNT 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DNET_RX_OK_PKT_CNT 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DNET_RX_CTL_FRM_CNT 0x31C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DNET_RX_PAUSE_FRM_CNT 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DNET_RX_MULTICAST_CNT 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DNET_RX_BROADCAST_CNT 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DNET_RX_VLAN_TAG_CNT 0x32C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DNET_RX_PRE_SHRINK_CNT 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DNET_RX_DRIB_NIB_CNT 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DNET_RX_UNSUP_OPCD_CNT 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DNET_RX_BYTE_CNT 0x33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* DNET TX STATISTICS COUNTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DNET_TX_UNICAST_CNT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DNET_TX_PAUSE_FRM_CNT 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DNET_TX_MULTICAST_CNT 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DNET_TX_BRDCAST_CNT 0x40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DNET_TX_VLAN_TAG_CNT 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DNET_TX_BAD_FCS_CNT 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DNET_TX_JUMBO_CNT 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DNET_TX_BYTE_CNT 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* SOME INTERNAL MAC-CORE REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DNET_INTERNAL_MODE_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DNET_INTERNAL_IGP_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DNET_INTERNAL_TX_RX_STS_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DNET_INTERNAL_WRITE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* MAC-CORE REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* MAC-CORE MODE REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DNET_INTERNAL_MODE_GBITEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DNET_INTERNAL_MODE_FCEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DNET_INTERNAL_MODE_RXEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DNET_INTERNAL_MODE_TXEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* MAC-CORE RXTX CONTROL REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SYSTEM CONTROL REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DNET_SYS_CTL_SENDPAUSE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* TX STATUS REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* INTERRUPT SOURCE REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DNET_INTR_SRC_PHY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* INTERRUPT ENABLE REGISTER FIELDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DNET_INTR_ENB_RX_ERROR (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* default values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * almost empty = less than one full sized ethernet frame (no jumbo) inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * the fifo almost full = can write less than one full sized ethernet frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * (no jumbo) inside the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DNET_CFG_TX_FIFO_FULL_THRES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DNET_CFG_RX_FIFO_FULL_THRES 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Capabilities. Used by the driver to know the capabilities that the ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * controller inside the FPGA have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DNET_HAS_MDIO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DNET_HAS_IRQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DNET_HAS_GIGABIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DNET_HAS_DMA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DNET_HAS_MII (1 << 4) /* or GMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DNET_HAS_RMII (1 << 5) /* or RGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DNET_CAPS_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DNET_FIFO_TX_DATA_AE_TH 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Hardware-collected statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dnet_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 rx_pkt_ignr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 rx_len_chk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 rx_lng_frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 rx_shrt_frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 rx_ipg_viol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 rx_crc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 rx_ok_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 rx_ctl_frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 rx_pause_frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 rx_multicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 rx_broadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 rx_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 rx_pre_shrink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 rx_drib_nib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 rx_unsup_opcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 tx_unicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 tx_pause_frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 tx_multicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 tx_brdcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 tx_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 tx_bad_fcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 tx_jumbo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dnet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dnet_stats hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int capabilities; /* read from FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* PHY stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif /* _DNET_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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