^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Written 1999-2000 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Drivers based on or derived from this code fall under the GPL and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) retain the authorship, copyright and license notice. This file is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) a complete program and may only be used when the entire operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) system is licensed under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The author may be reached as becker@scyld.com, or C/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Scyld Computing Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 410 Severn Ave., Suite 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Annapolis MD 21403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Support and updates available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) http://www.scyld.com/network/sundance.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [link no longer provides useful info -jgarzik]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Archives of the mailing list are still available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) https://www.beowulf.org/pipermail/netdrivers/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_NAME "sundance"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* The user-configurable values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) These may be modified when a driver module is loaded.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Typical is a 64 element hash table based on the Ethernet CRC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const int multicast_filter_limit = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Setting to > 1518 effectively disables this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) This chip can receive into offset buffers, so the Alpha does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) need a copy-align. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int flowctrl=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* media[] specifies the media type the NIC operates at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) autosense Autosensing active media.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 10mbps_hd 10Mbps half duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 10mbps_fd 10Mbps full duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 100mbps_hd 100Mbps half duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 100mbps_fd 100Mbps full duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0 Autosensing active media.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1 10Mbps half duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 2 10Mbps full duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 3 100Mbps half duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 4 100Mbps full duplex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX_UNITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static char *media[MAX_UNITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Operational parameters that are set at compile time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Keep the ring sizes a power of two for compile efficiency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) The compiler will convert <unsigned>'%'<2^N> into a bit mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Making the Tx ring too large decreases the effectiveness of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bonding and packet priority, and more than 128 requires modifying the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Tx error recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Large receive rings merely waste memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TX_RING_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RX_RING_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RX_BUDGET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Operational parameters that usually are not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Time in jiffies before concluding the transmitter is hung. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TX_TIMEOUT (4*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Include files, designed to support most kernel versions 2.0.0 and later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <asm/processor.h> /* Processor type for cache alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) module_param(rx_copybreak, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) module_param_array(media, charp, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) module_param(flowctrl, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Theory of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) I. Board Compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) This driver is designed for the Sundance Technologies "Alta" ST201 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) II. Board-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) III. Driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IIIa. Ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) This driver uses two statically allocated fixed-size descriptor lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) formed into rings by a branch from the final descriptor to the beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Some chips explicitly use only 2^N sized rings, while others use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 'next descriptor' pointer that the driver forms into rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) IIIb/c. Transmit/Receive Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) This driver uses a zero-copy receive and transmit scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) The driver allocates full frame size skbuffs for the Rx ring buffers at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) open() time and passes the skb->data field to the chip as receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) a fresh skbuff is allocated and the frame is copied to the new skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) When the incoming frame is larger, the skbuff is passed directly up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) protocol stack. Buffers consumed this way are replaced by newly allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) skbuffs in a later phase of receives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) The RX_COPYBREAK value is chosen to trade-off the memory wasted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) using a full-sized skbuff for small frames vs. the copying costs of larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) frames. New boards are typically used in generously configured machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) and the underfilled buffers have negligible impact compared to the benefit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) a single allocation size, so the default value of zero results in never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) copying packets. When copying is done, the cost is usually mitigated by using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) a combined copy/checksum routine. Copying also preloads the cache, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) most useful with small frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) A subtle aspect of the operation is that the IP header at offset 14 in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ethernet frame isn't longword aligned for further processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) Unaligned buffers are permitted by the Sundance hardware, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) frames are received into the skbuff at an offset of "+2", 16-byte aligning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) the IP header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IIId. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) The driver runs as two independent, single-threaded flows of control. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) is the send-packet routine, which enforces single-threaded use by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev->tbusy flag. The other thread is the interrupt handler, which is single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) threaded by the hardware and interrupt handling software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) The send packet thread has partial control over the Tx ring and 'dev->tbusy'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) queue slot is empty, it clears the tbusy flag when finished otherwise it sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) the 'lp->tx_full' flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) The interrupt handler has exclusive control over the Rx ring and records stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) from the Tx ring. After reaping the stats, it marks the Tx queue entry as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clears both the tx_full and tbusy flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IV. Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IVb. References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) The Sundance ST201 datasheet, preliminary version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) The Kendin KS8723 datasheet, preliminary version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) The ICplus IP100 datasheet, preliminary version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) http://www.scyld.com/expert/100mbps.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) http://www.scyld.com/expert/NWay.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IVc. Errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Work-around for Kendin chip bugs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifndef CONFIG_SUNDANCE_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define USE_IO_OPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct pci_device_id sundance_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) netdev_io_size = 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct pci_id_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct pci_id_info pci_id_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {"D-Link DFE-550TX FAST Ethernet Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {"D-Link DFE-580TX 4 port Server Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {"D-Link DFE-530TXS FAST Ethernet Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {"D-Link DL10050-based FAST Ethernet Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {"Sundance Technology Alta"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { } /* terminate list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* This driver was written to use PCI memory space, however x86-oriented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hardware often uses I/O space accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Offsets to the device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) Unlike software-only systems, device drivers interact with complex hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) It's not useful to define symbolic names for every register bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) device. The name can only partially document the semantics and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) the driver longer and more difficult to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) In general, only the important configuration values or bits changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) multiple times should be defined symbolically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum alta_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DMACtrl = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TxListPtr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TxDMABurstThresh = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TxDMAUrgentThresh = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TxDMAPollPeriod = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) RxDMAStatus = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) RxListPtr = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DebugCtrl0 = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DebugCtrl1 = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) RxDMABurstThresh = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) RxDMAUrgentThresh = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) RxDMAPollPeriod = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LEDCtrl = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ASICCtrl = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EEData = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) EECtrl = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FlashAddr = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FlashData = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) WakeEvent = 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TxStatus = 0x46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) TxFrameId = 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DownCounter = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IntrClear = 0x4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IntrEnable = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IntrStatus = 0x4e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MACCtrl0 = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MACCtrl1 = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) StationAddr = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MaxFrameSize = 0x5A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) RxMode = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MIICtrl = 0x5e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MulticastFilter0 = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MulticastFilter1 = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RxOctetsLow = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RxOctetsHigh = 0x6a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) TxOctetsLow = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) TxOctetsHigh = 0x6e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TxFramesOK = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RxFramesOK = 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) StatsCarrierError = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) StatsLateColl = 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) StatsMultiColl = 0x76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) StatsOneColl = 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) StatsTxDefer = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) RxMissed = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) StatsTxXSDefer = 0x7a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) StatsTxAbort = 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) StatsBcastTx = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) StatsBcastRx = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) StatsMcastTx = 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) StatsMcastRx = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Aliased and bogus values! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) RxStatus = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ASIC_HI_WORD(x) ((x) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) enum ASICCtrl_HiWord_bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GlobalReset = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RxReset = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) TxReset = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DMAReset = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FIFOReset = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) NetworkReset = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) HostReset = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ResetBusy = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Bits in the interrupt status/mask registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enum intr_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IntrDrvRqst=0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) StatsMax=0x0080, LinkChange=0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Bits in the RxMode register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum rx_mode_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Bits in MACCtrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum mac_ctrl0_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum mac_ctrl1_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Bits in WakeEvent register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum wake_event_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) WakePktEnable = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MagicPktEnable = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) LinkEventEnable = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) WolEnable = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* The Rx and Tx buffer descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Note that using only 32 bit fields simplifies conversion to big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) architectures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct netdev_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __le32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct desc_frag { __le32 addr, length; } frag[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Bits in netdev_desc.status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enum desc_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DescOwn=0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DescEndPacket=0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DescEndRing=0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) LastFrag=0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DescIntrOnTx=0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DescIntrOnDMADone=0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DisableAlign = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PRIV_ALIGN 15 /* Required alignment mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) within the structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MII_CNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct netdev_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Descriptor rings first for alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct netdev_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct netdev_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct sk_buff* rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct sk_buff* tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct timer_list timer; /* Media monitoring timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct net_device *ndev; /* backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* ethtool extra stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 tx_multiple_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u64 tx_single_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u64 tx_late_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u64 tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u64 tx_deferred_excessive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u64 tx_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 tx_bcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u64 rx_bcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u64 tx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u64 rx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } xstats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Frequently used values: keep some adjacent for cache effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int rx_buf_sz; /* Based on MTU+slack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct netdev_desc *last_tx; /* Last Tx descriptor used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int cur_tx, dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* These values are keep track of the transceiver/media in use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int flowctrl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int default_port:4; /* Last dev->if_port value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int an_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int wol_enabled:1; /* Wake on LAN enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct tasklet_struct rx_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct tasklet_struct tx_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int cur_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Multicast and receive mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spinlock_t mcastlock; /* SMP lock multicast updates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 mcast_filter[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* MII transceiver section. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int mii_preamble_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spinlock_t statlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* The station address location in the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define EEPROM_SA_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) IntrDrvRqst | IntrTxDone | StatsMax | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) LinkChange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int change_mtu(struct net_device *dev, int new_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int eeprom_read(void __iomem *ioaddr, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int mdio_read(struct net_device *dev, int phy_id, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int mdio_wait_link(struct net_device *dev, int wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int netdev_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void check_duplex(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void netdev_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void init_ring(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int reset_tx (struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static irqreturn_t intr_handler(int irq, void *dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void rx_poll(struct tasklet_struct *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void tx_poll(struct tasklet_struct *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void refill_rx (struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void netdev_error(struct net_device *dev, int intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void netdev_error(struct net_device *dev, int intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void set_rx_mode(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int __set_mac_addr(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int sundance_set_mac_addr(struct net_device *dev, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct net_device_stats *get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int netdev_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct ethtool_ops ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *ioaddr = np->base + ASICCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int countdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* ST201 documentation states ASICCtrl is a 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* ST201 documentation states reset can take up to 1 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) countdown = 10 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) while (ioread32 (ioaddr) & (ResetBusy << 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (--countdown == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void sundance_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) disable_irq(np->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) intr_handler(np->pci_dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) enable_irq(np->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct net_device_ops netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .ndo_open = netdev_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ndo_stop = netdev_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .ndo_start_xmit = start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ndo_get_stats = get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .ndo_set_rx_mode = set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ndo_do_ioctl = netdev_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .ndo_tx_timeout = tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .ndo_change_mtu = change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .ndo_set_mac_address = sundance_set_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .ndo_poll_controller = sundance_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int sundance_probe1(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct netdev_private *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int chip_idx = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 mii_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void *ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dma_addr_t ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #ifdef USE_IO_OPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int bar = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int phy, phy_end, phy_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (pci_enable_device(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev = alloc_etherdev(sizeof(*np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (pci_request_regions(pdev, DRV_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto err_out_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ioaddr = pci_iomap(pdev, bar, netdev_io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto err_out_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ((__le16 *)dev->dev_addr)[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) np->ndev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) np->base = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) np->pci_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) np->chip_id = chip_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) np->msg_enable = (1 << debug) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spin_lock_init(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_lock_init(&np->statlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tasklet_setup(&np->rx_tasklet, rx_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tasklet_setup(&np->tx_tasklet, tx_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &ring_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!ring_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto err_out_cleardev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) np->tx_ring = (struct netdev_desc *)ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) np->tx_ring_dma = ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &ring_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!ring_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto err_out_unmap_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) np->rx_ring = (struct netdev_desc *)ring_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) np->rx_ring_dma = ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) np->mii_if.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) np->mii_if.mdio_read = mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) np->mii_if.mdio_write = mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) np->mii_if.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) np->mii_if.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* The chip-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev->netdev_ops = &netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev->ethtool_ops = ðtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev->watchdog_timeo = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* MTU range: 68 - 8191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev->min_mtu = ETH_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev->max_mtu = 8191;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) i = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto err_out_unmap_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev->name, pci_id_tbl[chip_idx].name, ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev->dev_addr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) np->phys[0] = 1; /* Default setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) np->mii_preamble_required++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * It seems some phys doesn't deal well with address 0 being accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) phy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) phy_end = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) phy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int phyx = phy & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int mii_status = mdio_read(dev, phyx, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (mii_status != 0xffff && mii_status != 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) np->phys[phy_idx++] = phyx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if ((mii_status & 0x0040) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) np->mii_preamble_required++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) printk(KERN_INFO "%s: MII PHY found at address %d, status "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "0x%4.4x advertising %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev->name, phyx, mii_status, np->mii_if.advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) np->mii_preamble_required--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (phy_idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev->name, ioread32(ioaddr + ASICCtrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto err_out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) np->mii_if.phy_id = np->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Parse override configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) np->an_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (card_idx < MAX_UNITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (media[card_idx] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) np->an_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) strcmp (media[card_idx], "4") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) np->speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) np->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) strcmp (media[card_idx], "3") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) np->speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) np->mii_if.full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) strcmp (media[card_idx], "2") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) np->speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) np->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) strcmp (media[card_idx], "1") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) np->speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) np->mii_if.full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) np->an_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (flowctrl == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) np->flowctrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Fibre PHY? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Default 100Mbps Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (np->an_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) np->speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) np->mii_if.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) np->an_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Reset PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mdelay (300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* If flow control enabled, we need to advertise it.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (np->flowctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Force media type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!np->an_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mii_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) printk (KERN_INFO "Override speed=%d, %s duplex\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) np->speed, np->mii_if.full_duplex ? "Full" : "Half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Perhaps move the reset here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Reset the chip to erase previous misconfiguration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (netif_msg_hw(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) sundance_reset(dev, 0x00ff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (netif_msg_hw(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) card_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err_out_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) err_out_unmap_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) np->rx_ring, np->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) err_out_unmap_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) np->tx_ring, np->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) err_out_cleardev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pci_iounmap(pdev, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) err_out_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) err_out_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) free_netdev (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int change_mtu(struct net_device *dev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define eeprom_delay(ee_addr) ioread32(ee_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int eeprom_read(void __iomem *ioaddr, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int boguscnt = 10000; /* Typical 1900 ticks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) eeprom_delay(ioaddr + EECtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ioread16(ioaddr + EEData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) } while (--boguscnt > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* MII transceiver control section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) Read and write the MII registers using software-generated serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MDIO protocol. See the MII specifications or DP83840A data sheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) met by back-to-back 33Mhz PCI cycles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define mdio_delay() ioread8(mdio_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) enum mii_reg_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MDIO_EnbIn (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define MDIO_WRITE0 (MDIO_EnbOutput)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Generate the preamble required for initial synchronization and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) a few older transceivers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void mdio_sync(void __iomem *mdio_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Establish sync by sending at least 32 logic ones. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) while (--bits >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) iowrite8(MDIO_WRITE1, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int mdio_read(struct net_device *dev, int phy_id, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) void __iomem *mdio_addr = np->base + MIICtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int i, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (np->mii_preamble_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mdio_sync(mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Shift the read command bits out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) for (i = 15; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) iowrite8(dataval, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Read the two transition, 16 data, and wire-idle bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 19; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) iowrite8(MDIO_EnbIn, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return (retval>>1) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void __iomem *mdio_addr = np->base + MIICtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (np->mii_preamble_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mdio_sync(mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Shift the command bits out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 31; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) iowrite8(dataval, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Clear out extra bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (i = 2; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) iowrite8(MDIO_EnbIn, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mdio_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int mdio_wait_link(struct net_device *dev, int wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int bmsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct netdev_private *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) phy_id = np->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) bmsr = mdio_read(dev, phy_id, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (bmsr & 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } while (--wait > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int netdev_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) const int irq = np->pci_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) sundance_reset(dev, 0x00ff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (netif_msg_ifup(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) printk(KERN_DEBUG "%s: netdev_open() irq %d\n", dev->name, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* The Tx list pointer is written as packets are queued. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Initialize other registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __set_mac_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #if IS_ENABLED(CONFIG_VLAN_8021Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (dev->mtu > 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Configure the PCI bus bursts and FIFO thresholds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (dev->if_port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev->if_port = np->default_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) spin_lock_init(&np->mcastlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) iowrite16(0, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) iowrite16(0, ioaddr + DownCounter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Set the chip to poll every N*320nsec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) iowrite8(100, ioaddr + RxDMAPollPeriod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) iowrite8(127, ioaddr + TxDMAPollPeriod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Fix DFE-580TX packet drop issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (np->pci_dev->revision >= 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) iowrite8(0x01, ioaddr + DebugCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) spin_lock_irqsave(&np->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) reset_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) spin_unlock_irqrestore(&np->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Disable Wol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) iowrite8(ioread8(ioaddr + WakeEvent) | 0x00, ioaddr + WakeEvent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) np->wol_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (netif_msg_ifup(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "MAC Control %x, %4.4x %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ioread32(ioaddr + MACCtrl0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Set the timer to check for link beat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) timer_setup(&np->timer, netdev_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) np->timer.expires = jiffies + 3*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) add_timer(&np->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Enable interrupts by setting the interrupt mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static void check_duplex(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int negotiated = mii_lpa & np->mii_if.advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Force media */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!np->an_enable || mii_lpa == 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (np->mii_if.full_duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ioaddr + MACCtrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Autonegotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (np->mii_if.full_duplex != duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) np->mii_if.full_duplex = duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (netif_msg_link(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "negotiated capability %4.4x.\n", dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) duplex ? "full" : "half", np->phys[0], negotiated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void netdev_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct netdev_private *np = from_timer(np, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct net_device *dev = np->mii_if.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int next_tick = 10*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (netif_msg_timer(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "Tx %x Rx %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev->name, ioread16(ioaddr + IntrEnable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) check_duplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) np->timer.expires = jiffies + next_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) add_timer(&np->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static void tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) tasklet_disable(&np->tx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) iowrite16(0, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "TxFrameId %2.2x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ioread8(ioaddr + TxFrameId));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) for (i=0; i<TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) le32_to_cpu(np->tx_ring[i].next_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) le32_to_cpu(np->tx_ring[i].status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) le32_to_cpu(np->tx_ring[i].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) le32_to_cpu(np->tx_ring[i].frag[0].length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ioread32(np->base + TxListPtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) netif_queue_stopped(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) np->cur_tx, np->cur_tx % TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) spin_lock_irqsave(&np->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Stop and restart the chip's Tx processes . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) reset_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) spin_unlock_irqrestore(&np->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev->if_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) tasklet_enable(&np->tx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void init_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) np->cur_rx = np->cur_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) np->dirty_rx = np->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) np->cur_task = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Initialize all Rx descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) np->rx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) np->rx_ring[i].frag[0].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) np->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Fill in the Rx buffers. Handle allocation failure gracefully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct sk_buff *skb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) netdev_alloc_skb(dev, np->rx_buf_sz + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) np->rx_skbuff[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) skb_reserve(skb, 2); /* 16 byte align the IP header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) np->rx_ring[i].frag[0].addr = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dma_map_single(&np->pci_dev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) np->rx_buf_sz, DMA_FROM_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (dma_mapping_error(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) np->rx_ring[i].frag[0].addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) np->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) np->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) np->tx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void tx_poll(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct netdev_private *np = from_tasklet(np, t, tx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned head = np->cur_task % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct netdev_desc *txdesc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Chain the next pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int entry = np->cur_task % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) txdesc = &np->tx_ring[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (np->last_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) entry*sizeof(struct netdev_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) np->last_tx = txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Indicate the latest descriptor of tx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) txdesc->status |= cpu_to_le32(DescIntrOnTx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ioread32 (np->base + TxListPtr) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) np->base + TxListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) start_tx (struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct netdev_desc *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) unsigned entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Calculate the next Tx descriptor entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) entry = np->cur_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) np->tx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) txdesc = &np->tx_ring[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) txdesc->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) txdesc->frag[0].addr = cpu_to_le32(dma_map_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) skb->data, skb->len, DMA_TO_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (dma_mapping_error(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) txdesc->frag[0].addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto drop_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* Increment cur_tx before tasklet_schedule() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) np->cur_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Schedule a tx_poll() task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) tasklet_schedule(&np->tx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* On some architectures: explicitly flush cache lines here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) !netif_queue_stopped(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) netif_stop_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (netif_msg_tx_queued(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) printk (KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "%s: Transmit frame #%d queued in slot %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev->name, np->cur_tx, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) drop_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) np->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Reset hardware tx and free all of tx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) reset_tx (struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Reset tx logic, TxListPtr will be cleaned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) iowrite16 (TxDisable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* free all tx skbuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) np->tx_ring[i].next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) skb = np->tx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) le32_to_cpu(np->tx_ring[i].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) np->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) np->cur_tx = np->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) np->cur_task = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) np->last_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) iowrite8(127, ioaddr + TxDMAPollPeriod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* The interrupt handler cleans up after the Tx thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) and schedule a Rx thread work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static irqreturn_t intr_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct net_device *dev = (struct net_device *)dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int hw_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int intr_status = ioread16(ioaddr + IntrStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) iowrite16(intr_status, ioaddr + IntrStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (netif_msg_intr(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev->name, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!(intr_status & DEFAULT_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (intr_status & (IntrRxDMADone)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (np->budget < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) np->budget = RX_BUDGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) tasklet_schedule(&np->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (intr_status & (IntrTxDone | IntrDrvRqst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) tx_status = ioread16 (ioaddr + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (netif_msg_tx_done(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ("%s: Transmit status is %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev->name, tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (tx_status & 0x1e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (netif_msg_tx_err(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) printk("%s: Transmit error status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev->name, tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (tx_status & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (tx_status & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (tx_status & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (tx_status & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ** This reset has been verified on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ** DFE-580TX boards ! phdm@macqel.be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (tx_status & 0x10) { /* TxUnderrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Restart Tx FIFO and transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* No need to reset the Tx pointer here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* Restart the Tx. Need to make sure tx enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) i = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } while (--i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Yup, this is a documentation bug. It cost me *hours*. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) iowrite16 (0, ioaddr + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (tx_cnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) iowrite32(5000, ioaddr + DownCounter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) tx_status = ioread16 (ioaddr + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) hw_frame_id = (tx_status >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) hw_frame_id = ioread8(ioaddr + TxFrameId);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (np->pci_dev->revision >= 0x14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) spin_lock(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) int entry = np->dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) int sw_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sw_frame_id = (le32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) np->tx_ring[entry].status) >> 2) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (sw_frame_id == hw_frame_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) !(le32_to_cpu(np->tx_ring[entry].status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) & 0x00010000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (sw_frame_id == (hw_frame_id + 1) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) TX_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) skb = np->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Free the original skb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) le32_to_cpu(np->tx_ring[entry].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_consume_skb_irq(np->tx_skbuff[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) np->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) np->tx_ring[entry].frag[0].addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) np->tx_ring[entry].frag[0].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) spin_unlock(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_lock(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int entry = np->dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!(le32_to_cpu(np->tx_ring[entry].status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) & 0x00010000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) skb = np->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Free the original skb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) le32_to_cpu(np->tx_ring[entry].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_consume_skb_irq(np->tx_skbuff[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) np->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) np->tx_ring[entry].frag[0].addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) np->tx_ring[entry].frag[0].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) spin_unlock(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (netif_queue_stopped(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* The ring is no longer full, clear busy flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) netif_wake_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Abnormal error summary/uncommon events handlers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) netdev_error(dev, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (netif_msg_intr(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dev->name, ioread16(ioaddr + IntrStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static void rx_poll(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct netdev_private *np = from_tasklet(np, t, rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct net_device *dev = np->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int entry = np->cur_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int boguscnt = np->budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* If EOP is set on the next entry, it's a new packet. Send it up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct netdev_desc *desc = &(np->rx_ring[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u32 frame_status = le32_to_cpu(desc->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (--boguscnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) goto not_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (!(frame_status & DescOwn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (netif_msg_rx_status(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) frame_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (frame_status & 0x001f4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* There was a error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (netif_msg_rx_err(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) frame_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (frame_status & 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (frame_status & 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (frame_status & 0x00060000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (frame_status & 0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (frame_status & 0x00100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) printk(KERN_WARNING "%s: Oversized Ethernet frame,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) " status %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev->name, frame_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #ifndef final_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (netif_msg_rx_status(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ", bogus_cnt %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pkt_len, boguscnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Check if the packet is long enough to accept without copying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) to a minimally-sized skbuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (pkt_len < rx_copybreak &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) skb_reserve(skb, 2); /* 16 byte align the IP header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dma_sync_single_for_cpu(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) le32_to_cpu(desc->frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) np->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) dma_sync_single_for_device(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) le32_to_cpu(desc->frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) np->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) le32_to_cpu(desc->frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) np->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) skb_put(skb = np->rx_skbuff[entry], pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) np->rx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) entry = (entry + 1) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) received++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) np->cur_rx = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) refill_rx (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) np->budget -= received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) not_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) np->cur_rx = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) refill_rx (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (!received)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) received = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) np->budget -= received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (np->budget <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) np->budget = RX_BUDGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) tasklet_schedule(&np->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static void refill_rx (struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Refill the Rx ring buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) entry = np->dirty_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (np->rx_skbuff[entry] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) skb = netdev_alloc_skb(dev, np->rx_buf_sz + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) np->rx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break; /* Better luck next round. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) np->rx_ring[entry].frag[0].addr = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dma_map_single(&np->pci_dev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) np->rx_buf_sz, DMA_FROM_DEVICE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (dma_mapping_error(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) np->rx_ring[entry].frag[0].addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_kfree_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) np->rx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* Perhaps we need not reset this field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) np->rx_ring[entry].frag[0].length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) cpu_to_le32(np->rx_buf_sz | LastFrag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) np->rx_ring[entry].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static void netdev_error(struct net_device *dev, int intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u16 mii_ctl, mii_advertise, mii_lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (intr_status & LinkChange) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (mdio_wait_link(dev, 10) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) printk(KERN_INFO "%s: Link up\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (np->an_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mii_advertise = mdio_read(dev, np->phys[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mii_advertise &= mii_lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) printk(KERN_INFO "%s: Link changed: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (mii_advertise & ADVERTISE_100FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) np->speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) printk("100Mbps, full duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) } else if (mii_advertise & ADVERTISE_100HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) np->speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) printk("100Mbps, half duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) } else if (mii_advertise & ADVERTISE_10FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) np->speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) printk("10Mbps, full duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) } else if (mii_advertise & ADVERTISE_10HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) np->speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) printk("10Mbps, half duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) np->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) printk(KERN_INFO "%s: Link changed: %dMbps ,",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev->name, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) printk("%s duplex.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) (mii_ctl & BMCR_FULLDPLX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) check_duplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (np->flowctrl && np->mii_if.full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ioaddr + MulticastFilter1+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ioaddr + MACCtrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) printk(KERN_INFO "%s: Link down\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (intr_status & StatsMax) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) get_stats(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (intr_status & IntrPCIErr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev->name, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* We must do a global reset of DMA to continue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct net_device_stats *get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) u8 late_coll, single_coll, mult_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) spin_lock_irqsave(&np->statlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* The chip only need report frame silently dropped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) dev->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dev->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) mult_coll = ioread8(ioaddr + StatsMultiColl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) np->xstats.tx_multiple_collisions += mult_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) single_coll = ioread8(ioaddr + StatsOneColl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) np->xstats.tx_single_collisions += single_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) late_coll = ioread8(ioaddr + StatsLateColl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) np->xstats.tx_late_collisions += late_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev->stats.collisions += mult_coll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) + single_coll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) + late_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) np->xstats.tx_deferred += ioread8(ioaddr + StatsTxDefer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) np->xstats.tx_deferred_excessive += ioread8(ioaddr + StatsTxXSDefer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) np->xstats.tx_aborted += ioread8(ioaddr + StatsTxAbort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) np->xstats.tx_bcasts += ioread8(ioaddr + StatsBcastTx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) np->xstats.rx_bcasts += ioread8(ioaddr + StatsBcastRx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) np->xstats.tx_mcasts += ioread8(ioaddr + StatsMcastTx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) np->xstats.rx_mcasts += ioread8(ioaddr + StatsMcastRx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) spin_unlock_irqrestore(&np->statlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static void set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u16 mc_filter[4]; /* Multicast hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) u32 rx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) memset(mc_filter, 0xff, sizeof(mc_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) (dev->flags & IFF_ALLMULTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* Too many to match, or accept all multicasts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) memset(mc_filter, 0xff, sizeof(mc_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) } else if (!netdev_mc_empty(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) int crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) memset (mc_filter, 0, sizeof (mc_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) crc = ether_crc_le(ETH_ALEN, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (crc & 0x80000000) index |= 1 << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) mc_filter[index/16] |= (1 << (index % 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (np->mii_if.full_duplex && np->flowctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) mc_filter[3] |= 0x0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) iowrite8(rx_mode, ioaddr + RxMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static int __set_mac_addr(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) u16 addr16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) iowrite16(addr16, np->base + StationAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) iowrite16(addr16, np->base + StationAddr+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) iowrite16(addr16, np->base + StationAddr+4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* Invoked with rtnl_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static int sundance_set_mac_addr(struct net_device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) const struct sockaddr *addr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!is_valid_ether_addr(addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) __set_mac_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) const char name[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } sundance_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) { "tx_multiple_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) { "tx_single_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) { "tx_late_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) { "tx_deferred" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) { "tx_deferred_excessive" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) { "tx_aborted" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) { "tx_bcasts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) { "rx_bcasts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) { "tx_mcasts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) { "rx_mcasts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int check_if_running(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static int get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) mii_ethtool_get_link_ksettings(&np->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static int set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) res = mii_ethtool_set_link_ksettings(&np->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static int nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return mii_nway_restart(&np->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static u32 get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return mii_link_ok(&np->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static u32 get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return np->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static void set_msglevel(struct net_device *dev, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) np->msg_enable = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void get_strings(struct net_device *dev, u32 stringset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (stringset == ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) memcpy(data, sundance_stats, sizeof(sundance_stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static int get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) switch (sset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return ARRAY_SIZE(sundance_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static void get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) get_stats(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) data[i++] = np->xstats.tx_multiple_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) data[i++] = np->xstats.tx_single_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) data[i++] = np->xstats.tx_late_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) data[i++] = np->xstats.tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) data[i++] = np->xstats.tx_deferred_excessive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) data[i++] = np->xstats.tx_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) data[i++] = np->xstats.tx_bcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) data[i++] = np->xstats.rx_bcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) data[i++] = np->xstats.tx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) data[i++] = np->xstats.rx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static void sundance_get_wol(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) u8 wol_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) wol->supported = (WAKE_PHY | WAKE_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (!np->wol_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) wol_bits = ioread8(ioaddr + WakeEvent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (wol_bits & MagicPktEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) wol->wolopts |= WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (wol_bits & LinkEventEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) wol->wolopts |= WAKE_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static int sundance_set_wol(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u8 wol_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (!device_can_wakeup(&np->pci_dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) np->wol_enabled = !!(wol->wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) wol_bits = ioread8(ioaddr + WakeEvent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) wol_bits &= ~(WakePktEnable | MagicPktEnable |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) LinkEventEnable | WolEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (np->wol_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (wol->wolopts & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) wol_bits |= (MagicPktEnable | WolEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (wol->wolopts & WAKE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) wol_bits |= (LinkEventEnable | WolEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) iowrite8(wol_bits, ioaddr + WakeEvent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) device_set_wakeup_enable(&np->pci_dev->dev, np->wol_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define sundance_get_wol NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define sundance_set_wol NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const struct ethtool_ops ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .begin = check_if_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .get_drvinfo = get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .nway_reset = nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .get_link = get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .get_wol = sundance_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .set_wol = sundance_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .get_msglevel = get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .set_msglevel = set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .get_strings = get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .get_sset_count = get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .get_ethtool_stats = get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .get_link_ksettings = get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .set_link_ksettings = set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) spin_lock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) spin_unlock_irq(&np->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static int netdev_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* Wait and kill tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) tasklet_kill(&np->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) tasklet_kill(&np->tx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) np->cur_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) np->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) np->cur_task = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) np->last_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (netif_msg_ifdown(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) "Rx %4.4x Int %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) dev->name, ioread8(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* Disable interrupts by clearing the interrupt mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) iowrite16(0x0000, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* Disable Rx and Tx DMA for safely release resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) iowrite32(0x500, ioaddr + DMACtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* Stop the chip's Tx and Rx processes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) for (i = 2000; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) ioaddr + ASIC_HI_WORD(ASICCtrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) for (i = 2000; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if ((ioread16(ioaddr + ASIC_HI_WORD(ASICCtrl)) & ResetBusy) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #ifdef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (netif_msg_hw(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) printk(KERN_DEBUG " Tx ring at %8.8x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) (int)(np->tx_ring_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) printk(KERN_DEBUG " #%d desc. %4.4x %8.8x %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) np->tx_ring[i].frag[0].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) printk(KERN_DEBUG " Rx ring %8.8x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) (int)(np->rx_ring_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) np->rx_ring[i].frag[0].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #endif /* __i386__ debugging only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) free_irq(np->pci_dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) del_timer_sync(&np->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* Free all the skbuffs in the Rx queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) np->rx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) skb = np->rx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) le32_to_cpu(np->rx_ring[i].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) np->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) np->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) np->tx_ring[i].next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) skb = np->tx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) dma_unmap_single(&np->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) le32_to_cpu(np->tx_ring[i].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) np->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static void sundance_remove1(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct net_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) np->rx_ring, np->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) np->tx_ring, np->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pci_iounmap(pdev, np->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static int __maybe_unused sundance_suspend(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct netdev_private *np = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) void __iomem *ioaddr = np->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) netdev_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (np->wol_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) iowrite16(RxEnable, ioaddr + MACCtrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) device_set_wakeup_enable(dev_d, np->wol_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static int __maybe_unused sundance_resume(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) err = netdev_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) printk(KERN_ERR "%s: Can't resume interface!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static SIMPLE_DEV_PM_OPS(sundance_pm_ops, sundance_suspend, sundance_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static struct pci_driver sundance_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .id_table = sundance_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .probe = sundance_probe1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .remove = sundance_remove1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .driver.pm = &sundance_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static int __init sundance_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) return pci_register_driver(&sundance_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static void __exit sundance_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pci_unregister_driver(&sundance_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) module_init(sundance_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) module_exit(sundance_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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